JP2012146020A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of continuous signal processing even when a programmable circuit block performing signal processing is faulty.SOLUTION: When an output confirmation circuit 6 determines that a first FPGA 2 is faulty after configuration of a first function of the first FPGA 2, a control circuit 5 configures the first function to a substitute FPGA 3. After confirming that the configuration is normally complete, the control circuit controls a selection circuit 4 to selectively output an output signal of the substitute FPGA 3.

Description

  The present invention relates to a signal processing circuit.

  The function and performance of FPGA (Field Programmable Gate Array) is improving year by year. In addition, the FPGA uses the advantage that the hardware configuration can be flexibly changed by rewriting the program, and is actively used for a part where the hardware configuration is frequently changed or a model for a variety of products. It has been. The FPGA reconfiguration mechanism is a function for changing a circuit inside the FPGA during operation, and is often used in an FPGA mounted on a device that is desired to be operated by switching to a large number of operation modes such as business devices. The endoscope system is one of business devices that are desired to be operated by switching to a large number of operation modes. However, since the endoscope system is a medical device, high reliability is required.

  The endoscope system is a device that processes and displays moving images in real time, and includes a video processor, a scope (imaging means), a light source device, a monitor, and the like. In addition, when the endoscope system is configured to rewrite and operate the FPGA provided in the processor at the time of function change or update, even if any abnormality occurs at the time of rewriting of the FPGA, promptly It is desirable that the endoscope image can be set in a state where it can be observed. Furthermore, it is desired that images captured by the scope be continuously displayed on the monitor even during the FPGA rewriting operation.

  Also, a plurality of reconfigurable programmable logic devices, a means for selectively supplying configuration data to each programmable logic device, and a means for extracting the outputs of the programmable logic devices that are not being configured. An image processing apparatus provided is known (for example, see Patent Document 1).

  FIG. 6 is a diagram illustrating an example of an image calculation processing unit of a conventionally known image processing apparatus. In FIG. 6, the image calculation processing unit 100 includes two PLDs 101 and 102, three ROMs storing configuration data, ROM (A), ROM (B), ROM (C), and three ROM data. Is provided with a selector 103 and a configuration controller 107 for selectively sending any of the above to the PLD 101 or 102. Image data is input in parallel to the PLDs 101 and 102, and image processing is performed by the PLDs 101 and 102, respectively. The configuration controller 107 selects and takes out one of the output signals 108a and 108b of each PLD, and sends it out to, for example, an image memory for storing processed image data, an image calculation processing unit in the next stage, or the like.

  FIG. 7 is a flowchart showing the operation of the conventionally known image calculation processing unit shown in FIG. The operation of a conventionally known image calculation processing unit will be described using this flowchart. In the initial state t0, it is assumed that the ROM (A) configuration data Da is loaded into the PLD 101, and that the image calculation processing A is being executed in the PLD 101 (FIGS. 7A and 7B). As shown in FIG. 7D, the configuration controller 107 selects the output signal 108a from the PLD 101, and selects and outputs the image data subjected to the image calculation processing A.

  Next, when a configuration request specifying a new image processing B is received at time t1, the configuration controller 107 sends data for image processing B to the PLD 102 that has not been configured so far. Load Db. That is, the configuration controller 107 reads the data Db for image processing B from the ROM (B) and loads the data into the PLD 102 via the selector 103 to perform configuration (FIG. 7 (c). )).

  As shown in FIG. 7F, the PLD 102 generates a configuration completion signal 109b when the data Db has been loaded, and sends it to the configuration controller 107. Upon receiving this completion signal 109b, the configuration controller 107 receives the image data to be taken out from the output signal 108a from the PLD 101 and outputs the output signal 108b from the PLD 102 at the time t2 when the image calculation processing A continued in the PLD 101 is separated. Switch to. Therefore, after time t2, as shown in FIG. 7D, the image data subjected to the image processing B is extracted from the configuration controller 107 and sent to the image memory.

  Next, when a request for configuration specifying a new image processing C is received from an external computer at time t3, the configuration controller 107 applies the image processing C for the PLD 101 for which image output is not currently selected. Data Dc is loaded. That is, the configuration controller 107 reads data Dc for image processing C from the ROM (C) and loads the data to the PLD 101 via the selector 103 to perform configuration.

  As shown in FIG. 7E, the PLD 101 generates a configuration completion signal 109a when it has finished loading the data Dc and sends it to the configuration controller 107. Upon receiving this completion signal 109 a, the configuration controller 107 receives the image data to be taken out from the output signal 108 b from the PLD 102 and outputs the output data of the PLD 101 at the time t 4 when the image calculation process B continued in the PLD 102 is separated. Switch to 108a. For this reason, after time t4, as shown in FIG. 7D, the image data subjected to the image processing C is extracted from the configuration controller 107 and sent to the image memory. Thereby, the image pickup apparatus described in Patent Document 1 can continue image processing even during the change time when performing reconfiguration.

JP 2001-291484 A

  However, the image arithmetic processing unit described in Patent Document 1 has a problem that image processing cannot be performed continuously when a PLD that is a programmable circuit block that performs image processing fails. .

  The present invention has been made in view of the above circumstances, and provides a signal processing circuit capable of continuously performing signal processing even when a programmable circuit block performing signal processing fails. With the goal.

  The present invention includes a programmable first circuit block, a programmable second circuit block that can input and output the same input / output signals as the first circuit block, and the first circuit block. A selection circuit that selects and outputs either the output signal or the output signal of the second circuit block, and confirms the output signal of the first circuit block, and whether the first circuit block is faulty An output confirmation circuit for determining whether or not, the first circuit block and the second circuit block have a function of performing configuration, and the first circuit block is configured with the first function If the output confirmation circuit later determines that the first circuit block has failed, the first function is configured in the second circuit block, and the configuration And a control circuit that controls the selection circuit to select and output the output signal of the second circuit block after confirming that the transmission is normally completed. is there.

  In the signal processing circuit of the present invention, the control circuit further includes the second function when the second function is configured in the first circuit block in which the first function is configured. Configuring the second function in the circuit block, and controlling the selection circuit to select and output the output signal of the second circuit block after confirming that the configuration has been normally completed; Thereafter, the second function is configured in the first circuit block, and after confirming that the configuration has been normally completed, the output signal of the first circuit block is selected and output. The selection circuit is controlled.

  In addition, the present invention includes a third circuit block that is programmable, and the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit, The second circuit block can input / output the same input / output signals as those of the first circuit block and the third circuit block, and the selection circuit outputs the output signal of the first circuit block and the first circuit block. One of the output signals of the second circuit block is selected and input as the input signal to the third circuit block, and the control circuit further performs configuration on the third circuit block And when configuring the second function in the first circuit block in which the first function is configured, Selecting the output signal of one circuit block and controlling the selection circuit to input to the third circuit block as the input signal, configuring the second function in the second circuit block, After confirming that the configuration has been normally completed, the selection circuit is controlled so that the output signal of the second circuit block is selected and input as the input signal to the third circuit block. After configuring the second function in the first circuit block and confirming that the configuration has been completed normally, the output signal of the first circuit block is selected and the third circuit is selected. The selection circuit is controlled to input to the block as the input signal, and the third circuit in which the third function is configured is configured. When configuring the fourth function in the block, the selection circuit is controlled so that the output signal of the first circuit block is selected and input as the input signal to the third circuit block; After configuring the fourth function in the second circuit block and confirming that the configuration has been normally completed, the second circuit block is selected by selecting the output signal of the first circuit block. The selection circuit is controlled to be input as the input signal, and then the fourth function is configured in the third circuit block, and after confirming that the configuration is normally completed, The selection circuit is configured to select an output signal of the first circuit block and input the output signal to the third circuit block as the input signal. It is a signal processing circuit characterized by controlling.

  In the signal processing circuit of the present invention, when the control circuit configures the second function in the first circuit block in which the first function is configured, the second circuit After configuring the first function in the block and confirming that the configuration has been normally completed, the selection circuit is controlled to select and output the output signal of the second circuit block, and then The second function is configured in the first circuit block, and the selection is performed so as to select and output the output signal of the first circuit block after confirming that the configuration is normally completed. The circuit is controlled.

  In addition, the present invention includes a third circuit block that is programmable, and the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit, The second circuit block can input / output the same input / output signals as those of the first circuit block and the third circuit block, and the selection circuit outputs the output signal of the first circuit block and the first circuit block. One of the output signals of the second circuit block is selected and input as the input signal to the third circuit block, and the control circuit further performs configuration on the third circuit block And when configuring the second function in the first circuit block in which the first function is configured, Selecting the output signal of one circuit block and controlling the selection circuit to input it as the input signal to the third circuit block, configuring the first function in the second circuit block, After confirming that the configuration has been normally completed, the selection circuit is controlled so that the output signal of the second circuit block is selected and input as the input signal to the third circuit block. After configuring the second function in the first circuit block and confirming that the configuration has been completed normally, the output signal of the first circuit block is selected and the third circuit is selected. The selection circuit is controlled to input to the block as the input signal, and the third circuit in which the third function is configured is configured. When configuring the fourth function in the block, the selection circuit is controlled so that the output signal of the first circuit block is selected and input as the input signal to the third circuit block; After configuring the third function in the second circuit block and confirming that the configuration has been normally completed, the second circuit block is selected by selecting the output signal of the first circuit block. The selection circuit is controlled to be input as the input signal, and then the fourth function is configured in the third circuit block, and after confirming that the configuration is normally completed, The selection circuit is configured to select an output signal of the first circuit block and input the output signal to the third circuit block as the input signal. It is a signal processing circuit characterized by controlling.

  In the signal processing circuit of the present invention, the output confirmation circuit further confirms an output signal of the third circuit block, determines whether or not the third circuit block is faulty, and If the output check circuit determines that the third circuit block is faulty after the third function is configured in the circuit block, the third function is configured in the second circuit block. Then, after confirming that the configuration has been normally completed, the selection circuit is controlled to select and output the output signal of the second circuit block.

  In addition, the present invention includes a third circuit block that is programmable, and the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit, The second circuit block can input / output the same input / output signals as those of the first circuit block and the third circuit block, and the selection circuit outputs the output signal of the first circuit block and the first circuit block. One of the output signals of the second circuit block is selected and input as the input signal to the third circuit block, and the control circuit further performs configuration on the third circuit block And when configuring the second function in the first circuit block in which the first function is configured, The selection circuit is controlled so that an output signal of one circuit block is selected and input to the third circuit block as the input signal, and the first function or the second function is applied to the second circuit block. After configuring the fifth function, which is the minimum function among the functions, and confirming that the configuration has been completed normally, the output signal of the second circuit block is selected and the third circuit is selected. After controlling the selection circuit to input to the block as the input signal, and then configuring the second function in the first circuit block and confirming that the configuration has been completed successfully, Controlling the selection circuit to select an output signal of the first circuit block and input the output signal to the third circuit block as the input signal; When the fourth function is configured in the third circuit block configured with the function 3, the output signal of the first circuit block is selected and the input to the third circuit block. The selection circuit is controlled so as to be input as a signal, and the second function block is configured to configure the third function or the sixth function which is the minimum of the fourth functions, and Control the selection circuit to select the output signal of the first circuit block and input it as the input signal to the second circuit block, and then After configuring the fourth function in the third circuit block and confirming that the configuration is normally completed, The signal processing circuit is characterized in that the selection circuit is controlled so that an output signal of the first circuit block is selected and input to the third circuit block as the input signal.

  In addition, the present invention is programmable, and has a selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block, and the selection unit A third circuit block having the output signal to be output as an input signal is provided, and the second circuit block can input / output the same input / output signal as the first circuit block or the third circuit block. And the selection circuit selects any one of the output signal of the first circuit block, the output signal of the second circuit block, and the output signal of the third circuit block; The control circuit further has a function of implementing the configuration in the third circuit block, and a second circuit in the first circuit block in which the first function is configured. When configuring the function, the selection unit is controlled to select the output signal of the first circuit block and use it as the input signal of the third circuit block. After configuring the second function and confirming that the configuration has been completed normally, the output signal of the second circuit block is selected and used as the input signal of the third circuit block. And then, after configuring the second function in the first circuit block and confirming that the configuration has been completed normally, the output signal of the first circuit block Is selected and used as the input signal of the third circuit block to control the selector, and the third function is configured. When configuring the fourth function in the third circuit block, the selection circuit is controlled to select and output the output signal of the third circuit block to the outside, and the second circuit After configuring the fourth function in the block and confirming that the configuration has been normally completed, the selection circuit is configured to select and output the output signal of the second circuit block to the outside. After that, after configuring the fourth function in the third circuit block and confirming that the configuration has been normally completed, the output signal of the third circuit block is selected and externally selected. The signal processing circuit is characterized in that the selection circuit is controlled so as to output the signal.

  In addition, the present invention is programmable, and has a selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block, and the selection unit A third circuit block having the output signal to be output as an input signal is provided, and the second circuit block can input / output the same input / output signal as the first circuit block or the third circuit block. And the selection circuit selects any one of the output signal of the first circuit block, the output signal of the second circuit block, and the output signal of the third circuit block; The control circuit further has a function of implementing the configuration in the third circuit block, and a second circuit in the first circuit block in which the first function is configured. When configuring the function, the selection unit is controlled to select the output signal of the first circuit block and use it as the input signal of the third circuit block. After configuring the first function and confirming that the configuration has been completed normally, the output signal of the second circuit block is selected and used as the input signal of the third circuit block. And then, after configuring the second function in the first circuit block and confirming that the configuration has been completed normally, the output signal of the first circuit block Is selected and used as the input signal of the third circuit block to control the selector, and the third function is configured. When configuring the fourth function in the third circuit block, the selection circuit is controlled to select and output the output signal of the third circuit block to the outside, and the second circuit After configuring the third function in the block and confirming that the configuration has been normally completed, the selection circuit is configured to select and output the output signal of the second circuit block to the outside. After that, after configuring the fourth function in the third circuit block and confirming that the configuration has been normally completed, the output signal of the third circuit block is selected and externally selected. The signal processing circuit is characterized in that the selection circuit is controlled so as to output the signal.

  Further, the present invention is programmable, and has a first selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block, A third circuit block having the output signal output from the first selection unit as an input signal, wherein the second circuit block has the same input / output as the first circuit block or the third circuit block; A signal can be input / output, and the selection circuit is any one of an output signal of the first circuit block, an output signal of the second circuit block, and an output signal of the third circuit block. The control circuit further has a function of executing the configuration in the third circuit block, and the first circuit block in which the first function is configured is selected and output. When the second function is configured in the memory, the selection unit is controlled to select the output signal of the first circuit block and use it as the input signal of the third circuit block, After configuring the first function or the fifth function, which is the minimum of the second functions, in the second circuit block and confirming that the configuration has been normally completed, 2 selects the output signal of the second circuit block and uses it as the input signal of the third circuit block, and then configures the second function in the first circuit block. After confirming that the configuration has been completed normally, the output signal of the first circuit block is selected as the input signal of the third circuit block. When the fourth function is configured in the third circuit block configured to control the selection unit and the third function is configured, the output signal of the third circuit block is selected. The selection circuit is controlled to output to the outside, and the second function block is configured with the sixth function, which is the minimum function of the third function or the fourth function, and the configuration After selecting the output signal of the second circuit block, the selection circuit is controlled so as to be output to the outside. After that, the third circuit block receives the second signal. 4 is configured, and after confirming that the configuration has been completed normally, the output signal of the third circuit block is selected and output to the outside. The signal processing circuit is characterized in that the selection circuit is controlled so as to operate.

  In the signal processing circuit according to the present invention, the first circuit block and the second circuit block are a field programmable gate array.

  In the signal processing circuit according to the present invention, the first circuit block, the second circuit block, and the third circuit block are a field programmable gate array.

  According to the present invention, when the control circuit determines that the first circuit block has failed after the first function is configured in the first circuit block, the control circuit sets the second circuit block. After configuring the first function and confirming that the configuration has been completed normally, the selection circuit controls to select and output the output signal of the second circuit block.

  Thereby, when the first circuit block fails, the output confirmation circuit can determine that the first circuit block is defective. When the output confirmation circuit determines that the first circuit block has failed, the control circuit configures the first function, which is the same function as the first circuit block, in the second circuit block. Since the selection circuit outputs the output signal processed by the second circuit block, the processing can be continued even when the programmable first circuit block fails.

It is the schematic which showed the structure of the signal processing circuit in the 1st Embodiment of this invention. It is a timing chart which showed the operation timing of the signal processing circuit in a 1st embodiment of the present invention. It is the schematic which showed the structure of the signal processing circuit in the 2nd Embodiment of this invention. It is a timing chart which showed the operation timing of the signal processing circuit in the 3rd embodiment of the present invention. It is the schematic which showed the structure of the signal processing circuit in the 4th Embodiment of this invention. It is the figure which showed an example of the image calculation process part of the image processing apparatus known conventionally. It is the flowchart which showed operation | movement of the image calculation process part known conventionally.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram showing a configuration of a signal processing circuit in the present embodiment. In the illustrated example, the signal processing circuit 1 includes a first FPGA (Field Programmable Gate Array) 2 (first circuit block), an alternative FPGA 3 (second circuit block), a selection circuit 4, and a control circuit 5. Prepare.

  The first FPGA 2 and the alternative FPGA 3 are a type of programmable integrated circuit that can be configured (logic circuit rewriting) by reading configuration data (logic circuit program) stored in a ROM (not shown). In the present embodiment, the signal processing circuit 1 includes an FPGA as a programmable integrated circuit. However, the signal processing circuit 1 is not limited to this, and a programmable integrated circuit such as a PLD (Programmable Logic Device) can be used instead of the FPGA. A circuit may be provided.

  The first FPGA 2 includes an input terminal A to which a signal is input from the outside. The first FPGA 2 performs a process based on the configured functional circuit on the signal input to the input terminal A. The first FPGA 2 includes an output terminal E that outputs a processed signal. The alternative FPGA 3 includes an input terminal A to which the same signal as that input to the input terminal A included in the first FPGA 2 is input. The alternative FPGA 3 performs a process based on the configured functional circuit on the signal input to the input terminal A. The alternative FPGA 3 includes an output terminal G that outputs a processed signal.

  The selection circuit 4 includes an input terminal E to which a signal output from the first FPGA 2 is input, and an input terminal G to which a signal output from the alternative FPGA 3 is input. Further, the selection circuit 4 selects either one of the signal input to the input terminal E (the output signal of the first FPGA 2) and the signal input to the input terminal G (the output signal of the alternative FPGA 3). An output terminal I for outputting to the outside is provided. The selection circuit 4 includes an output confirmation circuit 6. The output confirmation circuit 6 confirms signals input to the input terminal E and the input terminal G of the selection circuit 4 and determines whether or not the first FPGA 2 and the alternative FPGA 3 are out of order. In addition, the output confirmation circuit 6 inputs a result of determining whether or not the first FPGA 2 and the alternative FPGA 3 are out of order to the control circuit 5. The control circuit 5 controls the configuration of the first FPGA 2 and the alternative FPGA 3. The control circuit 5 controls the signal output of the selection circuit 4.

  Next, an operation procedure of the signal processing circuit 1 when the first FPGA 2 fails while the first FPGA 2 configured with the first functional circuit is performing signal processing will be described. In the normal operation of the signal processing circuit 1, it is assumed that the first FPGA 2 is configured with the first functional circuit and the alternative FPGA 3 is not configured with the functional circuit.

  When the signal processing circuit 1 is operating normally, the signal input to the signal processing circuit 1 is input to the input terminal A of the first FPGA 2 and the input terminal A of the alternative FPGA 3. The first FPGA 2 performs signal processing based on the first functional circuit on the signal input to the input terminal A and outputs the signal from the output terminal E. A signal output from the output terminal E is input to the input terminal E of the selection circuit 4. Note that since the functional circuit is not configured in the alternative FPGA 3, the alternative FPGA 3 does not perform processing.

  The selection circuit 4 outputs the signal input to the input terminal E out of the signal input to the input terminal E and the signal input to the input terminal G from the output terminal I to the outside under the control of the control circuit 5. To do. Before the selection circuit 4 selects the output signal of the first FPGA 2 input to the input terminal E and outputs it from the output terminal I, the output confirmation circuit 6 confirms the output signal of the first FPGA 2 and the first FPGA 2 It is determined whether or not there is a failure.

  Here, when the first FPGA 2 fails, the output signal of the first FPGA 2 is different from the normal signal. When the output confirmation circuit 6 confirms the output signal of the first FPGA 2 that is different from the normal one, the output confirmation circuit 6 determines that the first FPGA 2 has failed, and inputs the determination result “first FPGA: failure” to the control circuit 5.

  When the determination result “first FPGA: failure” is input from the output confirmation circuit 6, the control circuit 5 inputs “alternative FPGA configuration start signal: first functional circuit” to the alternative FPGA 3. The alternative FPGA 3 configures the first functional circuit based on “alternative FPGA configuration start signal: first functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the alternative FPGA 3 inputs an “alternative FPGA configuration completion signal” to the control circuit 5. The alternative FPGA 3 performs signal processing based on the first functional circuit on the signal input to the input terminal A and outputs the signal from the output terminal G. A signal output from the output terminal G of the alternative FPGA 3 is input to the input terminal G of the selection circuit 4.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 3, the control circuit 5 determines that the configuration of the alternative FPGA 3 has been normally completed. When the control circuit 5 determines that the configuration of the alternative FPGA 3 is normally completed, the control circuit 5 outputs the signal output from the output terminal E of the first FPGA 2 and input to the input terminal E of the selection circuit 4 and the output terminal G of the alternative FPGA 3. Output signal from the output terminal G of the alternative FPGA 3 and input to the input terminal G of the selection circuit 4 among the signals output from the input terminal G of the selection circuit 4 and selected from the output terminal I. “Selection signal: alternative FPGA” is input to the selection circuit 4 so as to output to the outside. The selection circuit 4 selects a signal output from the output terminal G of the alternative FPGA 3 and input to the input terminal G of the selection circuit 4 based on the input “selection signal: alternative FPGA” and outputs the signal from the output terminal I to the outside. Output to.

  As described above, when the first FPGA 2 fails, the output confirmation circuit 6 can determine that the first FPGA 2 has failed by confirming the output signal of the first FPGA 2. When the output confirmation circuit 6 determines that the first FPGA 2 has failed, the control circuit 5 controls the alternative FPGA 3 to configure the first functional circuit. The control circuit 5 also outputs a signal output from the output terminal E of the first FPGA 2 and input to the input terminal E of the selection circuit 4, and is output from the output terminal G of the alternative FPGA 3 and input to the input terminal G of the selection circuit 4. The selection circuit 4 is controlled so that a signal output from the output terminal G of the alternative FPGA 3 and input to the input terminal G of the selection circuit 4 is selected and output from the output terminal I to the outside. . Therefore, the signal processing circuit 1 can continuously perform signal processing even when the first FPGA 2 fails.

  Next, the operation timing of the signal processing circuit 1 when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit will be described. FIG. 2 is a timing chart showing the operation timing of the signal processing circuit 1 when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit in the present embodiment.

  When the power supply of the device in which the signal processing circuit 1 is mounted is turned on, the system reset signal input to the control circuit 5 is canceled. When the system reset signal is canceled, the control circuit 5 inputs “first FPGA configuration start signal: first functional circuit” to the first FPGA 2 so that the first FPGA 2 configures the first functional circuit. The first FPGA 2 configures the first functional circuit based on “first FPGA configuration start signal: first functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the first FPGA 2 inputs a “first FPGA configuration completion signal” to the control circuit 5.

  When the “first FPGA configuration completion signal” is input from the first FPGA 2, the control circuit 5 determines that the configuration of the first FPGA 2 has been completed normally. When the control circuit 5 determines that the configuration of the first FPGA 2 is normally completed, the control circuit 5 selects the output signal of the first FPGA 2 out of the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected signal to the outside. Then, “selection signal: first FPGA” is input to the selection circuit 4. The selection circuit 4 selects the output signal of the first FPGA 2 based on the input “selection signal: first FPGA” and outputs the selected signal to the outside. Before the selection circuit 4 selects the output signal of the first FPGA 2 and outputs it to the outside (before switching the output), the output confirmation circuit 6 confirms the signal output by the first FPGA 2 and the first FPGA 2 fails. It is determined whether or not.

  Thereby, the signal processing circuit 1 can perform signal processing based on the first functional circuit with the first FPGA 2 on the signal input from the outside, and output the processed signal to the outside.

  When an instruction to change the function circuit of the first FPGA 2 from the first function circuit to the second function circuit is input to the control circuit 5, the control circuit 5 configures the second function circuit in the alternative FPGA 3. As such, “alternative FPGA configuration start signal: second functional circuit” is input to the alternative FPGA 3. The alternative FPGA 3 configures the second functional circuit based on “alternative FPGA configuration start signal: second functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the alternative FPGA 3 inputs an “alternative FPGA configuration completion signal” to the control circuit 5.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 3, the control circuit 5 determines that the configuration of the alternative FPGA 3 has been normally completed. When the control circuit 5 determines that the configuration of the alternative FPGA 3 is normally completed, the control circuit 5 selects the output signal of the alternative FPGA 3 from the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected output signal to the outside. Then, “selection signal: alternative FPGA” is input to the selection circuit 4. The selection circuit 4 selects an output signal of the alternative FPGA 3 based on the inputted “selection signal: alternative FPGA” and outputs the selected signal to the outside. Note that before the selection circuit 4 selects the output signal of the alternative FPGA 3 and outputs it to the outside, the output confirmation circuit 6 checks the signal output by the alternative FPGA 3 and determines whether or not the alternative FPGA 3 has failed. .

  Thereby, the signal processing circuit 1 can perform signal processing based on the second functional circuit with the alternative FPGA 3 on the signal input from the outside, and output the processed signal to the outside.

  Subsequently, the control circuit 5 inputs “first FPGA configuration start signal: second functional circuit” to the first FPGA 2 so that the first FPGA 2 configures the second functional circuit. The first FPGA 2 configures the second functional circuit based on “first FPGA configuration start signal: second functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the first FPGA 2 inputs a “first FPGA configuration completion signal” to the control circuit 5.

  When the “first FPGA configuration completion signal” is input from the first FPGA 2, the control circuit 5 determines that the configuration of the first FPGA 2 has been completed normally. When the control circuit 5 determines that the configuration of the first FPGA 2 is normally completed, the control circuit 5 selects the output signal of the first FPGA 2 out of the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected signal to the outside. Then, “selection signal: first FPGA” is input to the selection circuit 4. The selection circuit 4 selects the output signal of the first FPGA 2 based on the input “selection signal: first FPGA” and outputs the selected signal to the outside. Before the selection circuit 4 selects the output signal of the first FPGA 2 and outputs it to the outside, the output confirmation circuit 6 confirms the signal output by the first FPGA 2 and determines whether or not the first FPGA 2 has failed. .

  Thereby, the signal processing circuit 1 can perform signal processing based on the second functional circuit in the first FPGA 2 with respect to the signal input from the outside, and output the processed signal to the outside.

  The signal processing circuit 1 performs the above-described operation when the functional circuit configured in the first FPGA 2 is changed or updated. For example, when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit, the control circuit 5 first configures the second functional circuit for the alternative FPGA 3. Then, after confirming that this configuration has been completed normally, the control circuit 5 performs control so that the selection circuit 4 selects the output of the alternative FPGA 3 and outputs it to the outside. Next, the control circuit 5 configures the second functional circuit for the first FPGA 2 while performing signal processing with the alternative FPGA 3 instead of the first FPGA 2. Then, after confirming that this configuration has been completed normally, the control circuit 5 performs control so that the selection circuit 4 selects the output of the first FPGA 2 and outputs it to the outside. Thus, since the signal processing can be performed using the alternative FPGA 3 instead of the first FPGA 2 even while the first FPGA 2 is being configured, the signal processing circuit 1 includes a functional circuit that configures the first FPGA 2. Even in the case of updating, the processing can be continued.

  The signal processing circuit 1 configures the second functional circuit in the first FPGA 2 after configuring the second functional circuit in the alternative FPGA 3 and does not continue processing using the alternative FPGA 3. Process. As a result, the signal processing circuit 1 can operate on the normal path (path on which the first FPGA 2 processes signals) even after the functional circuit configured in the first FPGA 2 is changed.

  Further, after the second functional circuit is configured for the alternative FPGA 3, when the output confirmation circuit 6 included in the selection circuit 4 detects a failure of the alternative FPGA 3, the control circuit 5 outputs the output of the selection circuit 4 to the alternative FPGA 3 The output of the first FPGA 2 may be selected and output as it is without switching to the output. As a result, the signal processing circuit 1 can continuously perform processing on the input signal even when a failure occurs in the alternative FPGA 3.

  When the alternative FPGA 3 fails, the control circuit 5 changes the first FPGA 2 to the first FPGA 2 when the function circuit of the first FPGA 2 is to be changed from the first function circuit to the second function circuit even if the processing for the input signal is stopped. By controlling to configure the two-function circuit, the function circuit of the first FPGA 2 can be changed to the second function circuit.

  In addition, after configuring the second functional circuit for the alternative FPGA 3, if any failure occurs in the first FPGA 2 when configuring the second functional circuit for the first FPGA 2, the control circuit 5 outputs the output of the selection circuit 4. Instead of switching to the output of the first FPGA 2, the output of the alternative FPGA 3 may be selected and output as it is. As a result, the signal processing circuit 1 can continuously perform processing on the input signal even when a failure occurs in the first FPGA 2.

  Also, after configuring the second functional circuit for the alternative FPGA 3 and then configuring the second functional circuit for the first FPGA 2, some failure occurs in the first FPGA 2, and the output confirmation circuit 6 confirms the failure in the first FPGA 2. In this case, the control circuit 5 may retry the configuration of the second functional circuit to the first FPGA 2. When the output confirmation circuit 6 confirms that the first FPGA 2 is operating normally, the control circuit 5 may switch the output of the selection circuit 4 to the output of the first FPGA 2. Thus, even when a failure occurs in the first FPGA 2, the functional circuit of the first FPGA 2 can be changed to the second functional circuit by retrying the configuration.

  When retrying the configuration of the second functional circuit to the first FPGA 2, the configuration data may be read again from the same ROM, and a different ROM may be provided separately from the ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 5 retries the configuration of the second functional circuit to the first FPGA 2 is, for example, when the configuration of the second functional circuit to the first FPGA 2 is not normally completed or the output confirmation circuit 6 Is the timing when the failure of the first FPGA 2 is confirmed when it is confirmed whether or not the first FPGA 2 is operating normally. The timing at which the output confirmation circuit 6 confirms whether or not the first FPGA 2 is operating normally is the timing at which the configuration of the second functional circuit to the first FPGA 2 is completed, the blanking period of the vertical synchronization signal, etc. , Periodically in a certain cycle.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a schematic diagram showing the configuration of the signal processing circuit in the present embodiment. In the illustrated example, the signal processing circuit 20 includes a first FPGA 21 (first circuit block), a second FPGA 22 (third circuit block), an alternative FPGA 23 (second circuit block), a selection circuit 24, and a control circuit. Circuit 25. In addition, as shown with a broken line, you may make it further provide 3rd FPGA27.

  The first FPGA 21, the second FPGA 22, the alternative FPGA 23, and the third FPGA 27 are configured by reading configuration data stored in a ROM (not shown) in the same manner as the first FPGA 2 and the alternative FPGA 3 of the first embodiment. This is a type of programmable integrated circuit that can be configured.

  The first FPGA 21 includes an input terminal A to which a signal is input from the outside. The first FPGA 21 performs a process based on the configured functional circuit on the signal input to the input terminal A. The first FPGA 21 includes an output terminal C that outputs a processed signal and an output terminal e.

  The second FPGA 22 includes an input terminal I to which a signal is input from the selection circuit 24 and an input terminal b to which a signal is input from the outside. In addition, the second FPGA 22 performs processing based on the configured functional circuit on the signals input to the input terminal I and the input terminal b. The second FPGA 22 includes an output terminal K that outputs a processed signal and an output terminal d.

  The third FPGA 27 includes an input terminal N to which a signal is input from the selection circuit 24 and an input terminal j to which a signal is input from the outside. In addition, the third FPGA 27 performs processing based on the configured functional circuit on the signals input to the input terminal N and the input terminal j. The third FPGA 27 includes an output terminal M that outputs a processed signal and an output terminal p.

  The alternative FPGA 23 has an input terminal A to which the same signal as the signal input to the input terminal A included in the first FPGA 21 is input, and an input terminal b to which the same signal as the signal input to the input terminal b included in the second FPGA 22 is input. And an input terminal j to which the same signal as the signal input to the input terminal j included in the third FPGA 27 is input. The alternative FPGA 23 receives an input terminal C to which a signal processed by the first FPGA 21 is input, an input terminal K to which a signal processed by the second FPGA 22 is input, and a signal processed by the third FPGA 27 Input terminal M. The alternative FPGA 23 is a functional circuit configured for signals input to the input terminal A, the input terminal b, the input terminal j, the input terminal C, the input terminal K, and the input terminal M. Process based on The alternative FPGA 3 includes an output terminal G and an output terminal g for outputting the processed signal.

  The selection circuit 24 includes an input terminal C and an input terminal e to which a signal output from the first FPGA 21 is input, an input terminal K and an input terminal d to which a signal output from the second FPGA 22 is input, and a signal output from the third FPGA 27. An input terminal M, an input terminal p, an input terminal G, and an input terminal g, to which a signal output from the alternative FPGA 23 is input, are provided. The selection circuit 24 also includes a signal output from the first FPGA 21 (an output signal from the first FPGA 21), a signal output from the second FPGA 22 (an output signal from the second FPGA 22), and a signal output from the third FPGA 27 (an output signal from the third FPGA 27). And an output terminal I that selects and outputs one of the signals output from the alternative FPGA 23 (an output signal of the alternative FPGA 23), an output terminal N, an output terminal H, and an output terminal h. Yes.

  The output confirmation circuit 26 confirms the signal output from the first FPGA 21, the signal output from the second FPGA 22, the signal output from the third FPGA 27, and the signal output from the alternative FPGA 23 and input to the selection circuit 24. Then, it is determined whether or not the second FPGA 22, the third FPGA 27, and the alternative FPGA 23 are out of order. The output confirmation circuit 26 inputs a result of determining whether or not the first FPGA 21, the second FPGA 22, the third FPGA 27, and the alternative FPGA 23 are out of order to the control circuit 25. The control circuit 25 controls the configuration of the first FPGA 21, the second FPGA 22, the third FPGA 27, and the alternative FPGA 23. The control circuit 25 controls the signal output of the selection circuit 24.

  Next, the operation procedure of the signal processing circuit 20 will be described. Hereinafter, an operation procedure when the signal processing circuit 20 operates using the first FPGA 21, the second FPGA 22, and the alternative FPGA 23 will be described as an example. It is assumed that the first functional circuit is configured in the first FPGA 21, the third functional circuit is configured in the second FPGA 22, and the functional circuit is not configured in the alternative FPGA 23.

  When the signal processing circuit 20 is operating normally, the signal input to the signal processing circuit 20 is input to the input terminal A of the first FPGA 21 and the input terminal A of the alternative FPGA 23. The first FPGA 21 performs signal processing based on the first functional circuit on the signal input to the input terminal A and outputs the signal from the output terminal C. A signal output from the output terminal C is input to the input terminal C of the selection circuit 24. Note that since the functional circuit is not configured in the alternative FPGA 23, the alternative FPGA 23 does not perform processing.

  The selection circuit 24 outputs a signal input to the input terminal C from the output terminal I under the control of the control circuit 25. The signal output from the output terminal I is input to the input terminal I of the second FPGA 22. The second FPGA 22 performs signal processing based on the third functional circuit on the signal input to the input terminal I, and outputs the signal from the output terminal K. A signal output from the output terminal K is input to the input terminal K of the selection circuit 24. The selection circuit 24 outputs the signal input to the input terminal K from the output terminal H to the outside under the control of the control circuit 25.

  Next, an operation procedure when the functional circuit of the first FPGA 21 is rewritten from the first functional circuit to the second functional circuit will be described. When the functional circuit of the first FPGA 21 is rewritten from the first functional circuit to the second functional circuit, first, the control circuit 25 causes the alternative FPGA 23 to configure the alternative FPGA configuration in order to configure the second functional circuit. “Start signal: second functional circuit” is input. The alternative FPGA 23 configures the second functional circuit based on “alternative FPGA configuration start signal: second functional circuit” input from the control circuit 25. Then, after the configuration is normally completed, the alternative FPGA 23 inputs an “alternative FPGA configuration completion signal” to the control circuit 25.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 23, the control circuit 25 determines that the configuration of the alternative FPGA 23 has been completed normally. When the control circuit 25 determines that the configuration of the alternative FPGA 23 has been normally completed, the control circuit 25 outputs the signal output from the output terminal C of the first FPGA 21 and input to the input terminal C of the selection circuit 24 and the output terminal G of the alternative FPGA 23. The selection signal is output to the selection circuit 24 so that the signal input to the input terminal G is selected from the signals input to the input terminal G of the selection circuit 24 and output from the output terminal I. : Alternate FPGA-second FPGA ”. The selection circuit 24 selects the signal output from the output terminal G of the alternative FPGA 23 and input to the input terminal G of the selection circuit 24 based on the input “selection signal: alternative FPGA-second FPGA” and outputs an output terminal. Output from I. The signal output from the output terminal I of the selection circuit 24 is input to the second FPGA 22. Before the selection circuit 24 outputs the signal input to the input terminal G from the output terminal I, the output confirmation circuit 26 confirms the signal output from the alternative FPGA 23 to determine whether or not the alternative FPGA 23 has failed. judge.

  Thereby, the signal processing circuit 20 can perform signal processing based on the second functional circuit in the alternative FPGA 23 with respect to the signal input from the outside, and input the processed signal to the second FPGA 22. The signal input to the second FPGA 22 is subjected to the same processing as described above, and is output from the output terminal H of the selection circuit 24 to the outside.

  Subsequently, the control circuit 25 inputs “first FPGA configuration start signal: second functional circuit” to the first FPGA 21 in order to cause the first FPGA 21 to configure the second functional circuit. The first FPGA 21 configures the second functional circuit based on “first FPGA configuration start signal: second functional circuit” input from the control circuit 25. The first FPGA 21 inputs a “first FPGA configuration completion signal” to the control circuit 25 after the configuration is normally completed.

  When the “first FPGA configuration completion signal” is input from the first FPGA 21, the control circuit 25 determines that the configuration of the first FPGA 21 has been normally completed. When the control circuit 25 determines that the configuration of the first FPGA 21 has been normally completed, the control circuit 25 outputs the signal output from the output terminal C of the first FPGA 21 and input to the input terminal C of the selection circuit 24, and the output terminal G of the alternative FPGA 23. The selection signal is output to the selection circuit 24 so that the signal input to the input terminal C is selected from the signals input to the input terminal G of the selection circuit 24 and output from the output terminal I. : 1st FPGA-2nd FPGA "is input. The selection circuit 24 selects a signal output from the output terminal C of the first FPGA 21 and input to the input terminal C of the selection circuit 24 based on the input “selection signal: first FPGA−second FPGA” and outputs an output terminal. Output from I. The signal output from the output terminal I of the selection circuit 24 is input to the second FPGA 22. Before the selection circuit 24 outputs the signal input to the input terminal C from the output terminal I, the output confirmation circuit 26 confirms the signal output from the first FPGA 21 to determine whether or not the first FPGA 21 has failed. judge.

  Thereby, the signal processing circuit 20 can perform signal processing based on the second functional circuit in the first FPGA 21 with respect to the signal input from the outside, and input the processed signal to the second FPGA 22. The signal input to the second FPGA 22 is subjected to the same processing as described above, and is output from the output terminal H of the selection circuit 24 to the outside.

  As described above, when the functional circuit of the first FPGA 21 is rewritten from the first functional circuit to the second functional circuit, the control circuit 25 first configures the second functional circuit for the alternative FPGA 23. Then, after confirming that this configuration has been normally completed, the control circuit 25 controls the selection circuit 24 to select the output of the alternative FPGA 23 and input it to the second FPGA 22. Next, the control circuit 25 configures the second functional circuit for the first FPGA 21 while performing signal processing with the alternative FPGA 23 instead of the first FPGA 21. Then, after confirming that this configuration has been completed normally, the control circuit 25 controls the selection circuit 24 to select the output of the first FPGA 21 and input it to the second FPGA 22. As a result, signal processing can be performed using the alternative FPGA 23 instead of the first FPGA 21 even while the first FPGA 21 is being configured. Therefore, the signal processing circuit 20 includes a functional circuit configured for the first FPGA 21. Even in the case of updating, the processing can be continued.

  The signal processing circuit 20 configures the second functional circuit in the first FPGA 21 after configuring the second functional circuit in the alternative FPGA 23 and does not continue processing using the alternative FPGA 23. Process. As a result, the signal processing circuit 20 can operate on the normal path (the path on which the first FPGA 21 processes signals) even after the functional circuit configured in the first FPGA 21 is changed. Thereby, the alternative FPGA 23 can be used for other purposes (for example, rewriting of another FPGA).

  Further, after the second functional circuit is configured for the alternative FPGA 23, when the output confirmation circuit 26 included in the selection circuit 24 detects a failure of the alternative FPGA 23, the control circuit 25 outputs the output of the selection circuit 24 to the alternative FPGA 23. The output of the first FPGA 21 may be selected and output as it is without switching to the output. As a result, the signal processing circuit 20 can continuously process the input signal even when a failure occurs in the alternative FPGA 23.

  In the case where the alternative FPGA 23 fails, if the function circuit of the first FPGA 21 is to be changed from the first function circuit to the second function circuit even when the processing for the input signal is stopped, the control circuit 25 changes the first FPGA 21 to the first FPGA 21. By controlling to configure the two-function circuit, the function circuit of the first FPGA 21 can be changed to the second function circuit.

  In addition, after configuring the second functional circuit for the alternative FPGA 23, when some failure occurs in the first FPGA 21 when configuring the second functional circuit in the first FPGA 21, the control circuit 25 outputs the output of the selection circuit 24. Instead of switching to the output of the first FPGA 21, the output of the alternative FPGA 23 may be selected and output as it is. As a result, the signal processing circuit 20 can continuously process the input signal even when a failure occurs in the first FPGA 21.

  Also, after configuring the second functional circuit for the alternative FPGA 23 and then configuring the second functional circuit for the first FPGA 21, some failure occurs in the first FPGA 21, and the output confirmation circuit 26 confirms the failure of the first FPGA 21. In this case, the control circuit 25 may retry the configuration of the second functional circuit in the first FPGA 21. When the output confirmation circuit 26 confirms that the first FPGA 21 is operating normally, the control circuit 25 may switch the output of the selection circuit 24 to the output of the first FPGA 21. Thus, even when a failure occurs in the first FPGA 21, the functional circuit of the first FPGA 21 can be changed to the second functional circuit by retrying the configuration.

  When retrying the configuration of the second functional circuit to the first FPGA 21, the configuration data may be read again from the same ROM, and the configuration data may be separately provided from the ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 25 retries the configuration of the second functional circuit to the first FPGA 21 is, for example, when the configuration of the second functional circuit to the first FPGA 21 is not normally completed or when the output confirmation circuit 26 Is the timing when the failure of the first FPGA 21 is confirmed when it is confirmed whether or not the first FPGA 21 is operating normally. The timing at which the output confirmation circuit 26 confirms whether or not the first FPGA 21 is operating normally is the timing at which the configuration of the second functional circuit in the first FPGA 21 is completed, the blanking period of the vertical synchronization signal, etc. , Periodically in a certain cycle.

  Next, an operation procedure when the functional circuit of the second FPGA 22 is rewritten from the third functional circuit to the fourth functional circuit will be described. When the functional circuit of the second FPGA 22 is rewritten from the third functional circuit to the fourth functional circuit, first, the control circuit 25 causes the alternative FPGA 23 to configure the fourth functional circuit so that the alternative FPGA 23 is configured as “alternative FPGA config. “Start signal: fourth function circuit” is input. The alternative FPGA 23 configures the fourth functional circuit based on “alternative FPGA configuration start signal: fourth functional circuit” input from the control circuit 25. Then, after the configuration is normally completed, the alternative FPGA 23 inputs an “alternative FPGA configuration completion signal” to the control circuit 25.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 23, the control circuit 25 determines that the configuration of the alternative FPGA 23 has been completed normally. When the control circuit 25 determines that the configuration of the alternative FPGA 23 is normally completed, the control circuit 25 outputs the signal output from the output terminal K of the second FPGA 22 and input to the input terminal K of the selection circuit 24 and the output terminal G of the alternative FPGA 23. The selection circuit 24 is selected so that a signal input to the input terminal G is selected from the signals input to the input terminal G of the selection circuit 24 and output from the output terminal H to the outside. “Selection signal: alternative FPGA-external” is input. The selection circuit 24 selects a signal output from the output terminal G of the alternative FPGA 23 and input to the input terminal G of the selection circuit 24 based on the input “selection signal: alternative FPGA-external” and outputs the output terminal H. To the outside. Before the selection circuit 24 outputs the signal input to the input terminal G from the output terminal H, the output confirmation circuit 26 confirms the signal output from the alternative FPGA 23 to determine whether or not the alternative FPGA 23 has failed. judge.

  As a result, the signal processing circuit 20 can perform signal processing based on the fourth functional circuit in the alternative FPGA 23 on the signal processed by the first FPGA 21 and output the processed signal to the outside.

  Subsequently, the control circuit 25 inputs “second FPGA configuration start signal: fourth function circuit” to the second FPGA 22 in order to cause the second FPGA 22 to configure the fourth function circuit. The second FPGA 22 configures the fourth functional circuit based on “second FPGA configuration start signal: fourth functional circuit” input from the control circuit 25. Then, after the configuration is completed normally, the second FPGA 22 inputs a “second FPGA configuration completion signal” to the control circuit 25.

  When a “second FPGA configuration completion signal” is input from the second FPGA 22, the control circuit 25 determines that the configuration of the second FPGA 22 has been completed normally. When the control circuit 25 determines that the configuration of the second FPGA 22 has been normally completed, the control circuit 25 outputs a signal output from the output terminal K of the second FPGA 22 and input to the input terminal K of the selection circuit 24, and an output terminal G of the alternative FPGA 23. The selection circuit 24 is selected so that a signal input to the input terminal K is selected from among the signals input to the input terminal G of the selection circuit 24 and output from the output terminal H to the outside. Selection signal: 2nd FPGA-external "is input. The selection circuit 24 selects the signal output from the output terminal K of the second FPGA 22 and input to the input terminal K of the selection circuit 24 based on the input “selection signal: second FPGA-external” and outputs the output terminal H To the outside. Before the selection circuit 24 outputs the signal input to the input terminal K from the output terminal H to the outside, the output confirmation circuit 26 confirms the signal output from the second FPGA 22 and determines whether the second FPGA 22 has failed. Determine whether.

  Thereby, the signal processing circuit 20 can perform signal processing based on the fourth functional circuit in the second FPGA 22 on the signal processed by the first FPGA 21, and output the processed signal to the outside.

  As described above, when the functional circuit of the second FPGA 22 is rewritten from the third functional circuit to the fourth functional circuit, the control circuit 25 first configures the fourth functional circuit for the alternative FPGA 23. Then, after confirming that this configuration has been completed normally, the control circuit 25 controls the selection circuit 24 to select the output of the alternative FPGA 23 and output it to the outside. Next, the control circuit 25 configures a fourth functional circuit for the second FPGA 22 while performing signal processing with the alternative FPGA 23 instead of the second FPGA 22. Then, after confirming that this configuration has been completed normally, the control circuit 25 controls the selection circuit 24 to select the output of the second FPGA 22 and output it to the outside. Accordingly, since the signal processing can be performed using the alternative FPGA 23 instead of the second FPGA 22 even during the configuration of the second FPGA 22, the signal processing circuit 20 includes a functional circuit configured for the second FPGA 22. Even in the case of updating, the processing can be continued.

  In addition, the signal processing circuit 20 configures the fourth functional circuit in the second FPGA 22 after configuring the fourth functional circuit in the alternative FPGA 23 and does not continue processing using the alternative FPGA 23. Process. As a result, the signal processing circuit 20 can operate on the normal path (path on which the second FPGA 22 processes signals) even after the functional circuit configured in the second FPGA 22 is changed. Thereby, the alternative FPGA 23 can be used for other purposes (for example, rewriting of another FPGA).

  Further, after the fourth functional circuit is configured for the alternative FPGA 23, when the output confirmation circuit 26 included in the selection circuit 24 detects a failure of the alternative FPGA 23, the control circuit 25 outputs the output of the selection circuit 24 to the alternative FPGA 23. Instead of switching to the output, the output of the second FPGA 22 may be selected and output to the outside as it is. As a result, the signal processing circuit 20 can continuously process the input signal even when a failure occurs in the alternative FPGA 23.

  When the alternative FPGA 23 fails, the control circuit 25 changes the second FPGA 22 to the second FPGA 22 when it is desired to change the function circuit of the second FPGA 22 from the third function circuit to the fourth function circuit even if processing for the input signal is stopped. By controlling to configure the four function circuit, the function circuit of the second FPGA 22 can be changed to the fourth function circuit.

  In addition, after configuring the fourth functional circuit for the alternative FPGA 23, when some failure occurs in the second FPGA 22 when configuring the fourth functional circuit in the second FPGA 22, the control circuit 25 outputs the output of the selection circuit 24. Instead of switching to the output of the second FPGA 22, the output of the alternative FPGA 23 may be selected as it is and output to the outside. As a result, the signal processing circuit 20 can continuously process the input signal even when a failure occurs in the second FPGA 22.

Also, after configuring the fourth functional circuit for the alternative FPGA 23 and then configuring the fourth functional circuit for the second FPGA 22, some failure occurs in the second FPGA 22, and the output confirmation circuit 26 confirms the failure of the second FPGA 22. In this case, the control circuit 25 may retry the configuration of the fourth functional circuit in the second FPGA 22. When the output confirmation circuit 26 confirms that the second FPGA 22 is operating normally, the control circuit 25 may switch the output of the selection circuit 24 to the output of the second FPGA 22. Thereby, even when a failure occurs in the second FPGA 22, the functional circuit of the second FPGA 22 can be changed to the fourth functional circuit by retrying the configuration.

  When retrying the configuration of the fourth functional circuit to the second FPGA 22, the configuration data may be read again from the same ROM, and a different ROM may be provided separately from the ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 25 retries the configuration of the fourth functional circuit to the second FPGA 22 is, for example, when the configuration of the fourth functional circuit to the second FPGA 22 is not normally completed or the output confirmation circuit 26. Is the timing when the failure of the second FPGA 22 is confirmed when it is confirmed whether or not the second FPGA 22 is operating normally. The timing at which the output confirmation circuit 26 confirms whether or not the second FPGA 22 is operating normally is the timing at which the configuration of the fourth functional circuit in the second FPGA 22 is completed, the blanking period of the vertical synchronization signal, and the like. , Periodically in a certain cycle.

  Note that the first FPGA 21, the second FPGA 22, the third FPGA 27, the alternative FPGA 23, and the selection circuit 24 included in the signal processing circuit 20 shown in FIG. And an output terminal. For example, each of the second FPGA 22 and the alternative FPGA 23 includes an input terminal b for inputting a signal other than a signal input / output between the FPGAs. The second FPGA 22 includes an output terminal d, and the alternative FPGA 23 includes an output terminal g.

  With this configuration, when the second FPGA 22 performs processing on a signal input to the input terminal b from the outside and outputs the processed signal from the output terminal d, even when the functional circuit of the second FPGA 22 is rewritten. The functional circuit of the second FPGA 22 can be replaced with the alternative FPGA 23 by switching the signal input to the alternative FPGA 23 to the signal input from the input terminal b and switching the signal output from the alternative FPGA 23 to output from the output terminal g. it can. That is, even when the second FPGA 22 processes signals other than signals input / output between the FPGAs and signals input / output to / from the outside, the functional circuit of the second FPGA 22 can be replaced by the alternative FPGA 23.

  In the above-described example, the operation procedure when the signal processing circuit 20 operates using the first FPGA 21, the second FPGA 22, and the alternative FPGA 23 has been described. However, the signal processing circuit 20 can also operate using the third FPGA 27. . Specifically, as indicated by the dotted line in FIG. 3, the input / output terminal of the third FPGA 27 may be connected to the alternative FPGA 23 and the selection circuit 24 in the same manner as the input / output terminal of the second FPGA 22. Further, the signal processing circuit 20 may include four or more FPGAs and operate using the four or more FPGAs.

  In the example described above, the circuit scale of the alternative FPGA 23 has been described using an example in which the circuit scale of the first FPGA 21, the second FPGA 22, and the third FPGA 27 is equal to or greater than that, but is not limited thereto. For example, the circuit scale of the alternative FPGA 23 may be smaller than the circuit scale of the first FPGA 21, the second FPGA 22, and the third FPGA 27. In this case, the substitute FPGA 23 does not have to realize the same functional circuit as the first FPGA 21, the second FPGA 22, or the third FPGA 27 to be substituted, and among the functional circuits of the first FPGA 21, the second FPGA 22, and the third FPGA 27 to be substituted, Only the minimum necessary functional circuit capable of maintaining signal output may be configured using dedicated configuration data. Thereby, even when the signal processing circuit 20 includes the alternative FPGA 23 having a circuit scale smaller than the circuit scale of the first FPGA 21, the second FPGA 22, and the third FPGA 27, the signal processing circuit 20 can continuously perform the minimum processing.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to the drawings. The signal processing circuit 1 in the present embodiment has the same configuration as the signal processing circuit 1 in the first embodiment. The difference between the present embodiment and the first embodiment is that when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit, the second functional circuit is configured in the alternative FPGA 3 in the first embodiment. In this embodiment, the first functional circuit is configured in the alternative FPGA 3.

  Next, the operation timing of the signal processing circuit 1 when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit will be described. FIG. 4 is a timing chart showing the operation timing of the signal processing circuit 1 when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit in the present embodiment.

  When the power supply of the device in which the signal processing circuit 1 is mounted is turned on, the system reset signal input to the control circuit 5 is canceled. When the system reset signal is canceled, the control circuit 5 inputs “first FPGA configuration start signal: first functional circuit” to the first FPGA 2 so that the first FPGA 2 configures the first functional circuit. The first FPGA 2 configures the first functional circuit based on “first FPGA configuration start signal: first functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the first FPGA 2 inputs a “first FPGA configuration completion signal” to the control circuit 5.

  When the “first FPGA configuration completion signal” is input from the first FPGA 2, the control circuit 5 determines that the configuration of the first FPGA 2 has been completed normally. When the control circuit 5 determines that the configuration of the first FPGA 2 is normally completed, the control circuit 5 selects the output signal of the first FPGA 2 out of the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected signal to the outside. Then, “selection signal: first FPGA” is input to the selection circuit 4. The selection circuit 4 selects the output signal of the first FPGA 2 based on the input “selection signal: first FPGA” and outputs the selected signal to the outside. Before the selection circuit 4 selects the output signal of the first FPGA 2 and outputs it to the outside (before switching the output), the output confirmation circuit 6 confirms the signal output by the first FPGA 2 and the first FPGA 2 fails. It is determined whether or not.

  Thereby, the signal processing circuit 1 can perform signal processing based on the first functional circuit with the first FPGA 2 on the signal input from the outside, and output the processed signal to the outside.

  When an instruction to change the function circuit of the first FPGA 2 from the first function circuit to the second function circuit is input to the control circuit 5, the control circuit 5 configures the first function circuit in the alternative FPGA 3. As such, “alternative FPGA configuration start signal: first functional circuit” is input to the alternative FPGA 3. The alternative FPGA 3 configures the second functional circuit based on “alternative FPGA configuration start signal: first functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the alternative FPGA 3 inputs an “alternative FPGA configuration completion signal” to the control circuit 5.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 3, the control circuit 5 determines that the configuration of the alternative FPGA 3 has been normally completed. When the control circuit 5 determines that the configuration of the alternative FPGA 3 is normally completed, the control circuit 5 selects the output signal of the alternative FPGA 3 from the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected output signal to the outside. Then, “selection signal: alternative FPGA” is input to the selection circuit 4. The selection circuit 4 selects an output signal of the alternative FPGA 3 based on the inputted “selection signal: alternative FPGA” and outputs the selected signal to the outside. Note that before the selection circuit 4 selects the output signal of the alternative FPGA 3 and outputs it to the outside, the output confirmation circuit 6 checks the signal output by the alternative FPGA 3 and determines whether or not the alternative FPGA 3 has failed. .

  Thereby, the signal processing circuit 1 can perform signal processing based on the first functional circuit with the alternative FPGA 3 on the signal input from the outside, and output the processed signal to the outside.

  Subsequently, the control circuit 5 inputs “first FPGA configuration start signal: second functional circuit” to the first FPGA 2 so that the first FPGA 2 configures the second functional circuit. The first FPGA 2 configures the second functional circuit based on “first FPGA configuration start signal: second functional circuit” input from the control circuit 5. Then, after the configuration is normally completed, the first FPGA 2 inputs a “first FPGA configuration completion signal” to the control circuit 5.

  When the “first FPGA configuration completion signal” is input from the first FPGA 2, the control circuit 5 determines that the configuration of the first FPGA 2 has been completed normally. When the control circuit 5 determines that the configuration of the first FPGA 2 is normally completed, the control circuit 5 selects the output signal of the first FPGA 2 out of the output signal of the first FPGA 2 and the output signal of the alternative FPGA 3 and outputs the selected signal to the outside. Then, “selection signal: first FPGA” is input to the selection circuit 4. The selection circuit 4 selects the output signal of the first FPGA 2 based on the input “selection signal: first FPGA” and outputs the selected signal to the outside. Before the selection circuit 4 selects the output signal of the first FPGA 2 and outputs it to the outside, the output confirmation circuit 6 confirms the signal output by the first FPGA 2 and determines whether or not the first FPGA 2 has failed. .

  Thereby, the signal processing circuit 1 can perform signal processing based on the second functional circuit in the first FPGA 2 with respect to the signal input from the outside, and output the processed signal to the outside.

  The signal processing circuit 1 performs the above-described operation when the functional circuit configured in the first FPGA 2 is changed or updated. For example, when the functional circuit of the first FPGA 2 is rewritten from the first functional circuit to the second functional circuit, the control circuit 5 first configures the first functional circuit for the alternative FPGA 3. Then, after confirming that this configuration has been completed normally, the control circuit 5 performs control so that the selection circuit 4 selects the output of the alternative FPGA 3 and outputs it to the outside. Next, the control circuit 5 configures the second functional circuit for the first FPGA 2 while performing signal processing with the alternative FPGA 3 instead of the first FPGA 2. Then, after confirming that this configuration has been completed normally, the control circuit 5 performs control so that the selection circuit 4 selects the output of the first FPGA 2 and outputs it to the outside. Thus, since the signal processing can be performed using the alternative FPGA 3 instead of the first FPGA 2 even while the first FPGA 2 is being configured, the signal processing circuit 1 includes a functional circuit that configures the first FPGA 2. Even in the case of updating, the processing can be continued.

  The signal processing circuit 1 configures the second functional circuit in the first FPGA 2 and uses the first FPGA 2 instead of continuing the processing using the alternative FPGA 3 after configuring the first functional circuit in the alternative FPGA 3. Process. As a result, the signal processing circuit 1 can operate on the normal path (path on which the first FPGA 2 processes signals) even after the functional circuit configured in the first FPGA 2 is changed.

  Further, after the first functional circuit is configured for the alternative FPGA 3, when the output confirmation circuit 6 included in the selection circuit 4 detects a failure of the alternative FPGA 3, the control circuit 5 outputs the output of the selection circuit 4 to the alternative FPGA 3 Instead of switching to the output, the output of the first FPGA 2 may be selected and controlled as it is. As a result, the signal processing circuit 1 can continuously perform processing on the input signal even when a failure occurs in the alternative FPGA 3.

  When the alternative FPGA 3 fails, the control circuit 5 changes the first FPGA 2 to the first FPGA 2 when the function circuit of the first FPGA 2 is to be changed from the first function circuit to the second function circuit even if the processing for the input signal is stopped. By controlling to configure the two-function circuit, the function circuit of the first FPGA 2 can be changed to the second function circuit.

  In addition, after configuring the first functional circuit for the alternative FPGA 3, if any failure occurs in the first FPGA 2 when configuring the second functional circuit in the first FPGA 2, the control circuit 5 outputs the output of the selection circuit 4. Instead of switching to the output of the first FPGA 2, the output of the alternative FPGA 3 may be selected and output as it is. As a result, the signal processing circuit 1 can continuously perform processing on the input signal even when a failure occurs in the first FPGA 2.

  Also, after configuring the first functional circuit for the alternative FPGA 3 and then configuring the second functional circuit for the first FPGA 2, some failure occurs in the first FPGA 2, and the output confirmation circuit 6 confirms the failure in the first FPGA 2. In this case, the control circuit 5 may retry the configuration of the second functional circuit to the first FPGA 2. When the output confirmation circuit 6 confirms that the first FPGA 2 is operating normally, the control circuit 5 may switch the output of the selection circuit 4 to the output of the first FPGA 2. Thus, even when a failure occurs in the first FPGA 2, the functional circuit of the first FPGA 2 can be changed to the second functional circuit by retrying the configuration.

  When retrying the configuration of the second functional circuit to the first FPGA 2, the configuration data may be read again from the same ROM, and a different ROM may be provided separately from the ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 5 retries the configuration of the second functional circuit to the first FPGA 2 is, for example, when the configuration of the second functional circuit to the first FPGA 2 is not normally completed or the output confirmation circuit 6 Is the timing when the failure of the first FPGA 2 is confirmed when it is confirmed whether or not the first FPGA 2 is operating normally. The timing at which the output confirmation circuit 6 confirms whether or not the first FPGA 2 is operating normally is the timing at which the configuration of the second functional circuit to the first FPGA 2 is completed, the blanking period of the vertical synchronization signal, etc. , Periodically in a certain cycle.

  Further, when the signal processing circuit 1 performs signal processing using the first functional circuit again after rewriting the functional circuit of the first FPGA 2 from the first functional circuit to the second functional circuit, the alternative FPGA 3 already has the first Since the function is configured, signal processing can be instantaneously performed using the first functional circuit by simply switching the signal output from the selection circuit 4 from the output signal of the first FPGA 2 to the output signal of the alternative FPGA 3. .

  In the present embodiment, the signal processing circuit 1 has been described, but the present invention is not limited to this. For example, the signal processing circuit 20 according to the second embodiment can perform the same process as the process according to the present embodiment and obtain the same effect. Specifically, in the second embodiment, when the functional circuit of the first FPGA 21 is rewritten from the first functional circuit to the second functional circuit, the second functional circuit is configured in the alternative FPGA 23. Similarly, by configuring the first functional circuit in the alternative FPGA 23, the same effect as in the present embodiment can be obtained. Further, in the second embodiment, when the functional circuit of the second FPGA 22 is rewritten from the third functional circuit to the fourth functional circuit, the alternative FPGA 23 is configured with the fourth functional circuit. By configuring the third functional circuit in the alternative FPGA 23, the same effect as in the present embodiment can be obtained.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a schematic diagram showing the configuration of the signal processing circuit in the present embodiment. In the illustrated example, the signal processing circuit 30 includes a first FPGA 31, a second FPGA 32, an alternative FPGA 33, a selection circuit 34, and a control circuit 35. In addition, as shown with a broken line, you may make it further provide 3rd FPGA37.

  The first FPGA 31, the second FPGA 32, the alternative FPGA 33, and the third FPGA 37 are configured by reading configuration data stored in a ROM (not shown) in the same manner as the first FPGA 2 and the alternative FPGA 3 of the first embodiment. This is a type of programmable integrated circuit that can be configured. The second FPGA 32 includes a selector 40. The selector 40 includes an output confirmation circuit 41. Note that the selector 40 included in the second FPGA 32 and the output confirmation circuit 41 included in the selector 40 may be configured by the configuration of the second FPGA 32.

  The first FPGA 31 includes an input terminal A to which a signal is input from the outside. The first FPGA 31 performs a process based on the configured functional circuit on the signal input to the input terminal A. Further, the first FPGA 31 includes an output terminal C and an output terminal E for outputting a processed signal.

  The second FPGA 32 includes an input terminal C to which a signal is input from the first FPGA 31, an input terminal F to which a signal is input from the alternative FPGA 33, and an input terminal B to which a signal is input from the outside. In addition, the second FPGA 32 performs processing based on the configured functional circuit on signals input to the input terminal C, the input terminal F, and the input terminal B. In addition, the second FPGA 32 includes an output terminal D and an output terminal K for outputting a processed signal.

  The third FPGA 27 includes an input terminal K to which a signal is input from the second FPGA 32, an input terminal M to which a signal is input from the alternative FPGA 33, and an input terminal J to which a signal is input from the outside. The third FPGA 37 performs a process based on the configured functional circuit on the signals input to the input terminal K, the input terminal M, and the input terminal J. The third FPGA 37 includes an output terminal L that outputs a processed signal.

  The alternative FPGA 33 has an input terminal A to which the same signal as the signal input to the input terminal A included in the first FPGA 31 is input, and an input terminal B to which the same signal as the signal input to the input terminal B included in the second FPGA 32 is input. An input terminal C to which the same signal as the signal input to the input terminal C included in the second FPGA 32 is input, an input terminal J to which the same signal as the signal input to the input terminal J included in the third FPGA 37 is input, And an input terminal K to which the same signal as the signal input to the input terminal K included in the third FPGA 37 is input. Further, the alternative FPGA 33 performs processing based on the configured functional circuit for signals input to the input terminal A, the input terminal B, the input terminal C, the input terminal J, and the input terminal K. Do. The alternative FPGA 33 includes an output terminal G that outputs a processed signal.

  The selection circuit 34 includes an input terminal E to which a signal output from the first FPGA 31 is input, an input terminal D to which a signal output from the second FPGA 32 is input, an input terminal L to which a signal output from the third FPGA 37 is input, And an input terminal G to which a signal output from the alternative FPGA 33 is input. The selection circuit 34 also includes a signal output from the first FPGA 31 (an output signal from the first FPGA 31), a signal output from the second FPGA 32 (an output signal from the second FPGA 32), and a signal output from the third FPGA 37 (an output signal from the third FPGA 37). And an output terminal I that selects one of the signals output from the alternative FPGA 33 (an output signal of the alternative FPGA 33) and outputs the selected signal to the outside, an output terminal N, and an output terminal H.

  The output confirmation circuit 36 confirms the signal output from the first FPGA 31, the signal output from the second FPGA 32, the signal output from the third FPGA 37, and the signal output from the alternative FPGA 33, and is input to the selection circuit 34. Then, it is determined whether or not the second FPGA 32, the third FPGA 37, and the alternative FPGA 33 are out of order. Further, the output confirmation circuit 36 inputs a result of determining whether or not the first FPGA 31, the second FPGA 32, the third FPGA 37, and the alternative FPGA 33 are out of order to the control circuit 35.

  The selector 40 outputs a signal output from the first FPGA 31 and input to the input terminal C of the second FPGA 32, a signal output from the alternative FPGA 33 and input to the input terminal F of the second FPGA 32, and an input terminal of the second FPGA 32 from the outside. One of the signals input to B is selected and used as the input signal to the second FPGA 22.

  The output confirmation circuit 41 confirms the signal output from the first FPGA 31 and input to the input terminal C of the second FPGA 32 and the signal output from the alternative FPGA 33 and input to the input terminal F of the second FPGA 32. It is determined whether or not the alternative FPGA 33 is out of order. In addition, the output confirmation circuit 41 inputs a result of determining whether or not the first FPGA 31 and the alternative FPGA 33 are out of order to the control circuit 35. The control circuit 35 controls the configuration of the first FPGA 31, the second FPGA 32, the third FPGA 37, and the alternative FPGA 33. The control circuit 35 controls signal output from the selection circuit 34 and the selector 40.

  Next, the operation procedure of the signal processing circuit 30 will be described. Hereinafter, an operation procedure when the signal processing circuit 30 operates using the first FPGA 31, the second FPGA 32, and the alternative FPGA 33 will be described as an example. It is assumed that the first functional circuit is configured in the first FPGA 31, the third functional circuit is configured in the second FPGA 32, and the functional circuit is not configured in the alternative FPGA 33.

  When the signal processing circuit 30 is operating normally, the signal input to the signal processing circuit 30 is input to the input terminal A of the first FPGA 31 and the input terminal A of the alternative FPGA 33. The first FPGA 31 performs signal processing based on the first functional circuit on the signal input to the input terminal A and outputs the signal from the output terminal C. The signal output from the output terminal C is input to the input terminal C of the second FPGA 32 and the input terminal C of the alternative FPGA 33. Note that since the functional circuit is not configured in the alternative FPGA 33, the alternative FPGA 33 does not perform processing.

  The selector 40 of the second FPGA 32 selects a signal input to the input terminal C under the control of the control circuit 35 and uses it as an input signal of the second FPGA 32. The second FPGA 32 performs signal processing based on the third functional circuit on the signal input to the input terminal C selected by the selector 40 and outputs the signal from the output terminal D. A signal output from the output terminal D is input to the input terminal D of the selection circuit 34. The selection circuit 34 outputs the signal input to the input terminal D from the output terminal H to the outside under the control of the control circuit 35.

  Next, an operation procedure when the functional circuit of the first FPGA 31 is rewritten from the first functional circuit to the second functional circuit will be described. When the functional circuit of the first FPGA 31 is rewritten from the first functional circuit to the second functional circuit, first, the control circuit 35 causes the alternative FPGA 33 to configure the alternative FPGA configuration in order to configure the second functional circuit. “Start signal: second functional circuit” is input. The alternative FPGA 33 configures the second functional circuit based on “alternative FPGA configuration start signal: second functional circuit” input from the control circuit 35. Then, after the configuration is normally completed, the alternative FPGA 33 inputs an “alternative FPGA configuration completion signal” to the control circuit 35.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 33, the control circuit 35 determines that the configuration of the alternative FPGA 33 has been completed normally. When the control circuit 35 determines that the configuration of the alternative FPGA 33 is normally completed, the control circuit 35 outputs the signal output from the output terminal C of the first FPGA 31, the input to the input terminal C of the second FPGA 32, and the output terminal F of the alternative FPGA 33. Among the signals that are output and input to the input terminal F of the second FPGA 32, the selector 40 is selected as “selection signal: so that the signal input to the input terminal F is selected and used as the input signal of the second FPGA 32. Enter “Alternative FPGA”.

  The selector 40 selects the signal output from the output terminal F of the alternative FPGA 33 and input to the input terminal F of the second FPGA 32 based on the input “selection signal: alternative FPGA” and the input signal of the second FPGA 32. To do. Before the selector 40 sets the signal input to the input terminal F as the input signal of the second FPGA 32, the output confirmation circuit 41 confirms the signal output from the alternative FPGA 33 and determines whether or not the alternative FPGA 33 has failed. Determine.

  Thereby, the signal processing circuit 30 can perform signal processing based on the second functional circuit with the alternative FPGA 33 on the signal input from the outside, and input the processed signal to the second FPGA 32. The signal input to the second FPGA 32 is subjected to the same processing as described above, and is output from the output terminal H of the selection circuit 34 to the outside.

  Subsequently, the control circuit 35 inputs “first FPGA configuration start signal: second functional circuit” to the first FPGA 31 in order to cause the first FPGA 31 to configure the second functional circuit. The first FPGA 31 configures the second functional circuit based on the “first FPGA configuration start signal: second functional circuit” input from the control circuit 35. The first FPGA 31 inputs a “first FPGA configuration completion signal” to the control circuit 35 after the configuration is normally completed.

  When the “first FPGA configuration completion signal” is input from the first FPGA 31, the control circuit 35 determines that the configuration of the first FPGA 31 has been completed normally. When the control circuit 35 determines that the configuration of the first FPGA 31 has been normally completed, the control circuit 35 outputs the signal output from the output terminal C of the first FPGA 31, input to the input terminal C of the second FPGA 32, and the output terminal F of the alternative FPGA 33. Among the signals that are output and input to the input terminal F of the second FPGA 32, the selector 40 is selected as “selection signal: so that the signal input to the input terminal C is selected as the input signal of the second FPGA 32. “First FPGA” is input.

  The selector 40 selects the signal output from the output terminal C of the first FPGA 31 and input to the input terminal C of the second FPGA 32 based on the input “selection signal: first FPGA” and the input signal of the second FPGA 32. To do. Before the selector 40 sets the signal input to the input terminal C as the input signal of the second FPGA 32, the output confirmation circuit 41 confirms the signal output from the first FPGA 31 and determines whether or not the first FPGA 31 has failed. Determine.

  Thereby, the signal processing circuit 30 can perform signal processing based on the second functional circuit in the first FPGA 31 with respect to the signal input from the outside, and input the processed signal to the second FPGA 32. The signal input to the second FPGA 32 is subjected to the same processing as described above, and is output from the output terminal H of the selection circuit 34 to the outside.

  As described above, when the functional circuit of the first FPGA 31 is rewritten from the first functional circuit to the second functional circuit, the control circuit 35 first configures the second functional circuit for the alternative FPGA 33. Then, after confirming that this configuration has been completed normally, the control circuit 35 controls the selector 40 to select a signal input to the input terminal F and use it as an input signal to the second FPGA 32. Next, the control circuit 35 configures the second functional circuit for the first FPGA 31 while performing signal processing with the alternative FPGA 33 instead of the first FPGA 31. Then, after confirming that this configuration has been completed normally, the control circuit 35 controls the selector 40 to select a signal input to the input terminal C and use it as an input signal to the second FPGA 32. Accordingly, since the signal processing can be performed using the alternative FPGA 33 instead of the first FPGA 31 even during the configuration of the first FPGA 31, the signal processing circuit 30 has a functional circuit configured for the first FPGA 31. Even in the case of updating, the processing can be continued.

  The signal processing circuit 30 configures the second functional circuit in the first FPGA 31 after configuring the second functional circuit in the alternative FPGA 33 and does not continue processing using the alternative FPGA 33. Process. As a result, the signal processing circuit 30 can operate on the normal path (the path on which the first FPGA 31 processes signals) even after the functional circuit configured in the first FPGA 31 is changed. Thereby, the alternative FPGA 33 can be used for other purposes (for example, rewriting of another FPGA).

  Further, after the second functional circuit is configured for the alternative FPGA 33, when the output confirmation circuit 41 included in the selector 40 detects a failure of the alternative FPGA 33, the control circuit 35 outputs the output selected by the selector 40. Instead of switching to the output of the alternative FPGA 33, the output of the first FPGA 31 may be selected as it is and used as the input signal of the second FPGA 32. As a result, the signal processing circuit 30 can continuously process the input signal even when a failure occurs in the alternative FPGA 33.

  In the case where the alternative FPGA 33 fails, if the function circuit of the first FPGA 31 is to be changed from the first function circuit to the second function circuit even when processing for the input signal is stopped, the control circuit 35 changes the first FPGA 31 to the first FPGA 31. By controlling to configure the two-function circuit, the function circuit of the first FPGA 31 can be changed to the second function circuit.

  Also, after configuring the second functional circuit for the alternative FPGA 33, if any failure occurs in the first FPGA 31 when configuring the second functional circuit in the first FPGA 31, the control circuit 35 selects the selector 40. Instead of switching the output to be output to the output of the first FPGA 31, the output of the alternative FPGA 23 may be selected as it is and used as the input signal of the second FPGA 32. As a result, the signal processing circuit 30 can continuously process the input signal even when a failure occurs in the first FPGA 31.

  Also, after configuring the second functional circuit for the alternative FPGA 33 and then configuring the second functional circuit for the first FPGA 31, some failure occurs in the first FPGA 31, and the output confirmation circuit 41 confirms the failure of the first FPGA 31. In this case, the control circuit 35 may retry the configuration of the second functional circuit in the first FPGA 31. When the output confirmation circuit 41 confirms that the first FPGA 31 is operating normally, the control circuit 35 switches the output selected by the selector 40 to the output of the first FPGA 31 and uses it as the input signal of the second FPGA 32. It may be. Thereby, even when a failure occurs in the first FPGA 31, the functional circuit of the first FPGA 31 can be changed to the second functional circuit by retrying the configuration.

  When retrying the configuration of the second functional circuit to the first FPGA 31, the configuration data may be read again from the same ROM, and the configuration data may be separately provided from the ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 35 retries the configuration of the second functional circuit to the first FPGA 31 is, for example, when the configuration of the second functional circuit to the first FPGA 31 is not normally completed or the output confirmation circuit 41. Is the timing when the failure of the first FPGA 31 is confirmed when it is confirmed whether or not the first FPGA 31 is operating normally. The timing at which the output confirmation circuit 41 confirms whether or not the first FPGA 31 is operating normally is the timing at which the configuration of the second functional circuit in the first FPGA 31 is completed, the blanking period of the vertical synchronization signal, etc. , Periodically in a certain cycle.

  Further, the second FPGA 32 includes a selector 40, which can select either the signal processed by the first FPGA 31 or the signal processed by the alternative FPGA 33 as an input signal of the second FPGA 32. The signal processed by the alternative FPGA 33 can be input to the second FPGA 32 without going through the selection circuit 34. Therefore, since the path for transmitting the signal is shortened, the delay of the signal input from the first FPGA 31 and the alternative FPGA 33 to the second FPGA 32 can be reduced.

  Next, an operation procedure when the functional circuit of the second FPGA 32 is rewritten from the third functional circuit to the fourth functional circuit will be described. When the functional circuit of the second FPGA 32 is rewritten from the third functional circuit to the fourth functional circuit, first, the control circuit 35 causes the alternative FPGA 33 to configure the fourth functional circuit in order to configure the alternative FPGA 33. “Start signal: fourth function circuit” is input. The alternative FPGA 33 configures the fourth functional circuit based on “alternative FPGA configuration start signal: fourth functional circuit” input from the control circuit 35. Then, after the configuration is normally completed, the alternative FPGA 33 inputs an “alternative FPGA configuration completion signal” to the control circuit 35.

  When the “alternative FPGA configuration completion signal” is input from the alternative FPGA 33, the control circuit 35 determines that the configuration of the alternative FPGA 33 has been completed normally. When the control circuit 35 determines that the configuration of the alternative FPGA 33 is normally completed, the control circuit 35 outputs the signal output from the output terminal D of the second FPGA 32 and input to the input terminal D of the selection circuit 34 and the output terminal G of the alternative FPGA 33. The selection circuit 34 is selected so that a signal input to the input terminal G is selected from the signals output to the input terminal G of the selection circuit 34 and output from the output terminal H to the outside. “Selection signal: alternative FPGA-external” is input. The selection circuit 34 selects the signal output from the output terminal G of the alternative FPGA 33 and input to the input terminal G of the selection circuit 34 based on the input “selection signal: alternative FPGA-external” and outputs the output terminal H. To the outside. Before the selection circuit 34 outputs the signal input to the input terminal G from the output terminal H, the output confirmation circuit 36 confirms the signal output from the alternative FPGA 33 and determines whether the alternative FPGA 33 has failed. judge.

  Thereby, the signal processing circuit 30 can perform signal processing based on the fourth functional circuit in the alternative FPGA 33 on the signal processed by the first FPGA 31, and output the processed signal to the outside.

  Subsequently, the control circuit 35 inputs “second FPGA configuration start signal: fourth function circuit” to the second FPGA 32 in order to cause the second FPGA 32 to configure the fourth function circuit. The second FPGA 32 configures the fourth functional circuit based on “second FPGA configuration start signal: fourth functional circuit” input from the control circuit 35. The second FPGA 32 inputs a “second FPGA configuration completion signal” to the control circuit 35 after the configuration is normally completed.

  When the “second FPGA configuration completion signal” is input from the second FPGA 32, the control circuit 35 determines that the configuration of the second FPGA 32 has been completed normally. When the control circuit 35 determines that the configuration of the second FPGA 32 has been normally completed, the control circuit 35 outputs the signal output from the output terminal D of the second FPGA 32 and input to the input terminal D of the selection circuit 34, and the output terminal G of the alternative FPGA 33. The selection circuit 34 is selected so that a signal input to the input terminal D is selected from the signals input to the input terminal G of the selection circuit 34 and output from the output terminal H to the outside. Selection signal: 2nd FPGA-external "is input. The selection circuit 34 selects the signal output from the output terminal D of the second FPGA 32 and input to the input terminal D of the selection circuit 34 based on the input “selection signal: second FPGA-external” and outputs the output terminal H To the outside. Before the selection circuit 34 outputs the signal input to the input terminal D from the output terminal H to the outside, the output confirmation circuit 36 confirms the signal output from the second FPGA 32 and determines whether the second FPGA 32 has failed. Determine whether.

  Thereby, the signal processing circuit 30 can perform signal processing based on the fourth functional circuit in the second FPGA 32 with respect to the signal processed by the first FPGA 31, and output the processed signal to the outside.

  As described above, when the functional circuit of the second FPGA 32 is rewritten from the third functional circuit to the fourth functional circuit, the control circuit 35 first configures the fourth functional circuit for the alternative FPGA 33. Then, after confirming that this configuration has been completed normally, the control circuit 35 controls the selection circuit 34 to select the output of the alternative FPGA 33 and output it to the outside. Next, the control circuit 35 configures the fourth functional circuit for the second FPGA 32 while performing signal processing with the alternative FPGA 33 instead of the second FPGA 32. Then, after confirming that this configuration has been completed normally, the control circuit 35 controls the selection circuit 34 to select the output of the second FPGA 32 and output it to the outside. Accordingly, since the signal processing can be performed using the alternative FPGA 33 instead of the second FPGA 32 even while the second FPGA 32 is being configured, the signal processing circuit 30 has a functional circuit configured for the second FPGA 32. Even in the case of updating, the processing can be continued.

  In addition, the signal processing circuit 30 configures the fourth functional circuit in the second FPGA 32 after configuring the fourth functional circuit in the alternative FPGA 33 and does not continue processing using the alternative FPGA 33. Process. As a result, the signal processing circuit 30 can operate on the normal path (path on which the second FPGA 32 processes signals) even after the functional circuit configured in the second FPGA 32 is changed. Thereby, the alternative FPGA 33 can be used for other purposes (for example, rewriting of another FPGA).

  Further, after the fourth functional circuit is configured for the alternative FPGA 33, when the output confirmation circuit 36 included in the selection circuit 34 detects a failure of the alternative FPGA 33, the control circuit 35 outputs the output of the selection circuit 34 to the alternative FPGA 33. The output of the second FPGA 32 may be selected as it is without being switched to the output of the second, and controlled to be output to the outside. As a result, the signal processing circuit 30 can continuously process the input signal even when a failure occurs in the alternative FPGA 33.

  When the alternative FPGA 33 fails, the control circuit 35 changes the second FPGA 32 to the second FPGA 32 when it is desired to change the function circuit of the second FPGA 32 from the third function circuit to the fourth function circuit even if processing for the input signal is stopped. By controlling to configure the four function circuit, the function circuit of the second FPGA 32 can be changed to the fourth function circuit.

  Further, after configuring the fourth functional circuit for the alternative FPGA 33, if any failure occurs in the second FPGA 32 when configuring the fourth functional circuit in the second FPGA 32, the control circuit 35 outputs the output of the selection circuit 34. Instead of switching to the output of the second FPGA 32, the output of the alternative FPGA 33 may be selected as it is and output to the outside. Thus, the signal processing circuit 30 can continuously process the input signal even when a failure occurs in the second FPGA 32.

  In addition, after configuring the fourth functional circuit for the alternative FPGA 33 and then configuring the fourth functional circuit for the second FPGA 32, some failure occurs in the second FPGA 32, and the output confirmation circuit 36 confirms the failure of the second FPGA 32. In this case, the control circuit 35 may retry the configuration of the fourth functional circuit in the second FPGA 32. When the output confirmation circuit 36 confirms that the second FPGA 32 is operating normally, the control circuit 35 may switch the output of the selection circuit 34 to the output of the second FPGA 32. Thereby, even when a failure occurs in the second FPGA 32, the functional circuit of the second FPGA 32 can be changed to the fourth functional circuit by retrying the configuration.

  When retrying the configuration of the fourth functional circuit to the second FPGA 32, the configuration data may be read again from the same ROM, and the configuration data may be provided separately from this ROM. May be read and configured. Further, the configuration may be retried by changing the configuration method.

  The timing at which the control circuit 35 retries the configuration of the fourth function circuit to the second FPGA 32 is, for example, when the configuration of the fourth function circuit to the second FPGA 32 is not completed normally, or when the output confirmation circuit 36 Is the timing when the failure of the second FPGA 32 is confirmed when it is confirmed whether or not the second FPGA 32 is operating normally. The timing at which the output confirmation circuit 36 confirms whether or not the second FPGA 32 is operating normally is the timing at which the configuration of the fourth functional circuit in the second FPGA 32 is completed, the blanking period of the vertical synchronization signal, and the like. , Periodically in a certain cycle.

  In the example described above, the operation procedure when the signal processing circuit 30 operates using the first FPGA 31, the second FPGA 32, and the alternative FPGA 33 has been described. However, the signal processing circuit 30 can also operate using the third FPGA 37. . Specifically, as shown by the dotted line in FIG. 5, the input terminal K of the third FPGA 37 is connected to the output terminal K of the second FPGA 32, the input terminal J of the third FPGA 37 is connected to an external input, and the input terminal M of the third FPGA 37 is connected. It is only necessary to connect to the output terminal M of the alternative FPGA 33 and connect the output terminal L of the third FPGA 37 to the input terminal L of the selection circuit 36. The signal processing circuit 30 may include four or more FPGAs and operate using the four or more FPGAs.

  In the above-described example, the circuit scale of the alternative FPGA 33 has been described using an example in which the circuit scale of the first FPGA 31, the second FPGA 32, and the third FPGA 37 is equal to or greater than that, but is not limited thereto. For example, the circuit scale of the alternative FPGA 33 may be smaller than the circuit scale of the first FPGA 31, the second FPGA 32, and the third FPGA 37. In this case, the alternative FPGA 33 does not need to realize the same functional circuit as the first FPGA 31, the second FPGA 32, and the third FPGA 37 to be replaced. Of the functional circuits of the first FPGA 31, the second FPGA 32, and the third FPGA 37 to be replaced, Only the minimum necessary functional circuit capable of maintaining signal output may be configured using dedicated configuration data. Thereby, even when the signal processing circuit 30 includes the alternative FPGA 33 having a circuit scale smaller than the circuit scale of the first FPGA 31, the second FPGA 32, and the third FPGA 37, the minimum processing can be continuously performed.

  The first to fourth embodiments of the present invention have been described in detail with reference to the drawings, but the specific configuration is not limited to this embodiment and does not depart from the gist of the present invention. Range design etc. are also included.

  For example, in the above-described embodiment, the signal processing circuit has been described using an example including a plurality of FPGAs, a selection circuit, and a control circuit. However, the present invention is not limited to this. For example, each FPGA, a selection circuit, and a control circuit are each interpreted as a circuit block, and all circuit blocks are configured in one FPGA. Then, even when the circuit configured in the FPGA is operating, the partial reconfiguration function capable of rewriting a part of the FPGA is used to partially reconfigure the desired circuit block. The operations shown in the first to fourth embodiments may be performed. Accordingly, the number of devices included in the signal processing circuit can be reduced, so that the area of the substrate can be reduced. Further, since the number of devices can be reduced, the cost for generating the signal processing circuit can also be reduced.

  DESCRIPTION OF SYMBOLS 1,20,30 ... Signal processing circuit 2, 21, 31 ... 1st FPGA, 3, 23, 33 ... Alternative FPGA, 4, 24, 34 ... Selection circuit, 5, 25, 35 ... Control circuit, 6, 26, 36, 41 ... Output confirmation circuit, 22.32 ... Second FPGA, 27,37 ... Third FPGA, 40 ... Selector

Claims (12)

A first programmable circuit block;
A second circuit block that is programmable and capable of inputting and outputting the same input / output signals as the first circuit block;
A selection circuit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block;
An output confirmation circuit for confirming an output signal of the first circuit block and determining whether or not the first circuit block is faulty;
The first circuit block and the second circuit block have a function of performing configuration. After the first function is configured in the first circuit block, the output confirmation circuit has the first circuit block. When it is determined that the circuit block has failed, the first function is configured in the second circuit block, and after confirming that the configuration has been completed normally, the selection circuit performs the second function. A control circuit that controls to select and output the output signal of the circuit block;
A signal processing circuit comprising: The control circuit further configures the second function in the second circuit block when configuring the second function in the first circuit block in which the first function is configured. And after confirming that the configuration has been completed normally, the selection circuit is controlled to select and output the output signal of the second circuit block, and then the first circuit block The second circuit is configured, and the selection circuit is controlled to select and output the output signal of the first circuit block after confirming that the configuration is normally completed. The signal processing circuit according to claim 1. A third circuit block that is programmable, and wherein the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit;
The second circuit block can input / output the same input / output signals as the first circuit block and the third circuit block,
The selection circuit selects one of the output signal of the first circuit block and the output signal of the second circuit block, and inputs the selected output signal to the third circuit block as the input signal,
The control circuit further includes
The third circuit block has a function of performing configuration,
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block is selected. The selection circuit is controlled to be input as the input signal, the second function is configured in the second circuit block, and after confirming that the configuration is normally completed, the second circuit is configured. Selecting the output signal of the circuit block and controlling the selection circuit to input it as the input signal to the third circuit block, and then configuring the second function in the first circuit block; After confirming that the configuration has been normally completed, the output signal of the first circuit block is selected and the third circuit is selected. It controls the selection circuit to enter as the input signal to the lock,
When the fourth function is configured in the third circuit block in which the third function is configured, the output signal of the first circuit block is selected and the third circuit block is set in the third circuit block. The first circuit is controlled after controlling the selection circuit to input as an input signal, configuring the fourth function in the second circuit block, and confirming that the configuration is normally completed. Controlling the selection circuit to select the output signal of a block and input it as the input signal to the second circuit block, and then configure the fourth function in the third circuit block; After confirming that the configuration has been normally completed, the output signal of the first circuit block is selected and the third circuit is selected. The signal processing circuit according to claim 1, wherein the controller controls the selection circuit to enter as the input signal to the lock. The control circuit configures the first function in the second circuit block when configuring the second function in the first circuit block in which the first function is configured. Then, after confirming that the configuration has been normally completed, the selection circuit is controlled so as to select and output the output signal of the second circuit block, and then the first circuit block receives the first circuit block. The control circuit is configured to control the selection circuit to select and output the output signal of the first circuit block after confirming that the configuration is normally completed. Item 2. The signal processing circuit according to Item 1. A third circuit block that is programmable, and wherein the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit;
The second circuit block can input / output the same input / output signals as the first circuit block and the third circuit block,
The selection circuit selects one of the output signal of the first circuit block and the output signal of the second circuit block, and inputs the selected output signal to the third circuit block as the input signal,
The control circuit further includes
The third circuit block has a function of performing configuration,
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block is selected. The selection circuit is controlled to input as the input signal, the first function is configured in the second circuit block, and after confirming that the configuration has been normally completed, the second circuit is configured. Selecting the output signal of the circuit block and controlling the selection circuit to input it as the input signal to the third circuit block, and then configuring the second function in the first circuit block; After confirming that the configuration has been normally completed, the output signal of the first circuit block is selected and the third circuit is selected. It controls the selection circuit to enter as the input signal to the lock,
When the fourth function is configured in the third circuit block in which the third function is configured, the output signal of the first circuit block is selected and the third circuit block is set in the third circuit block. The selection circuit is controlled to input as an input signal, the third function is configured in the second circuit block, and it is confirmed that the configuration has been normally completed, and then the first circuit Controlling the selection circuit to select the output signal of a block and input it as the input signal to the second circuit block, and then configure the fourth function in the third circuit block; After confirming that the configuration has been normally completed, the output signal of the first circuit block is selected and the third circuit is selected. The signal processing circuit according to claim 1, wherein the controller controls the selection circuit to enter as the input signal to the lock. The output check circuit further checks the output signal of the third circuit block to determine whether or not the third circuit block is faulty;
If the output check circuit determines that the third circuit block has failed after the third function is configured in the third circuit block, the third function is added to the second circuit block. 4. After confirming that the configuration is normally completed, the selection circuit controls to select and output the output signal of the second circuit block. Or the signal processing circuit of any one of Claim 5. A third circuit block that is programmable, and wherein the output signal from the first circuit block or the second circuit block is input as an input signal through the selection circuit;
The second circuit block can input / output the same input / output signals as the first circuit block and the third circuit block,
The selection circuit selects one of the output signal of the first circuit block and the output signal of the second circuit block, and inputs the selected output signal to the third circuit block as the input signal,
The control circuit further includes
The third circuit block has a function of performing configuration,
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block is selected. Controlling the selection circuit to input as the input signal, configuring the second function in the second circuit block, the fifth function being the minimum function of the first function or the second function; After confirming that the configuration has been normally completed, the selection circuit is controlled so that the output signal of the second circuit block is selected and input as the input signal to the third circuit block. After configuring the second function in the first circuit block and confirming that the configuration has been normally completed, It selects the output signal of the first circuit block controls the selection circuit to enter as the input signal to the third circuit block,
When the fourth function is configured in the third circuit block in which the third function is configured, the output signal of the first circuit block is selected and the third circuit block is set in the third circuit block. The selection circuit is controlled so as to be input as an input signal, and the second function block is configured with the sixth function which is the minimum function among the third function and the fourth function, and After confirming that the configuration has been normally completed, the selection circuit is controlled so that the output signal of the first circuit block is selected and input to the second circuit block as the input signal. After configuring the fourth function in the third circuit block and confirming that the configuration has been normally completed, The signal processing circuit according to claim 1, wherein the controller controls the selection circuit such selects the output signal of the first circuit block inputted as the input signal to the third circuit block. Programmable, having a selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block, and the output signal output by the selection unit A third circuit block as an input signal,
The second circuit block can input / output the same input / output signal as the first circuit block or the third circuit block,
The selection circuit selects and outputs one of an output signal of the first circuit block, an output signal of the second circuit block, and an output signal of the third circuit block. ,
The control circuit further includes
The third circuit block has a function of performing the configuration;
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block The second circuit is controlled after the selection unit is controlled to be the input signal, the second function is configured in the second circuit block, and the configuration is confirmed to be normally completed. The selection unit is controlled to select an output signal of the block to be used as the input signal of the third circuit block, and then the second function is configured in the first circuit block. After confirming that the communication is normally completed, the output signal of the first circuit block is selected and the input signal of the third circuit block is selected. Controls the selector so as to,
When the fourth function is configured in the third circuit block in which the third function is configured, the selection is performed so that the output signal of the third circuit block is selected and output to the outside. After controlling the circuit, configuring the fourth function in the second circuit block, and confirming that the configuration has been normally completed, select the output signal of the second circuit block. The selection circuit is controlled to output to the outside, and then the fourth function is configured in the third circuit block, and after confirming that the configuration has been normally completed, the third circuit is configured. 2. The signal processing circuit according to claim 1, wherein the selection circuit is controlled to select an output signal of the circuit block and output the selected signal to the outside. . Programmable, having a selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block, and the output signal output by the selection unit A third circuit block as an input signal,
The second circuit block can input / output the same input / output signal as the first circuit block or the third circuit block,
The selection circuit selects and outputs one of an output signal of the first circuit block, an output signal of the second circuit block, and an output signal of the third circuit block. ,
The control circuit further includes
The third circuit block has a function of performing the configuration;
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block The selection circuit is controlled so as to be the input signal, the first function is configured in the second circuit block, and after confirming that the configuration is normally completed, the second circuit is configured. The selection unit is controlled to select an output signal of the block to be used as the input signal of the third circuit block, and then the second function is configured in the first circuit block. After confirming that the communication is normally completed, the output signal of the first circuit block is selected and the input signal of the third circuit block is selected. Controls the selector so as to,
When the fourth function is configured in the third circuit block in which the third function is configured, the selection is performed so that the output signal of the third circuit block is selected and output to the outside. After controlling the circuit, configuring the third function in the second circuit block, and confirming that the configuration has been normally completed, select the output signal of the second circuit block. The selection circuit is controlled to output to the outside, and then the fourth function is configured in the third circuit block, and after confirming that the configuration has been normally completed, the third circuit is configured. 2. The signal processing circuit according to claim 1, wherein the selection circuit is controlled to select an output signal of the circuit block and output the selected signal to the outside. . A first selection unit that is programmable and has a first selection unit that selects and outputs either the output signal of the first circuit block or the output signal of the second circuit block. A third circuit block having the output signal to be output as an input signal,
The second circuit block can input / output the same input / output signal as the first circuit block or the third circuit block,
The selection circuit selects and outputs one of an output signal of the first circuit block, an output signal of the second circuit block, and an output signal of the third circuit block. ,
The control circuit further includes
The third circuit block has a function of performing the configuration;
When configuring the second function in the first circuit block in which the first function is configured, the output signal of the first circuit block is selected and the third circuit block The selection unit is controlled so as to be the input signal, and the second function is configured in the second function block, which is the minimum function among the first function and the second function. After confirming that the configuration has been normally completed, the output signal of the second circuit block is selected and the selection unit is controlled to be the input signal of the third circuit block. After configuring the second function in the first circuit block and confirming that the configuration has been completed normally, the first circuit block The selector control to select the output signal to said input signal of said third circuit block,
When the fourth function is configured in the third circuit block in which the third function is configured, the selection is performed so that the output signal of the third circuit block is selected and output to the outside. The circuit is controlled, and the second function block is configured with the third function or the sixth function, which is the minimum function of the fourth function, and the configuration is completed normally. After confirming, the selection circuit is controlled to select and output the output signal of the second circuit block, and then the fourth function is configured in the third circuit block, After confirming that the configuration has been normally completed, the selection circuit selects the output signal of the third circuit block and outputs it to the outside. The signal processing circuit according to claim 1, characterized in that control. The signal processing circuit according to claim 1, wherein the first circuit block and the second circuit block are Field Programmable Gate Arrays. The said 1st circuit block, the said 2nd circuit block, and the said 3rd circuit block are Field Programmable Gate Arrays, Any one of Claims 3-10 characterized by the above-mentioned. Signal processing circuit.

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