JP2012145993A - Computer system, interruption control method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow each OS to start using a new interrupt number in any arbitrary timing under an environment where a plurality of OSs operate, and to share the interrupt number among two or more OSs even when the interrupt number of which the use is to be newly started is used by the other OS already.SOLUTION: A virtual computer monitor 200 has a function which specifies a guest OS which processes an interruption when there is the interruption including a shared interrupt number, and a guest OS 400 determines whether an interrupt number of which the use is to be newly started is being used by any other guest OS. If used by the other guest OS, the interrupt number is designated as the shared interrupt number and information making the shared interrupt number correspondent to the virtual computer monitor is set to an interrupt controller. An interrupt controller 120 causes the virtual computer monitor to specify the guest OS which processes the interruption in the case where the interrupt number included in the received interruption is corresponding to the shared interrupt number.

Description

  The present invention relates to an interrupt control technique in an environment where a plurality of OSs (Operating Systems) operate.

In this specification, a virtual machine system will be described as an example of an environment in which a plurality of OSs operate.
In a conventional virtual machine system, an interrupt management device that notifies an interrupt control device of interrupts from a plurality of peripheral devices with the same interrupt number has a device identification register for specifying an interrupt generation device. The intermediate control unit (corresponding to the virtual machine monitor) refers to the register to determine which device has generated an interrupt with a common interrupt number.
Alternatively, the inter-OS control unit directly accesses all devices sharing the interrupt number and identifies the interrupt generation device (for example, Patent Document 1).

Japanese Patent Laid-Open No. 2001-229038 Item 3-4, Item 6, FIG.

In a conventional virtual machine system, an interrupt with a common interrupt number can be issued only by an I / O (Input / Output) device supported by the interrupt management device, and a new I / O that is not supported by the interrupt management device. The O device has a problem that it cannot issue an interrupt with a common interrupt number.
In the method of directly accessing all the I / O devices sharing the interrupt number, when the user installs a new unsupported I / O device after the release of the virtual machine monitor, the virtual machine monitor is corrected and re-released. There is a problem that tracking is necessary.

  The present invention has been made in view of such a problem. In a computer system in which a plurality of OSs operate, each OS can start using a new interrupt number for a new device at an arbitrary timing. The main object is to realize a mechanism in which an interrupt number can be shared between two or more OSs even when the interrupt number is already used by another OS.

The computer system according to the present invention is:
A computer system in which a plurality of OSs (Operating Systems) operate,
An interrupt controller that accepts an interrupt containing an interrupt number;
A shared interrupt response processing unit that identifies an OS that processes the interrupt as an interrupt processing OS when there is an interrupt including a shared interrupt number shared by two or more OSs;
The use start interrupt number information indicating the interrupt number that the OS starts using is input from any OS, and the interrupt number indicated in the use start interrupt number information is used by another OS. If the interrupt number is used by another OS, the interrupt number is designated as a shared interrupt number, and the shared interrupt control information that associates the shared interrupt number with the shared interrupt response processing unit An interrupt number management unit that sets the interrupt controller in the interrupt controller,
The interrupt controller is
Based on the shared interrupt control information, it is determined whether the interrupt number included in the received interrupt corresponds to the shared interrupt number, and when the interrupt number included in the received interrupt corresponds to the shared interrupt number, the shared interrupt response processing The interrupt processing OS of the interrupt is specified in the section.

According to the present invention, it is determined whether or not the interrupt number that the OS starts to use is used by another OS, and when the OS is used by another OS, the interrupt number is designated as a shared interrupt number. In addition, the association between the shared interrupt number and the shared interrupt response processing unit is set in the interrupt controller.
When the interrupt number included in the interrupt received by the interrupt controller corresponds to the shared interrupt number, the shared interrupt response processing unit is caused to specify the interrupt processing OS of the interrupt.
For this reason, each OS can start using a new interrupt number for a new device at an arbitrary timing, and even if the interrupt number is already used by another OS, it is appropriate. An interrupt processing OS can process an interrupt, and an interrupt number can be shared between two or more OSs.

1 is a diagram illustrating a configuration example of a virtual computer system according to a first embodiment. FIG. 4 is a diagram illustrating a data configuration example of a shared interrupt management table according to the first embodiment. FIG. 3 is a flowchart showing a procedure for setting a shared interrupt management table according to the first embodiment. FIG. 3 is a flowchart showing a procedure for registering an interrupt source determination unit according to the first embodiment. FIG. 3 is a flowchart showing a shared interrupt processing procedure according to the first embodiment. FIG. 6 is a diagram illustrating a configuration example of a virtual machine monitor according to the second embodiment. FIG. 9 is a flowchart showing a processing procedure of a shared interrupt injection destination determination unit according to the second embodiment. FIG. 9 is a flowchart showing a processing procedure of an interrupt handler of a device driver of a guest OS according to the second embodiment. FIG. 10 is a diagram illustrating a data configuration example of a shared interrupt management table according to the third embodiment. FIG. 10 is a flowchart showing a procedure for registering an interrupt source determination unit and the like according to the third embodiment. FIG. 10 is a flowchart showing a shared interrupt processing procedure according to the third embodiment. FIG. 10 is a diagram illustrating a configuration example of a virtual machine monitor according to a fourth embodiment. FIG. 10 is a diagram illustrating a data configuration example of a shared interrupt management table according to the fourth embodiment. The flowchart figure which shows the procedure which registers the interruption origin determination means etc. which concern on Embodiment 4. FIG. FIG. 10 is a flowchart showing a shared interrupt processing procedure according to the fourth embodiment. FIG. 4 is a diagram illustrating an example of interrupt controller registration information according to the first embodiment. The figure which shows the structural example of the physical computer which concerns on Embodiment 1-4.

Embodiment 1 FIG.
In the first to fourth embodiments, in a multi-core virtual machine system, tracking a new I / O device that uses an interrupt with a shared interrupt number is performed without changing the virtual machine monitor, and interrupt processing A configuration for suppressing the overhead will be described.
The shared interrupt number is an interrupt number shared by two or more OSs.
An OS sharing a shared interrupt number is also referred to as a number sharing OS.

FIG. 1 is a diagram showing a configuration of a virtual computer system 500 in the present embodiment.
In the first to fourth embodiments, a virtual computer system 500 will be described as an example of a multi-core computer system in which a plurality of OSs operate.

The physical computer 100 includes processors 110-0, 110-1, 110-2, and 110-3, an interrupt controller 120, an I / O device (for example, a Peripheral Components Interconnect (PCI) device) 130-0 and 130-1, and a memory 140. And a disk device 150 (hereinafter also simply referred to as a disk).
Although the disk device 150 may also operate as the I / O device 130, the disk device 150 has a role of storing a shared interrupt management table 250 to be described later, and is shown separately from the I / O device 130.

The processors 110-0, 110-1, 110-2, and 110-3 include inter-processor interrupt control units 111-0, 111-1, 111-2, and 111-3, respectively.
The interrupt controller 120 is a device that converts an external interrupt into an interrupt vector and outputs the interrupt vector to the processor. The interrupt vector and output destination processor settings for the interrupt number are programmable.
More specifically, the interrupt controller 120 receives an interrupt, determines whether the interrupt number included in the received interrupt is a shared interrupt number, and when the interrupt number included in the received interrupt is a shared interrupt number. The virtual machine monitor 200 identifies the guest OS (interrupt processing OS) that processes the interrupt.
On the other hand, if the interrupt number included in the accepted interrupt is not a shared interrupt number, the guest OS corresponding to the interrupt number is caused to process the interrupt.
The process executed by the interrupt controller 120 corresponds to the interrupt acceptance process.

A virtual machine monitor (VMM: Virtual Machine Monitor) 200 logically divides the processors 110-0 to 110-3 and the I / O devices 130-0 to 130-1 into a virtual machine (VM: Virtual Machine) 300. -0, 300-1 are constructed.
The processors 110-0 and 110-1 and the I / O device 130-0 are allocated to the virtual machine 300-0.
The processors 110-2 and 110-3 and the I / O device 130-1 are assigned to the virtual machine 300-1.
The virtual machine monitor 200 is executed by all of the processors 110-0 to 110-3.
In the following description, it is assumed that the processor 110-0 is a boot processor for the virtual machine monitor 200.
The I / O device 130-0 and the I / O device 130-1 are I / O devices that can be directly accessed from the guest OS and are not shared between the guest OSes, and are not emulated by the virtual machine monitor 200.

  The virtual machine monitor 200 includes an external interrupt handler 210, an inter-processor communication control unit 220, an interrupt injection unit 230, a shared interrupt injection destination determination unit 240, a shared interrupt management table 250, and a controller registration unit 280.

The external interrupt handler 210 is activated when an external interrupt occurs, and intercepts an interrupt to the guest OS 400.
The inter-processor communication control unit 220 performs message communication between processors.
The interrupt injection unit 230 performs processing for injecting the intercepted interrupt into the guest OS 400.
The shared interrupt injection destination determination unit 240 determines which processor 110 in which guest OS 400 the interrupt by the common interrupt number (hereinafter referred to as a shared interrupt) intercepted by the external interrupt handler 210 is injected. .
The processing performed by the external interrupt handler 210, the interrupt injection unit 230, and the shared interrupt injection destination determination unit 240 corresponds to the shared interrupt response processing.
Therefore, the processors 110-0 to 110-3 that execute the virtual machine monitor 200, that is, the processors 110-0 to 110-3 that execute the shared interrupt response processing correspond to an example of the shared interrupt response processing unit.
In FIG. 1, the processor 110-0 is described as a shared interrupt number processing unit for the reason of drawing, but the processors 110-1 to 110-3 also function as a shared interrupt response processing unit.
More specifically, the shared interrupt response processing is instructed by the interrupt controller 120 to specify a guest OS (interrupt processing OS) that processes an interrupt including the shared interrupt number, and the shared interrupt number and the shared interrupt management described later. Based on the table 250, the number sharing OS that shares the shared interrupt number is identified, and the presence / absence of an interrupt from the I / O device 130 specified for each number sharing OS is determined using each identified number sharing OS. The number-shared OS that caused an interrupt from the designated I / O device 130 is identified as the interrupt processing OS, and the interrupt handler of the interrupt processing OS is assigned to the processor associated with the interrupt processing OS in the shared interrupt management table 250. 411 is executed.

The shared interrupt management table 250 is a table that manages information necessary for identifying the interrupt processing OS of the shared interrupt and determining the injection destination of the shared interrupt for each interrupt number.
Details of the shared interrupt management table 250 will be described later.

The controller registration unit 280 inputs the use start interrupt number information transmitted from each guest OS 400 to the interrupt controller 120.
The use start interrupt number information is information indicating the interrupt number that each guest OS 400 is about to start using, the interrupt vector of the interrupt handler 411 of each guest OS 400, and the processor 110 that executes each guest OS 400.
Further, the controller registration unit 280 determines whether or not the interrupt number indicated in the input use start interrupt number information is used by another guest OS 400, and when the interrupt number is used by another guest OS 400. The processor 110 (for example, the processor 110-0) that executes the virtual machine monitor 200 (shared interrupt response processing) and the shared interrupt number are designated with the interrupt number indicated in the input use start interrupt number information as the shared interrupt number. Is registered in the interrupt controller 120 (an example of shared interrupt control information).
On the other hand, if the interrupt number is not used by another guest OS 400, the controller registration unit 280 transfers use start interrupt number information to the interrupt controller 120.
The process performed by the controller registration unit 280 corresponds to an interrupt number management process.
Therefore, the controller registration unit 280, that is, the processors 110-0 to 110-3 executing the virtual machine monitor 200 is also an example of an interrupt number management unit.
In FIG. 1, the processor 110-0 is described as an interrupt number management unit for reasons of drawing, but the processors 110-1 to 110-3 also function as an interrupt number management unit.

Here, FIG. 2 shows an example of the data configuration of the shared interrupt management table 250 in the present embodiment.
In FIG. 2, a “shared interrupt interrupt vector” holds an interrupt vector (hereinafter referred to as a shared interrupt interrupt vector) used by the virtual machine monitor 200 to intercept the shared interrupt.
As the shared interrupt vector, an interrupt vector reserved in advance by the virtual machine monitor 200 exclusively for the shared interrupt is used.
The “registration source OS” holds the identifier of the guest OS that uses the shared interrupt, and the “injection destination processor” and “interrupt vector” are the interrupt vector output destination processors set by the guest OS for the shared interrupt. And holds the interrupt vector information.
The “interrupt source determination unit” holds the interrupt source determination unit given from the guest OS.

In the setting example of FIG. 2, for the interrupt of interrupt number 17, the guest OS 400-0 sets the injection destination processor as the processor 110-0 and the interrupt vector to be injected as number 49, and the guest OS 400-1 Is set as the processor 110-1 and the interrupt vector to be injected is set as No. 65.
The interrupt with the interrupt number 17 is shared by the guest OS 400-0 and the guest OS 400-1, and the virtual machine monitor 200 intercepts the interrupt with the interrupt vector 241.
The interrupt number 16 is used only by the guest OS 400-0.
Furthermore, the interrupt number 18 is not used in any guest OS.
As shown in the line of the interrupt number 18, the shared interrupt vector is set in advance even if the interrupt number is not used.
Further, as apparent from the line of the interrupt number 17, the shared interrupt management table 250 has a shared interrupt number (interrupt number 17) shared by two or more OSs and a number shared OS that shares the shared interrupt number. This is information associating (guest OS 400-0 and guest OS 400-1) with processors (processors 110-0 and 110-1) that execute each number-shared OS, and is an example of shared interrupt number information.

  In FIG. 1, the shared interrupt management table 250 is shown in the virtual machine monitor 200 in order to clearly indicate that the virtual machine monitor 200 refers to the shared interrupt management table 250. However, at the physical machine 100 level, the shared interrupt management table 250 is shared. The interrupt management table 250 is stored in the disk 150. When the virtual machine monitor 200 is executed, for example, the boot processor of the virtual machine monitor 200 loads the memory 150 from the disk 150, and the processors 110-0 to 110-3 store the memory. Read from 140 and refer to the shared interrupt management table 250.

  The guest OS 400-0 operates on the virtual computer 300-0, and the guest OS 400-1 operates on the virtual computer 300-1.

The guest OS 400-0 is an OS that operates on a single processor or a multiprocessor.
As an example, in the present embodiment, the guest OS 400-0 is a multiprocessor OS that uses the processor 110-0 as a boot processor.
The device driver 410-0 of the guest OS 400-0 is a driver of the I / O device 130-0.
The device driver 410-0 includes an interrupt handler 411-0 that performs interrupt processing from the I / O device 130-0 and an interrupt source determination unit 412-0.
The interrupt source determination unit 412-0 refers to the interrupt status register of the I / O device 130-0 to check whether there is an interrupt from the I / O device 130-0, and is true if an interrupt has occurred. The function that can be executed in the context of the virtual machine monitor 200 returns false if it has not occurred.
As described above, in the guest OS 400-0, the I / O device 130-0 is designated as the interrupt source device.
The I / O device 130-0 is a device designated as an interrupt issuer device of the guest OS 400-0, and is an example of a designated device.
The interrupt source determination unit 412-0, which is a function for accessing the designated device and confirming whether or not there is an interrupt from the designated device, is an example of an interrupt presence / absence confirmation function.

The guest OS 400-1 is an OS that operates on a single processor or a multiprocessor.
As an example, in the present embodiment, the guest OS 400-1 is a multiprocessor OS that uses the processor 110-2 as a boot processor.
The guest OS 400-1 has a device driver 410-1 that is a driver of the I / O device 130-1, and the device driver 410-1 performs an interrupt handler that performs interrupt processing from the I / O device 130-1. 411-1 and interrupt source determination means 412-1.
The interrupt source determination unit 412-1 checks the presence / absence of an interrupt from the I / O device 130-1 with reference to the interrupt status register of the I / O device 130-1, and is true if an interrupt has occurred. The function that can be executed in the context of the virtual machine monitor 200 returns false if it has not occurred.
As described above, in the guest OS 400-1, the I / O device 130-1 is designated as the interrupt source device.
The I / O device 130-1 is a device designated as a device that issued an interrupt of the guest OS 400-1, and is an example of a designated device.
The interrupt source determination unit 412-1 which is a function for accessing the designated device and confirming the presence / absence of an interrupt from the designated device is an example of an interrupt presence / absence confirmation function.

  In this embodiment, as an example, a configuration is shown in which there are four processors, two I / O devices, two virtual machines and two guest OSes, but there is only one guest OS in the virtual machine. If the configuration is such that the processor and the I / O device are exclusively allocated to the guest OS, the number of these components is not limited.

  Next, the operation of each component in the present embodiment will be described.

FIG. 3 is a flowchart of a process in which the virtual machine monitor 200 captures the setting process of the interrupt controller 120 by the guest OS 400 and sets the shared interrupt management table 250 in the present embodiment.
In the following description, there may be a case where the elements in the virtual machine monitor 200 such as the controller registration unit 280 and the shared interrupt injection destination determination unit 240 perform a predetermined operation. (For example, in the case of the guest OS 400, the processor 110-0 that is the boot processor of the guest OS 400) performs predetermined operations (interrupt number management) as the controller registration unit 280, the shared interrupt injection destination determination unit 240, and the like. Processing and shared interrupt response processing).

First, in step S101, the guest OS 400 performs an operation for setting an output destination processor and an interrupt vector as an interrupt number for the interrupt controller 120.
In other words, the guest OS 400 gives the interrupt controller 120 the interrupt number to start using, the interrupt vector of the interrupt handler 411 of the guest OS 400, and the start interrupt number information indicating the processor 110 that executes the guest OS 400. Output.
Next, in step S <b> 102, the virtual machine monitor 200 captures access to the interrupt controller 120 by the guest OS 400.
That is, the controller registration unit 280 inputs use start interrupt number information prior to input to the interrupt controller 120.
Next, in step S103, the controller registration unit 280 checks whether another guest OS is using the interrupt number included in the use start interrupt number information.
Specifically, the entry of the registration source OS in the line of the interrupt number in the shared interrupt management table 250 is checked, and the presence / absence of registration of another guest OS is checked.
If there is no other guest OS using the interrupt number in step S103, the controller registration unit 280 emulates the operation of the interrupt controller 120 by the guest OS 400 as it is in step S104.
That is, the controller registration unit 280 transfers the use start interrupt number information to the interrupt controller 120 as it is.
The interrupt controller 120 registers the contents included in the use start interrupt number information as they are.
On the other hand, in step S103, if another guest OS is using the interrupt number included in the use start interrupt number information, in step S105, the controller registration unit 280 designates the interrupt number as a shared interrupt number, and the interrupt controller 120, one of the processors used by the virtual machine monitor 200, for example, the boot processor of the virtual machine monitor 200 is set as the output destination processor for the shared interrupt number, and the interrupt vector for the shared interrupt is set as the interrupt vector. Set.
That is, the controller registration unit 280 sets information (an example of shared interrupt control information) that associates the shared interrupt number, the shared interrupt vector, and the boot processor of the virtual machine monitor 200 in the interrupt controller 120.
Finally, in step S106, the controller registration unit 280 registers the registration source OS, the injection destination processor, and the interrupt vector in the shared interrupt management table 250, and ends.
In this embodiment, information is set to the interrupt controller 120 and the shared interrupt management table 250 is set by capturing access to the interrupt controller 120. You may do this by calling.

FIG. 16 shows an example of interrupt controller registration information registered in the interrupt controller 120.
FIG. 16A shows interrupt controller registration information registered in the interrupt controller 120 when the interrupt number 17 is used only for the guest OS 400-0.
That is, in the interrupt controller registration information in FIG. 16A, the use start interrupt number information output from the guest OS 400-0 is left as it is, and the processor 110-0 executing the guest OS 400-0 is displayed in the output destination processor column. In addition, the interrupt vector column 49 of the guest OS 400-0 is shown in the interrupt vector column.
When the interrupt controller registration information in FIG. 16A is registered in the interrupt controller 120, the line of the interrupt number 17 in the shared interrupt management table 250 in FIG. It is registered.
FIG. 16B shows a state where the interrupt registration information of FIG. 16A is registered in the interrupt controller 120, and the controller registration unit 280 uses the interrupt from the guest OS 400-1 for the interrupt number 17. The interrupt controller registration information when the number information is captured and information related to the shared interrupt is newly set in the interrupt controller 120 is shown.
In this case, the controller registration unit 280 refers to the shared interrupt management table 250 and determines that the interrupt number 17 is already used by another guest OS (OS 400-0).
Since it is shared by the two guest OSs 400, the processor 110-0 executing the virtual machine monitor 200 is shown in the output processor column of the interrupt controller registration information in FIG. 16B, and the interrupt vector column. Indicates an interrupt vector for shared interrupt: No. 241.
Note that the information on the line of the interrupt number 17 in FIG. 16B is an example of the shared interrupt control information.
When the interrupt controller registration information in FIG. 16B is set in the interrupt controller 120, the controller registration unit 280 changes the line of the interrupt number 17 in the shared interrupt management table 250, and as shown in FIG. The row of the registration source OS: 400-0 and the row of the registration source OS: 400-1 are set in the No. 17 row.

  FIG. 4 is a flowchart of processing in which the guest OS 400 registers the interrupt source determination unit in the virtual machine monitor 200 in the present embodiment.

First, in step S111, the guest OS 400 executes normal device driver initialization processing, for example, processing such as connection of an interrupt handler to an interrupt vector.
In step S112, the guest OS 400 requests the virtual machine monitor 200 to register the interrupt source determination unit 412 included in the device driver 410.
In step S113, the virtual machine monitor 200 registers the interrupt source determination unit 412 in the shared interrupt management table 250 using the interrupt number and the registration source OS as keys.

  FIG. 5 is a flowchart showing the procedure of interrupt processing when a shared interrupt occurs in the present embodiment.

First, in step S121, the I / O device 130 issues an interrupt.
Next, in step S122, the interrupt controller 120 refers to the interrupt controller registration information illustrated in FIG. 16 and determines that the interrupt number included in the interrupt is a shared interrupt number, and the boot processor ( For example, a shared interrupt vector is output to the processor 110-0).
Next, in step S123, the boot processor of the virtual machine monitor 200 activates the external interrupt handler 210 of the virtual machine monitor 200 based on the shared interrupt vector, and the shared interrupt injection destination determination unit 240 is called.
In step S124, the boot processor of the virtual machine monitor 200 executes the shared interrupt injection destination determination unit 240.
That is, the boot processor of the virtual machine monitor 200 uses the interrupt source determination unit 412 registered in the shared interrupt management table 250 as the shared interrupt injection destination determination unit 240 to identify the interrupt vector to be injected with the injection destination processor. .
Specifically, all interrupt source determination means 412 registered in the line of the generated interrupt number in the shared interrupt management table 250 are executed in order (execution of the interrupt source determination means 412 as a function is executed), and true is set. The contents of the injection destination processor and interrupt vector terms in the returned line of the interrupt source determination means 412 are acquired.
That is, the guest OS shown in the registration source OS column of the line of the interrupt source determination unit 412 that has returned true is an interrupt processing OS that processes a shared interrupt, and the processor shown in the injection destination processor column is The processor executes the interrupt processing OS, and the interrupt vector shown in the interrupt vector column is the interrupt vector of the interrupt handler of the interrupt processing OS.

In step S125, the boot processor of the virtual machine monitor 200 serves as the shared interrupt injection destination determination unit 240, and checks whether the interrupted processor, that is, the boot processor of the virtual machine monitor 200 is equal to the injection destination processor specified in step S124. To do.
If the interrupt injection destination processor is not equal to the boot processor of the virtual machine monitor 200 in step S125, the boot processor of the virtual machine monitor 200 uses the inter-processor communication control unit 220 in step S126 to Then, the interrupt vector specified in step S124 is transferred.
Next, in step S127, the interrupt injection destination processor injects the interrupt vector specified in step S124 to the guest OS (interrupt processing OS) as the interrupt injection unit 230. Finally, in step S128, the guest OS The interrupt handler of (interrupt processing OS) is activated.

  As a specific example, when the shared interrupt management table 250 is set as shown in FIG. 2 and the interrupt controller registration information is set as shown in FIG. 16B, the I / O device 130-1 has an interrupt number of No. 17. An example of issuing an interrupt is shown below.

When the I / O device 130-1 issues an interrupt of interrupt number 17 that is a shared interrupt, in step S122, the interrupt controller 120 sends a boot processor (for example, the processor 110-0) of the virtual machine monitor 200 to the boot processor. Interrupt vector 241 is output.
Next, in step S123, the external interrupt handler 210 of the virtual machine monitor 200 is activated and the shared interrupt injection destination determination unit 240 is called.
Next, in step S704, the shared interrupt injection destination determination unit 240 sequentially executes the interrupt source determination units 412-0 and 412-1 registered in the line of the interrupt number 17 in the shared interrupt management table 250, Since the interrupt determination means 412-1 returns true, it is determined that the processor to be injected is the processor 110-1 and the interrupt vector to be injected is No. 65.
In step S125, it is determined that the processor that intercepted the interrupt is not equal to the injection destination processor specified in step S124. In step S126, the inter-processor communication control unit 220 determines the processor 110-1 that is the injection destination processor. The interrupt vector 65 is transferred.
Next, in step S127, the interrupt injection unit 230 injects the interrupt vector 65 into the guest OS 400-1, and finally, in step S128, the interrupt handler of the guest OS 400-1 is activated.

As described above, in this embodiment, the guest OS registers the interrupt source determination unit that determines whether or not there is an interrupt with reference to the interrupt status register of the I / O device, and the shared interrupt At the time of occurrence, the virtual machine monitor executes the interrupt source determination means to identify the interrupt source device, that is, the interrupt injection destination processor.
Thereby, it is possible to efficiently follow a new I / O device without changing the virtual machine monitor.
Further, in this embodiment, it is determined whether or not the interrupt number that the guest OS starts to use is used by another guest OS. If the guest OS is used by another guest OS, the interrupt number is set. Designate as a shared interrupt number, and set information for associating the shared interrupt number with the virtual machine monitor in the interrupt controller.
Then, the interrupt controller causes the virtual machine monitor to specify the interrupt processing OS when the interrupt number included in the received interrupt corresponds to the shared interrupt number.
For this reason, even when the interrupt number is already used by another OS, it is possible to cause an appropriate interrupt processing OS to process the interrupt and to share the interrupt number between two or more OSs. it can.

As described above, in the present embodiment,
A virtual machine system in which a virtual machine monitor runs on a physical machine and a guest OS runs on a virtual machine constructed by the virtual machine monitor,
A guest OS including a device driver having an “interrupt source determination unit” that checks whether or not there is an interrupt from the control target I / O device;
A "shared interrupt management table" that holds information such as the usage status of interrupt numbers by guest OSs and the determination of the guest OS to which interrupts with interrupt numbers that are shared among guest OSs are injected, and interrupt controller operations by guest OSs Or a means for registering information for determining a guest OS to which an interrupt with a shared interrupt number is requested and registered in the shared interrupt management table upon request from the guest OS, and from the guest OS. The means for accepting the registration of the interrupt source determination means, and when an interrupt with a shared interrupt number occurs, the interrupt is intercepted, the interrupt source determination means associated with the interrupt number is executed, and the interrupt source The I / O device is specified, and the processor and interrupt of the guest OS into which the interrupt is injected from the shared interrupt management table It described a virtual computer system comprising a virtual machine monitor with the "shared interrupt injection determination section" for specifying a vector.

In the present embodiment,
Explaining that the interrupt source determination unit is a function that can be executed in the context of the virtual machine monitor that accesses the control target I / O device of the device driver having the interrupt source determination unit to determine the presence or absence of an interrupt. did.

Further, the virtual machine system described in the present embodiment can be grasped as an interrupt control method including the following steps.
The virtual interrupt monitor intercepts the operation of the interrupt controller by the guest OS, or is requested by the guest OS, and information for determining the guest OS to which the interrupt with the interrupt number to be shared is injected is the shared interrupt management table. Registering with
A step in which the guest OS registers the interrupt source determination means with respect to the virtual machine monitor;
When an interrupt with a shared interrupt number occurs, the virtual machine monitor intercepts the interrupt and executes the interrupt source determination means associated with the interrupt number to identify the I / O device that generated the interrupt. Identifying a processor and an interrupt vector of the guest OS into which the interrupt is injected from the shared interrupt management table.

In addition, the virtual computer system described in the present embodiment can be grasped as a program for causing a computer to execute the following steps.
The virtual interrupt monitor intercepts the operation of the interrupt controller by the guest OS, or is requested by the guest OS, and information for determining the guest OS to which the interrupt with the interrupt number to be shared is injected is the shared interrupt management table. Registering with
A step in which the guest OS registers the interrupt source determination means with respect to the virtual machine monitor;
When an interrupt with a shared interrupt number occurs, the virtual machine monitor intercepts the interrupt and executes the interrupt source determination means associated with the interrupt number to identify the I / O device that generated the interrupt. Identifying a processor and an interrupt vector of the guest OS into which the interrupt is injected from the shared interrupt management table.

Embodiment 2. FIG.
In the first embodiment, the virtual machine monitor 200 refers to the interrupt status register of the I / O device when determining the interrupt injection destination processor and when the interrupted guest OS device driver performs interrupt processing. However, in the present embodiment, a configuration and an operation in which the number of times the interrupt status register is referred to are described.

FIG. 6 is a diagram illustrating a configuration of the virtual machine monitor 200 according to the second embodiment.
In the present embodiment, the virtual machine monitor 200 newly has an interrupt state register storage area 260.
The other constituent elements of the virtual machine monitor 200 or the constituent elements other than the virtual machine monitor 200 are the same as those in the first embodiment, and a description thereof will be omitted.
The interrupt status register storage area 260 is an area for saving the contents of the interrupt status register of the I / O device (hereinafter referred to as register information) read by the interrupt source determination unit 412.
Thus, the interrupt status register storage area 260 is an area for storing register information, and is an example of a register information storage unit.
Note that the interrupt status register storage area 260 may be configured in the memory 140, for example.

  FIG. 7 shows a flowchart of the processing procedure of the interrupt determination unit 412 executed by the shared interrupt injection destination determination unit 240 in this embodiment.

In step S201, the shared interrupt injection destination determination unit 240 refers to the interrupt status register of the I / O device 130 and holds the contents in a predetermined memory area.
Next, in step S202, the shared interrupt injection destination determination unit 240 checks the contents of the interrupt status register held in a predetermined area in the memory 140, and determines whether or not the I / O device 130 is an interrupt generation source. Investigate.
If it is determined in step S202 that the I / O device 130 is an interrupt source, in step S203, the contents of the interrupt status register held in the memory 140 are changed to the interrupt status that is another area in the memory. Save to the register storage area 260.
In step S204, the return value is set to true, and the process ends.
If it is determined in step S202 that the I / O device 130 is not an interrupt generation source, the return value is set to false in step S205, and the process ends.

FIG. 8 shows a flowchart of the processing procedure of the interrupt handler 411 in the present embodiment.
In step S211, the interrupt handler 411 refers to the interrupt status register storage area 260 instead of directly referring to the interrupt status register in the I / O device 130, and uses the value to perform normal interrupt handler processing. This is executed in step S212.

As described above, in the present embodiment, the virtual machine monitor 200 accesses the interrupt status register of the I / O device only once, and the guest OS device driver saves the interrupt saved in the memory. Refers to the contents of the status register.
As a result, the total number of accesses to the I / O device is reduced, and overhead can be reduced.
In addition, the interrupt status register can correspond to an I / O device that is automatically cleared at the time of reading.

In this embodiment,
The virtual machine monitor further includes an “interrupt status register storage area” for storing the contents of the interrupt status register of the I / O device,
When an interrupt with a shared interrupt number occurs, when the virtual machine monitor reads the contents of the interrupt status register of the I / O device during execution of the shared interrupt injection destination determination unit, the contents of the register are changed to the interrupt status. Save to the register save area,
It has been described that the interrupt handler of the device driver that processes the interrupt acquires the contents of the interrupt status register from the interrupt status register storage area.

Embodiment 3 FIG.
In the present embodiment, a configuration and operation for reducing the overhead of interrupt processing of an I / O device having a high device priority by setting a priority (hereinafter referred to as a device priority) between I / O devices. explain.

  FIG. 9 shows an example of the data configuration of the shared interrupt management table 250 in the third embodiment.

In the present embodiment, the shared interrupt management table 250 newly has items of “device number” and “device priority”.
The other constituent elements of the virtual machine monitor 200 or the constituent elements other than the virtual machine monitor 200 are the same as those in the second embodiment, and a description thereof will be omitted.
In the shared interrupt management table 250, “device number” holds an identifier of a device.
For example, in the case of a PCI device, a BDF number (bus number, device number, function number) is stored. “Device priority” holds the device priority.
In the setting example of FIG. 9, the I / O device 130-0 used by the guest OS 400-0 has a device priority of 30, and the I / O device 130-1 used by the guest OS 400-1 has a device priority. Is 60.
In the present embodiment, the device priority is higher as the value is larger.
As an example, the setting of the device priority may be set from the device driver of the guest OS, or may be determined by the virtual machine monitor 200.

  FIG. 10 is a flowchart of processing in which the guest OS 400 registers the device number and the device priority with respect to the shared interrupt management table 250 of the virtual machine monitor 200 in this embodiment.

Step S111 is the same as step S111 of flowchart S110 of the first embodiment, and a description thereof is omitted.
Next, in step S301, the guest OS 400 sends an interrupt source determination unit, a device number, and a device priority to the virtual interrupt monitor 200 using the interrupt number and the registration source OS as keys. Request registration.
In step S302, the virtual machine monitor 200 sets the interrupt source determination unit 412, the device number, and the device priority with respect to the shared interrupt management table 250 using the interrupt number and registration source OS given from the guest OS 400 as keys. sign up.
At this time, each row belonging to the same interrupt number in the shared interrupt management table 250 is registered in alignment with the device priority value.
The order of arrangement may be ascending or descending.
In the setting example of FIG. 9, as an example, the rows belonging to the interrupt number 17 in the shared interrupt management table 250 are arranged in ascending order of device priority.

  FIG. 11 is a flowchart showing a procedure of interrupt processing when a shared interrupt occurs in the present embodiment.

Steps other than step S311 are the same as those in flowchart S120 of the first embodiment, and a description thereof is omitted.
In step S311, the shared interrupt injection destination determination unit 240 uses the interrupt source determination unit 412 registered in the shared interrupt management table 250 to identify the interrupt vector to be injected with the injection destination processor.
Specifically, all the interrupt source determination means registered in the line of the generated interrupt number in the shared interrupt management table 250 are executed in descending order of device priority, and the interrupt source determination means that returns true Get the contents of the injection destination processor and interrupt vector terms in the row.

  As described above, in this embodiment, when a shared interrupt occurs, the interrupt source determination unit is executed in order from the I / O device with the highest priority. It is possible to reduce the overhead of interrupt processing at the time of occurrence.

As described above, in the present embodiment,
The shared interrupt management table further includes a section that holds a “device number” that is an identifier of an I / O device and a “device priority” that defines a priority of interrupt processing between I / O devices,
The value of the device number is registered with the virtual machine monitor by the guest OS that uses the device,
The device priority value is registered with the virtual machine monitor by a guest OS that uses the device, or is determined by the virtual machine monitor,
The interrupt source determination unit of the shared interrupt management table is registered by the virtual machine monitor in order of the device priority for each interrupt number,
It has been explained that when an interrupt with a shared interrupt number occurs, the virtual machine monitor executes the interrupt source determination means associated with the interrupt number in descending order of the device priority.

Embodiment 4 FIG.
In the present embodiment, a configuration and operation for reducing the overhead of interrupt processing of an I / O device having the highest device priority will be described.

FIG. 12 is a diagram illustrating a configuration of the virtual machine monitor 200 according to the fourth embodiment.
In the present embodiment, the virtual machine monitor 200 newly includes an external interrupt reception processor management unit 270.
Furthermore, the shared interrupt management table 250 has a new item “shared interrupt acceptance processor”.
The other constituent elements of the virtual machine monitor 200 or the constituent elements other than the virtual machine monitor 200 are the same as those in the third embodiment, and a description thereof will be omitted.
The external interrupt acceptance processor management unit 270 sets which processor the virtual machine monitor 200 accepts a shared interrupt.

FIG. 13 shows an example of the data configuration of the shared interrupt management table 250 in the fourth embodiment.
The “shared interrupt acceptance processor” section holds an identifier of a processor that accepts a shared interrupt.
In the setting example of FIG. 13, the guest OS 400-0 has an I / O device 130-0 with a device priority 30 and the guest OS 400-1 has an I / O device 130-1 with a device priority 60 interrupted. The interrupt No. 17 is shared, and the interrupt is intercepted by the virtual machine monitor 200 using the interrupt vector No. 241 in the processor 110-2.

FIG. 14 is a flowchart of processing in which the guest OS 400 registers the device number and the device priority with respect to the shared interrupt management table 250 of the virtual machine monitor 200 in the present embodiment.
Steps S111 to S302 are the same as those in the flowchart S300 of the third embodiment, and a description thereof will be omitted.

In step S401, referring to the line of the interrupt number acquired from step S301 in the shared interrupt management table 250, the guest OS having the I / O device with the highest device priority shares the processor specified as the output destination processor. Register as an interrupt receiving processor.
In step S402, the virtual machine monitor 200 operates the interrupt controller 120, sets the content of “shared interrupt acceptance processor” as the output destination processor for the interrupt number, and sets “interrupt for shared interrupt” as the interrupt vector. Set the contents of “Vector”.
For example, in the setting example of the shared interrupt management table 250 in FIG. 13, for the interrupt with interrupt number 17, the I / O device with the highest device priority is the I / O device 130-1, and the I / O device is The guest OS 400-1 to be used sets the processor 110-2 as an injection destination processor.
Therefore, in step S401, the processor 110-2 is set as a shared interrupt receiving processor item.
In step S402, the virtual machine monitor 200 operates the interrupt controller 120 to set the processor 110-2 as the output destination processor and the number 241 as the interrupt vector for the interrupt number 17.

FIG. 15 is a flowchart showing the procedure of interrupt processing when a shared interrupt occurs in the present embodiment.
Steps other than steps S411 and S412 are the same as those in flowchart S310 of the third embodiment, and a description thereof will be omitted.

When a shared interrupt occurs, in step S411, the interrupt controller 120 outputs a shared interrupt vector to the shared interrupt receiving processor according to the setting by the virtual machine monitor 200.
Thereafter, in step S412, the virtual machine monitor 200 checks whether the injection destination processor specified in step S311 is equal to the shared interrupt reception destination processor.
For example, an operation example in the setting example of the shared interrupt management table 250 in FIG. 13 will be described.
When the I / O device 130-1 generates an interrupt with an interrupt number of 17, the interrupt vector 241 is output to the processor 110-2 that is a shared interrupt receiving processor in step S411.
Since the injection destination processor and the shared interrupt receiving processor are equal, the interrupt vector is not transferred in step S126, and the interrupt vector is injected into the guest OS 400-1 in step S127.
When the I / O device 130-0 generates an interrupt with the interrupt number 17, the interrupt vector 241 is output to the processor 110-2 that is the shared interrupt receiving processor in step S411.
Since the injection destination processor is 110-0, which is different from the shared interrupt receiving processor, the interrupt vector is transferred to the injection destination processor in step S126, and the interrupt vector is injected into the guest OS 400-0 in step S127.

  As described above, in the present embodiment, when a shared interrupt occurs, the guest OS processor having the I / O device with the highest device priority among the I / O devices using the interrupt number is Since the interrupt is accepted, the transfer of the interrupt is unnecessary, and the overhead of the interrupt processing of the I / O device having the highest device priority can be reduced.

As described above, in the present embodiment,
The virtual machine monitor further includes an “external interrupt reception processor management unit” that determines which processor the virtual machine monitor accepts an interrupt with a shared interrupt number,
The shared interrupt management table further includes a “shared interrupt receiving processor” section that holds a processor that receives an interrupt of a shared interrupt number.
The virtual machine monitor registers, for each interrupt number, a processor specified by the guest OS using the I / O device having the highest device priority in the shared interrupt reception processor section of the shared interrupt management table,
It has been described that the virtual machine monitor operates the interrupt controller to set the contents of the shared interrupt reception processor section of the shared interrupt management table as a processor that receives an interrupt for each interrupt number.

Finally, a hardware configuration example of the virtual machine system 500 shown in the first to fourth embodiments, that is, a configuration example of the physical computer 100 shown in FIG. 1 will be described in more detail.
Note that the configuration of FIG. 17 is merely an example of the configuration of the physical computer 100, and the configuration of the physical computer 100 is not limited to the configuration described in FIG. 17, and may be another configuration.

In FIG. 17, the physical computer 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, and a microcomputer) that is a processor 110.
The CPU 911 receives, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, a magnetic disk device 920, and an interrupt controller 907 via the bus 912. Connected and controls these hardware devices.
The communication board 915, the display device 901, the keyboard 902, the mouse 903, and the magnetic disk device 920 may generate an interrupt as the I / O device 130 shown in FIG.
The magnetic disk device 902 is an example of the disk device 150 shown in FIG.
Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), and a printer device 906.
Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card (registered trademark) read / write device may be used.
The RAM 914 is an example of a volatile memory, and corresponds to the memory 140 illustrated in FIG.
The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
The communication board 915, the keyboard 902, the mouse 903, the FDD 904, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

The communication board 915 is connected to a network.
For example, the communication board 915 is connected to a LAN (Local Area Network), the Internet, a WAN (Wide Area Network) or the like.

The magnetic disk device 920 stores a virtual machine monitor 921, a guest OS 922, a program group 923, and a file group 924.
The programs in the program group 923 are executed by the CPU 911, the virtual machine monitor 921, and the guest OS 922.

The ROM 913 stores a BIOS (Basic Input Output System) program, and the magnetic disk device 920 stores a boot program.
When the physical computer 100 is activated, the BIOS program in the ROM 913 and the boot program for the magnetic disk device 920 are executed, the physical computer 100 is activated by the BIOS program and the boot program, and then the virtual computer monitor 921 and the guest OS 922 are activated.

The virtual machine monitor 921 includes software modules such as the external interrupt handler 210, the inter-processor communication control unit 220, the interrupt injection unit 230, the shared interrupt injection destination determination unit 240, and the controller registration unit 280 described in the first to fourth embodiments. included.
The guest OS 922 includes the device driver 410 described in the first to fourth embodiments.
The program group 923 includes application programs shown in the first to fourth embodiments and executed by the guest OS.

Further, in the description of the first to fourth embodiments, the file group 924 includes “determination of”, “determination of”, “execution of”, “comparison of”, “registration of”, “ Update "," Settings "," Selection "," Specify "," Specify "," Input "," Output "," Transfer ", etc. Information, data, signal values, variable values, and parameters indicating the results of processing are stored as items of “˜file” and “˜database”.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, and calculated. Used for CPU operations such as calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
In addition, arrows in the flowcharts described in the first to fourth embodiments mainly indicate input / output of data and signals, and the data and signal values are the RAM 914 memory, the FDD 904 flexible disk, the CDD 905 compact disk, and the magnetic field. Recording is performed on a recording medium such as a magnetic disk of the disk device 920, other optical disks, mini disks, DVDs, and the like. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

In addition, what is described as “to process” in the description of the first to fourth embodiments may be “to step” and “to procedure”.
In addition, what is described as “to process” may be realized by firmware stored in the ROM 913. Alternatively, only software may be implemented by a combination of software and firmware.
Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911.

  110 processor, 111 interprocessor interrupt control unit, 120 interrupt controller, 130 I / O device, 140 memory, 150 disk device, 200 virtual machine monitor, 210 external interrupt handler, 220 interprocessor communication control unit, 230 interrupt injection unit, 240 Shared interrupt injection destination determination unit, 250 shared interrupt management table, 260 interrupt status register storage area, 270 external interrupt reception processor management unit, 280 controller registration unit, 400 guest OS, 410 device driver, 411 interrupt handler, 412 interrupt source determination means 500 virtual machine system.

Claims (11)

A computer system in which a plurality of OSs (Operating Systems) operate,
An interrupt controller that accepts an interrupt containing an interrupt number;
A shared interrupt response processing unit that identifies an OS that processes the interrupt as an interrupt processing OS when there is an interrupt including a shared interrupt number shared by two or more OSs;
The use start interrupt number information indicating the interrupt number that the OS starts using is input from any OS, and the interrupt number indicated in the use start interrupt number information is used by another OS. If the interrupt number is used by another OS, the interrupt number is designated as a shared interrupt number, and the shared interrupt control information that associates the shared interrupt number with the shared interrupt response processing unit An interrupt number management unit that sets the interrupt controller in the interrupt controller,
The interrupt controller is
Based on the shared interrupt control information, it is determined whether the interrupt number included in the received interrupt corresponds to the shared interrupt number, and when the interrupt number included in the received interrupt corresponds to the shared interrupt number, the shared interrupt response processing A computer system characterized by causing a section to specify an interrupt processing OS for the interrupt. The interrupt number management unit
If the interrupt number indicated in the use start interrupt number information is not used by another OS, the use start interrupt number information is transferred to the interrupt controller;
The interrupt controller is
Storing the interrupt number shown in the use start interrupt number information transferred by the interrupt number management unit in association with the OS from which the use start interrupt number information is output;
The OS according to claim 1, wherein when the interrupt number included in the accepted interrupt does not correspond to the shared interrupt number, the OS associated with the interrupt number included in the accepted interrupt is processed. Computer system. In the computer system,
A device that issues an interrupt is designated as a designated device for each, an interrupt handler that processes an interrupt from the designated device is included, and a plurality of OSs that have a function of confirming the presence or absence of an interrupt from the designated device include a plurality of processors Is working
The interrupt number management unit
When the shared interrupt control information is set in the interrupt controller, the shared interrupt number indicated in the shared interrupt control information, a number shared OS that is two or more OSs sharing the shared interrupt number, and each number Generate shared interrupt number information that associates the processor that executes the shared OS,
The shared interrupt response processing unit
When the interrupt controller is instructed to specify the interrupt processing OS, the shared interrupt number is shared based on the shared interrupt number included in the interrupt instructed to specify the interrupt processing OS and the shared interrupt number information. The number sharing OS to be identified is identified, the number sharing OS identified is used to determine whether there is an interrupt from the designated device of each number sharing OS, and the number sharing OS that has been interrupted by the designated device is identified as the interrupt processing OS. 3. The computer system according to claim 1, wherein a processor associated with the interrupt processing OS in the shared interrupt number information is caused to execute an interrupt handler of the interrupt processing OS. The shared interrupt response processing unit
A function included in each identified number-shared OS that executes an interrupt presence / absence confirmation function that accesses the designated device and confirms the presence / absence of an interrupt from the designated device. The computer system according to claim 3, wherein the determination is performed. The shared interrupt response processing unit
A function included in each identified number-shared OS that executes the interrupt presence / absence confirmation function that accesses the register information of the register in the designated device and confirms the presence / absence of an interrupt from the designated device. Judge whether there is an interrupt from the device,
The computer system further includes:
It has a register information storage unit that stores register information accessed by each interrupt existence confirmation function,
Each processor
5. The computer system according to claim 4, wherein an interrupt handler of the interrupt processing OS is executed using the register information stored in the register information storage unit. The interrupt number management unit
Generating shared interrupt number information that associates a shared interrupt number, each number shared OS, a processor that executes each number shared OS, and the priority of a designated device of each number shared OS;
The shared interrupt response processing unit
6. The computer system according to claim 3, wherein the presence / absence of an interrupt from a designated device is determined in order from a number sharing OS having a higher priority of the designated device in the shared interrupt number information.   7. The computer system according to claim 3, wherein a processor that executes a specific number sharing OS is the shared interrupt response processing unit. The interrupt number management unit
Generating shared interrupt number information that associates a shared interrupt number, each number shared OS, a processor that executes each number shared OS, and the priority of a designated device of each number shared OS;
8. The computer system according to claim 3, wherein a processor that executes a number sharing OS having the highest priority of the designated device in the shared interrupt number information is the shared interrupt response processing unit. The computer system is
A virtual machine system having a virtual machine monitor that controls the plurality of OSs;
The computer system according to claim 3, wherein the shared interrupt response processing unit and the interrupt number management unit are processors that execute the virtual computer monitor. An interrupt control method performed by a computer system in which a plurality of OSs (Operating Systems) operate,
A shared interrupt response process that identifies an OS that processes the interrupt as an interrupt processing OS when there is an interrupt that includes a shared interrupt number shared by two or more OSs;
The use start interrupt number information indicating the interrupt number that the OS starts using is input from any OS, and the interrupt number indicated in the use start interrupt number information is used by another OS. If the interrupt number is used by another OS, the interrupt number is designated as a shared interrupt number, and the shared interrupt control information for associating the shared interrupt number with the shared interrupt response process is obtained. The interrupt number management process to be generated,
Accepts an interrupt that includes one of the interrupt numbers, determines whether the interrupt number included in the received interrupt corresponds to the shared interrupt number based on the shared interrupt control information, and shares the interrupt number included in the received interrupt An interrupt control method comprising: an interrupt acceptance process for identifying the interrupt process OS of the interrupt in the shared interrupt response process when the interrupt number corresponds to the interrupt number. In a computer system in which multiple OSs (Operating Systems) operate,
A shared interrupt response process that identifies an OS that processes the interrupt as an interrupt processing OS when there is an interrupt that includes a shared interrupt number shared by two or more OSs;
The use start interrupt number information indicating the interrupt number that the OS starts using is input from any OS, and the interrupt number indicated in the use start interrupt number information is used by another OS. If the interrupt number is used by another OS, the interrupt number is designated as a shared interrupt number, and the shared interrupt control information for associating the shared interrupt number with the shared interrupt response process is obtained. The interrupt number management process to be generated,
Accepts an interrupt that includes one of the interrupt numbers, determines whether the interrupt number included in the received interrupt corresponds to the shared interrupt number based on the shared interrupt control information, and shares the interrupt number included in the received interrupt A program that causes the shared interrupt response process to execute an interrupt acceptance process that identifies an interrupt process OS of the interrupt when the interrupt number corresponds to the interrupt number.

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