JP2012138848A - Time digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a power- and space-saving high-resolution Time-to-Digital Converter (TDC) which measures time difference between a start signal and a stop signal.SOLUTION: The TDC is realized by connecting in series n modules Mto Mwhich perform binary search in the time domain. Difference TDCin rise time between a start signal and a stop signal can be directly obtained from output (tdcto tdc) of Mto M.

Description

  The present invention relates to a time-to-digital converter (TDC) that converts time into a digital value.

  A time digital converter (hereinafter referred to as “TDC”) is used to digitally measure a time difference between a start signal (reference signal) and a stop signal (comparison signal). In recent years, TDC has been widely used in the communication field and the measurement field. In particular, it is used for a frequency synthesizer, a delay lock loop (DLL), an on-chip test circuit, an analog / digital converter (ADC), and the like. For example, Non-Patent Document 1 discloses a technique related to a frequency synthesizer using TDC.

FIG. 1 shows a conventional technique for explaining the principle of TDC. The TDC 100 measures a time difference tm between the rising times of the start signal and the stop signal that are digital signals. A binary digital code TDC _out corresponding to the measured time difference is generated.

The operation of FIG. 1 is as follows. The TDC 100 in FIG. 1B includes a start signal line 110 to which a start signal is transmitted, a stop signal line 120 to which a stop signal is transmitted, a voltage of a node of the start signal line 110 and a stop signal line 120 corresponding thereto. A comparator 130 (F ₁ to F _n ) for comparing the voltage of the node is included. Each comparator 130 is realized by a flip-flop. Each node of the start signal line is connected to each input terminal of the comparator 130. A stop signal line is connected to each clock terminal of the comparator 130.

The time difference between the start signal and the stop signal is output as TDC _out from the outputs Q ₁ to Q _n of the comparator 130 via the encoder 140. Each of from delay element D ₁ present in the input signal line 110 D _n has a function of transmitting a signal with delay t1. This delay element is realized, for example, by connecting inverters in two stages in series. The delay amount t1 is the resolution (resolution) of TDC.

Due to the delay of the delay elements D ₁ to D _n , a start signal delayed by a predetermined delay amount t ₁ is input to the inputs of the comparators F ₁ to F _n . For this reason, when the stop signal 120 becomes “high (H)”, the output of the delay element D _k and the delay element closer to the input side (left side in FIG. 1) than the delay element D _k becomes “high (H)”. However, the output after the next delay element D _{k + 1} is in the “low (L)” state. In this case, Q ₁ to Q _{k + 1} are “high (H)”, and Q _{k + 2} (not shown) and thereafter are “low (L)”. Therefore, the value of k is measured by observing the outputs Q ₁ to Q _n of the comparator, and the number of outputs counted from the input side is “high (H)” (in this case, Q _{k + 1} ). You can know. The encoder 140 extracts TDC _{out obtained} by converting the value of k into a binary number based on the values of the comparator outputs Q ₁ to Q _n as the output of the TDC 100.

FIG. 1A shows the timing of the start signal 110 and the stop signal 120. The resolution (resolution) of TDC _out is t1. The time difference tm between the rising edge of the start signal and the stop signal can be obtained by the following calculation formula.
tm = t1 × TDC _out
Here, as shown in FIG. 1A, a quantization error te exists between the accurate time difference ta between the start signal and the stop signal and the measured time difference tm.

The operation of the encoder 140 that outputs TDC _out from the values of the outputs Q ₁ to Q _n is well known to those skilled in the art and will not be described in this specification.

In order to reduce the quantization error te (te <= t1), it is necessary to reduce the delay amount t1. 2, in order to increase the resolution (resolution), to no delay element Dv ₁ delay amount t2 to stop signal line 220 indicates a conventional TDC200 with vernier (Vernier) delay line 220 having a Dv _n. Unlike the TDC of FIG. 1, it has two delay lines. There is a difference in the delay amount between the delay elements (D ₁ to D _n ) included in the first delay line 110 and the delay elements (Dv ₁ to Dv _n ) included in the vernier delay line 220 (t1 <t2 ). In this case, since the stop signal is also delayed relative to the start signal, the quantization resolution (resolution) is t2-t1. For example, if the delay amount of t1 has a delay amount of 45 picoseconds and the delay amount of t2 is 50 picoseconds, the resolution (resolution) is t2−t1 = 50−45 = 5 picoseconds. Non-Patent Document 2 discloses a TDC using this vernier delay line.

  1 and 2 both require a large number of delay elements, comparators, and the like, and therefore, in the time domain, TDC (hereinafter referred to as “sequential”) using successive approximation (successive approximation). "Comparative TDC" is also proposed (Non-Patent Document 3). This successive approximation type TDC basically uses a binary search when measuring the rise time of the stop signal from the rise time of the start signal. In order to perform a binary search on time domain data, a binary search of the rise time of the stop signal is performed while feeding back the outputs of two independent digital time converters (DTCs) to the input. I do. As for the output of this TDC, the measurement value expressed in binary number is sequentially output to the shift register from the upper bit (MSB) to the lower bit (LSB). For this reason, the encoder 140 shown in FIGS. 1 and 2 is not necessary.

R. B. Staszewski et al., "1.3V 20ps time-to-digital converters for frequency synthesis in 90-nm CMOS," Transaction on Circuits and Systems-II: Express Briefs, pp. 220-224, Mar. 2006 P. Dudek et al., "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," Journal of Solid-State Circuits, pp. 240-247, Feb. 2000 A. Mantyniemi et al., "A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method," Journal of Solid-State Circuits, pp. 3067-3078, Nov. 2009

  The prior art shown in FIG. 1 requires a large number of elements in order to increase the accuracy of measurement results. For example, to obtain 10-bit resolution, at least 1024 delay elements and 1024 comparators are required. In addition, the encoder 140 becomes complicated and consumes a very large amount of power.

  The prior art shown in FIG. 2 requires at least twice as many delay elements as the prior art of FIG. Since the maximum time (time measurement range) that can be measured is shortened by the increase in measurement resolution, it is necessary to further increase the number of stages in order to measure a long time. For this reason, the complexity is higher than that of the prior art shown in FIG. 1, and more power is consumed.

  1 and 2 requires a large area because the circuit is complicated.

  The successive approximation type TDC described above performs a binary search while performing feedback, and therefore requires a necessary timing margin and takes a long time (conversion time) for measurement.

  As described above, TDC is also used, for example, for receiving clock synchronization of a mobile terminal using a high frequency band. For this reason, it is desired to operate at a high speed and with low power consumption and to be mounted in a small area. An object of the present invention is to solve the above-described problems and to realize a high-resolution, power-saving, and space-saving TDC. The object shown here is an example, and the object of the present invention is not limited thereto.

The present invention realizes TDC by connecting _n modules (M ₁ to M _n ) that perform binary search in series. The time difference TDC _out between the rise time of the start signal and the stop signal can be obtained directly from the output (tdc ₁ to tdc _n ) of the module (M ₁ to M _n ).

More specifically, the present invention is a time digital converter for measuring a time difference between a start signal and a stop signal with a resolution of a natural number n within the time measurement range T _p in order to achieve the above object.
N first delay elements connected in series to the start signal, and the kth (1 <= k <= n) first delay elements counted from the input are T _p / 2 ^k N first delay elements having a delay amount;
The stop signal includes n second delay elements connected in series via a multiplexer, and the kth second delay element has n delay amounts of T _p / 2 ^k. A second delay element of
n determination circuits, wherein the kth determination circuit uses the change edge of the output signal of the kth first delay element as a reference time, and the change edge of the input signal of the kth second delay element N determination circuits that determine whether or not the error occurred before and output as the kth determination result signal;
Have
the multiplexer connected to the output of the kth second delay element determines whether to use or bypass the kth second delay element based on the kth determination result signal;
A time digital converter is provided which outputs the first determination result signal to the nth determination result signal as a signal representing the time difference.

  According to the present invention, TDC with high resolution and low power consumption can be realized with a small circuit scale.

FIG. 2 is a timing diagram and a block diagram for showing the prior art and explaining the principle of TDC. It is a block diagram for demonstrating the prior art using a vernier delay line. It is a figure which shows the Example of this invention. It is a figure which shows the detail of the module _Mk which is a component of this invention. It is the timing figure which showed the process of this invention typically. It is a block diagram for performing calibration of the delay element of the present invention.

FIG. 3 is a block diagram showing the TDC of the present invention. The start signal _{S 1} and the stop signal _{P 1} is input to the module _{M 1.}

The module M ₁ outputs the most significant bit (MSB) tdc ₁ to the register 340 when the time difference between the start signal S ₁ and the stop signal P ₁ is represented by an n-bit binary number. In the embodiment shown in FIG. 3, since it is composed of n-stage modules, an n-bit TDC data output TDC _out (tdc ₁ to tdc _n ) can be obtained.

Register 340, to output tdc no ₁ from _{M n} to each module _{M 1} without temporarily storing tdc _n, it is for outputting a _{TDC out} a TDC of binary output. The operations of the modules M ₁ to M _n are executed in a pipeline manner and are divided into stages 1 to n. The register 340 may be a storage device having any configuration as long as it can temporarily store tdc ₁ to tdc _n . There may be n independent registers, or an n-stage shift register.

Figure 4 shows an embodiment of a circuit configuration of a module M _k at stage k. The circuit configuration of the modules M ₁ to M _n is the same as that of the module M _k . From the previous stage of the module _{M k,} the start signal _{S k} and the stop signal _{P k} is input to the module _{M k.} The start signal _{S k is} input to the delay element Ds having a delay amount of ^{T p / 2 k (k)} , the delayed signal Sd _k. The delay signal Sd _k is input to the hold input terminal of the sample / hold circuit S / H (k). Further, the delay signal Sd _k becomes the start signal S _{k + 1} of the module M _{k + 1} of the next stage via the delay elements d1 (k) and Dc (k).

The stop signal P _k from the previous stage is input to the delay element Dp (k) having a delay amount of T _p / 2 ^k , and one of the multiplexers M (k) is passed through the delay element d2 (k). Connected to the input terminal. The stop signal P _k is connected to the input of the sample / hold circuit S / H (k). In addition, the stop signal P _k is connected to the other input terminal of the multiplexer M (k) via the delay element d3 (k).

As shown in FIG. 4, the multiplexer M (k) passes through the delay element Dp (k) and the delay element d2 (k) when the output of the sample / hold circuit S / H (k) is “0”. The stop input signal thus output is output as a stop signal P _{k + 1} for the next stage. When the output of the sample / hold circuit S / H (k) is “1”, the stop signal P _k passing through the delay element d3 (k) is output as the stop signal P _{k + 1} of the next stage ( The delay element Dp (k) is bypassed).

Note that the delay elements d1 (k), d2 (k), and d3 (k) have the same delay amount TS _{/ H} as the delay amount of the sample / hold circuit S / H (k). These delay elements add a delay amount T _{S / H} equal to the delay amount of the sample / hold circuit S / H (k) to each line, so that the sample / hold circuit S / H ( It serves to compensate for the delay amount T _{S / H} of k). In addition, the delay element Dc (k) has the same delay amount T _M as the delay amount of the multiplexer M (k). The delay element Dc (k) serves to cancel and compensate the delay amount T _M of the multiplexer M (k) for the circuits in the subsequent stages by adding the same delay amount T _M to the start signal line. To fulfill. Thus, by inserting d1 (k), d2 (k), d3 (k), and Dc (k), the delay amount caused by the sample / hold circuit S / H (k) and the multiplexer M (k) Can be prevented from affecting the start signal S _{k + 1} and the stop signal P _{k + 1} to the next stage.

FIG. 5 is a timing diagram schematically showing the operation of the present invention when n = 4. Note that n is not limited to 4, and a circuit actually used may have other stages such as n = 10. Therefore, the embodiment shown in FIG. 5 does not limit the present invention. Also, in FIG. 5, in order to make the explanation easy to understand, at each stage, for compensation generated by inserting d1 (k), d2 (k), d3 (k), and Dc (k) described above. The delay amounts T _{S / H} and T _M are not considered. Also in the following description, the delay for compensation is omitted for easy understanding.

5, the measurement range of the time difference between T _p. Then, the start signal S ₁ and the stop signal P ₁ shown in FIG. 5 is input. Hereinafter, each stage will be described.

[Stage 1]
The timing diagram of the stage 1 in FIG. 5 shows the timing in the module M _1. Signal Sd ₁ shows a signal obtained by delaying the start signals _{S 1} by _T p / ^{2 1.} Signal Sd ₁ is inputted to the hold input terminal of the module M ₁ sample / hold circuit S / H (1), a stop input signal P ₁ is inputted to the input terminal. In stage 1, at the rising edge 501 of the signal Sd _1, holding the inverted value of the stop signal _{P 1,} and outputs as tdc _1. In the case of the stage 1 in FIG. 5, the stop signal P ₁ is “1” at the timing 501, and thus the inverted value “0” is output as tdc ₁ . Then, “0” is input to the multiplexer M (1) as a control signal. Thus, multiplexer M (1) is, via a Dp (1), a stop signal _{P 1} is passed through a _T p / ^{2 1} only signal delayed, is transmitted to the stage 2 as a stop signal _{P 2.}

Thus, the sample / hold circuit S / H (1), based on the delay signal Sd ₁ rising (i.e. changing edge) time 501 of the start signal S ₁ inputted, the inputted rising stop signal P ₁ It is checking whether the time has occurred before in time. If it occurred before in time, the sample / hold circuit S / H (1) outputs the value “0” as tdc ₁ ; otherwise, the sample / hold circuit S / H (1) outputs the value “1” as tdc ₁ .

[Stage 2]
In stage 2 in FIG. 5, in module M ₂ , start signal S ₂ is delayed by T _p / 2 ² by delay element Ds (2) to become signal Sd ₂ . The stop signal P ₂ is a signal obtained by delaying the stop signal P ₁ by T _p / 2 ¹ in the above-described stage 1. Signal Sd ₂ to the hold input terminal of the sample / hold circuit S / H of the module M2 (2) is input, a stop signal P ₂ is inputted to the input terminal. In stage 2, at the rising edge 502 of the signal Sd _2, holding the inverted value of the stop signal _{P 2,} and outputs it as tdc _2. In the case of the stage 2 in FIG. 5, the stop signal P ₂ is “0” at the timing 502, and thus the inverted value “1” is output as tdc ₂ . Then, “1” is input to the multiplexer M (2) as a control signal. Thus, multiplexer M (2) does not delay the stop signal P _2, as it passed through, and transmits to the stage 3 as a stop signal P _3.

[Stage 3]
In stage 3 in FIG. 5, in module M ₃ , start signal S ₃ is delayed by T _p / 2 ³ by delay element Ds (3) to become signal Sd ₃ . Further, the stop signal P _3, in stage 2 above, the stop signal P ₂ is in the pass intact signal. Module M ₃ sample / hold circuit S / H (3) signal Sd ₃ to the hold input terminal of the input, a stop signal P ₃ is inputted to the input terminal. In stage 3, at the rising edge 503 of the signal Sd _3, holding the inverted value of the stop signal _{P 3,} and outputs it as tdc _3. In the case of the stage 3 in FIG. 5, the stop signal P ₃ is “0” at the timing 503, so this inverted value “1” is output as tdc ₃ . Then, “1” is input to the multiplexer M (3) as a control signal. Thus, multiplexer M (3) does not delay the stop signal P _3, directly passed through, and transmits to the stage 4 as a stop signal P _4.

[Stage 4]
In the stage 4 in FIG. 5, in the module M ₄ , the start signal S ₄ is delayed by T _p / 2 ⁴ by the delay element Ds (4) to become the signal Sd ₄ . Further, the stop signal P _4, in stage 3 described above, the stop signal P ₃ has a pass intact signal. Signal Sd ₄ is inputted to the hold input terminal of the module M ₄ sample / hold circuit S / H (4), a stop input signal P ₄ is inputted to the input terminal. In stage 4, at the rising edge 504 of the signal Sd _4, holding the inverted value of the stop signal _{P 4,} and outputs it as tdc _4. In the case of the stage 4 in FIG. 5, the stop signal P ₄ is “1” at the timing 504, so this inverted value “0” is output as tdc ₄ .

[Output DCT _out ]
Through the above stages 1 to 4, a binary number “0110” is output as DCT _out (ie, tdc ₁ , tdc ₂ , tdc ₃ , tdc ₄ ). This value is 6 when converted to a decimal number. Therefore, the time difference between the start signal S ₁ and the stop signal P ₁ is grasped as T _p / TDC _out = T _p / 6.

[Calibration of delay element]
There are various delay elements in the present invention. When the circuit of the present invention is mounted on an integrated circuit, an error may occur in the delay element. For this reason, calibration for adjusting the delay amount of each delay element in the integrated circuit to a desired value may be required. By performing calibration, it is possible to operate as a highly accurate TDC.

FIG. 6 is a block diagram for calibrating the delay element of the module _Mk . 6 includes a sample / hold circuit S / H2 (k) for comparing the start signal S _k and the stop signal P _k in addition to the block diagram of FIG. The sample / hold circuit S / H2 (k) outputs Align (k) and is used to check whether the timings of the start signal _Sk and the stop signal _Pk coincide. The delay amounts of the delay elements Ds (k), Dp (k), and Dc (k) can be controlled from the outside.

  Various methods can be considered for calibration of the delay element, and an example thereof will be described below. The present invention is not limited to the following calibration.

  As shown in FIG. 6, the delay amount of the delay elements Ds (k), Dp (k), and Dc (k) is controlled from the outside so that calibration can be performed. An example of calibration will be described below with reference to FIG.

(1) The timing of the start signal _Sk and the stop signal _Pk is matched by monitoring the Align (k) signal.

(2) Delay the stop signal P _k by T _p / 2 ^k .

(3) While watching tdc _k , the delay amount of the delay element Ds (k) is adjusted, and the start signal S _k is delayed by T _p / 2 ^k . As a result, the timings of the signals Sd _k and P _k coincide.

(4) The delay element Dc (k) is adjusted by monitoring Align (k + 1) of the module M _{k + 1} of the next stage. As a result, the timings of the start signal S _{k + 1} and the stop signal P _{k + 1} that are the outputs of the module M _k can be matched. By this adjustment, the delay of the sample / hold circuit S / H (k) and the multiplexer M (k) is compensated.

(5) In the above (2), the delay of the delayed stop signal _Pk is canceled, and the timings of the start signal _Sk and the stop signal _Pk are matched. Then, the delay element Dp (k) is adjusted while monitoring Align (n + 1). As a result, the delay amount of the delay element Dp (k) is T _p / 2 ^k .

  This completes the calibration of each delay element.

  Note that a vernier delay line may be used as the delay element in the module of the subsequent stage where the delay amount is small. This can be realized by inserting a delay element in the stop signal line (for example, the position 401 in FIG. 4). The operation of the vernier delay line is as already described with reference to FIG.

  Further, the configurations of the respective embodiments described in the present specification are not exclusive, and the configurations of the respective embodiments can be freely combined as long as no contradiction occurs.

S ₁ to S _n start signal _P 1 to P _n stop signal _M 1 ~M _n module M (k) module _M measurement range of the multiplexer _{T p} time difference in _k S / H _(k) the sample / hold circuits in the module _{M k} S / H2 (k) sample / hold circuit in module _Mk

Claims (6)

Within the time measurement range T _p, a time to digital converter to measure the time difference between the start signal and a stop signal at a resolution of natural numbers n,
N first delay elements connected in series to the start signal, and the kth (1 <= k <= n) first delay elements counted from the input are T _p / 2 ^k N first delay elements having a delay amount;
The stop signal includes n second delay elements connected in series via a multiplexer, and the kth second delay element has n delay amounts of T _p / 2 ^k. A second delay element of
n determination circuits, wherein the kth determination circuit uses the change edge of the output signal of the kth first delay element as a reference time, and the change edge of the input signal of the kth second delay element N determination circuits that determine whether or not the error occurred before and output as the kth determination result signal;
Have
the multiplexer connected to the output of the kth second delay element determines whether to use or bypass the kth second delay element based on the kth determination result signal;
A time digital converter that outputs the first determination result signal to the nth determination result signal as a signal representing the time difference. The multiplexer connected to the output of the kth second delay element selects an output signal of the kth second delay element when the determination result signal of the kth is positive, and k If the determination result signal is negative, the input signal of the kth second delay element is selected and transmitted to the k + 1th second delay element;
The time digital converter according to claim 1.   The time digital converter according to claim 1 or 2, wherein some of the n first delay elements constitute a vernier delay circuit.   4. The time digital converter according to claim 1, further comprising at least one compensation delay element that compensates at least one delay amount of the determination circuit and the multiplexer. 5.   5. The n first delay elements, the n second delay elements, and the at least one compensation delay element are configured with a delay element capable of varying a delay amount. Time digital converter.   n determination circuits for calibration, where the change edge of the input signal of the kth first delay element is the reference time, and the change edge of the input signal of the kth second delay element is temporally 6. The time digital converter according to claim 5, further comprising n calibration determination circuits that determine whether the occurrence has occurred before and output the result as a kth calibration determination result signal.

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