JP2012138020A - Multichip system, communication device, video/audio device and automobile - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip system and the like capable of reducing total power consumption by the multichip system.SOLUTION: A multichip system having two or more chips for performing tasks includes a first holding part 4 that holds leak current information of each chip representing leak-current characteristics of a transistor in the chips; a second holding part 5 that holds thermal resistance information of each chip representing thermal conduction level from each chip to the outside of the multichip system; a power estimation part 6 that estimates leakage power of each chip when the task processing is allotted based on the leak current information and the thermal resistance information; a power comparison part 7 that compares power consumption including the leakage power; a task management part 8 that allots the task to the chips so that the power consumption gets smaller based on the comparison result.

Description

  The present invention relates to a multichip system having two or more chips that perform task processing, and more particularly to a multichip system that reduces the total power of the multichip.

  In recent years, there has been a very high demand for lower power consumption of LSIs such as SoC (System On a Chip) and memory that perform information processing. However, due to miniaturization of transistors integrated in SoC and memory, there is a problem that manufacturing variation becomes obvious and a chip in which leakage power is extremely increased with a certain probability is produced. Since this leakage power increases exponentially as the temperature rises, it causes reliability problems such as an increase in power at a high temperature, an increase in package cost, and thermal runaway.

  In response to this problem, the following digital circuit technology has been disclosed (Patent Document 1). That is, the digital circuit has an on-chip non-volatile memory into which chip-specific speed binning data characterizing the performance of the digital circuit is written during production testing. A power controller that controls the power supply signal applied to the digital circuit during normal operation optimizes (eg, minimizes) power consumption in the digital circuit, dynamic supply voltage scaling, dynamic clock scaling, and Read speed binning data from on-chip memory for use as input parameters for adaptive power control. Chip-specific speed binning data allows better customization of digital circuit power management, thus improving the accuracy and efficiency of dynamic and / or adaptive power control.

  On the other hand, research and development of a technology for stacking and mounting a plurality of chips such as the above-described SoC and memory in a three-dimensional direction in a package and a technology for incorporating a passive component such as a capacitor in a package are actively conducted. Yes. The advantages of implementing these mountings are that a chip and passive components can be incorporated into the package to provide cost advantages in terms of production of set equipment, and broadband signals can be transmitted at high speed and low power. Points are raised. Such mounting may have a complicated temperature distribution in the package. For example, when a plurality of DRAM chips capable of performing the same task processing are stacked, even if the same power is applied to the chips in the uppermost layer and the lowermost layer and the same processing is performed, the temperature rise values of the chips may be different. This is because, for example, the SoC chip is stacked below the lowermost layer, or a heat sink is mounted on the uppermost layer. In this example, assigning a task to the uppermost chip having a heat sink is advantageous in terms of reducing the total power of the multichip and reducing the temperature.

  As a technique for allocating processing in a multi-chip system, there is a technique that uses a standby redundant chip section instead of a chip section at risk of overheating based on a certain sensor signal (Patent Document 2). In this technique, when a sensor signal is received, the operation of the dangerous chip section is transferred to the redundant chip section and the dangerous chip section is blocked. After the original tip section has cooled, it can itself be used as a replacement tip section. The sensor signal is based on temperature, elapsed operating time, number or speed of chip section operations.

  As described above, there has been proposed a technique for reducing power and temperature by performing voltage control and task allocation according to transistor manufacturing variations and temperature states.

Special table 2010-511247 gazette JP 2000-31382 A

  In an information processing system composed of multiple chips, when there are sufficient resources such as memory and processor, the power changes depending on which chip resource the task is allocated to. For example, if a task is assigned to a chip in which transistors are manufactured at a low Vt due to manufacturing variations, the leakage power increases. In addition, if a task is assigned to a chip whose temperature is likely to rise, leakage power increases due to the temperature rise.

  In the technology of Patent Document 1, power is optimized for one chip according to transistor manufacturing variations, but a mechanism for allocating tasks to chips with low power between chips is not provided. Total power cannot be optimized.

  In Patent Document 2, a temperature sensor is mounted for each chip, and the temperature can be managed by assigning tasks to a plurality of chips according to the temperature state, but the power of the multi-chip cannot be optimized. . Moreover, the technique of patent document 2 raises manufacturing cost by a point provided with a temperature sensor.

  The present invention was created in view of such circumstances, and a multi-chip system that reduces the total power of a multi-chip system by allocating task processing to the chip according to the leakage current and thermal resistance characteristics of the chip. The purpose is to provide a chip system and the like.

  In order to solve the above problems, a multi-chip system according to an aspect of the present invention is a multi-chip system having two or more chips that execute a task, and has a leakage current characteristic for each chip indicating a leakage current characteristic of a transistor in the chip. A first holding unit that holds information, a second holding unit that holds thermal resistance information for each chip indicating how hard the heat from each chip is to the outside of the multichip system, and the leakage current information and thermal resistance information A power estimation unit that estimates the leakage power of each chip when the task processing is allocated, a power comparison unit that compares power consumption including the leakage power, and a chip that reduces power consumption according to the comparison result. A task management unit for allocating tasks.

  According to this configuration, task processing is allocated to the chip according to the leakage current and thermal resistance characteristics of the chip, and the total power of the multichip system can be reduced. That is, in a multi-chip configuration, task allocation for reducing power in the multi-chip total can be determined based on leakage current information and thermal resistance information resulting from manufacturing variations. The thermal resistance information determined in the multichip mounting form may be, for example, thermal resistance when a plurality of chips are molded in one package, or heat when a plurality of chips are arranged on a set substrate. Resistance may be used. A chip including a task processing unit that performs predetermined processing may be any one of a processor, a microcomputer, a memory, and a SoC (System On a Chip).

  Here, the power estimation unit has a table showing a characteristic curve indicating a correspondence relationship between the chip temperature and the leakage power, the product of the thermal resistance value indicated by the thermal resistance information and the power consumption of the chip, and the ambient temperature It is also possible to estimate the chip temperature by adding the assumed maximum value, and to estimate the leakage power from the estimated chip temperature and the table.

  According to this configuration, since the chip temperature is estimated, it is not necessary to provide a temperature sensor, and the manufacturing cost can be reduced.

  Here, the power estimation unit may repeat the estimation of the chip temperature and the estimation of the leakage power a predetermined number of times, and the power estimation unit may perform the estimation of the chip temperature and the estimation of the leakage power under a predetermined condition. You may repeat until it meets. The predetermined condition may be that a difference between a previously estimated chip temperature or leakage current and a currently estimated chip temperature or leakage current is equal to or less than a threshold value.

  According to this configuration, it is possible to ensure the accuracy of chip temperature estimation and leakage power estimation.

  Here, the task management unit may put a chip to which the task processing is not assigned into a power saving state.

  According to this configuration, power consumption can be further reduced.

  Here, the task management unit sets a plurality of combinations of task processing, a chip, and a minimum operating frequency required to execute the task processing in the chip as allocation candidates, and the power estimation unit includes: A leakage current may be estimated for each of the allocation candidates.

  According to this configuration, by setting an allocation candidate including an operating frequency (processing capability) for each chip, optimization of the operating frequency for each chip and power consumption in execution of one task process or a plurality of task processes Can be optimized and done.

  Here, the power comparison unit further compares the leakage power or power consumption of each chip, and gives priority to the priority in ascending order of the comparison result, and the multi-chip system further holds the priority A priority holding unit may be provided, and the task management unit may allocate tasks to chips according to the priority held in the priority holding unit.

  According to this configuration, by holding the priority in the priority holding unit, the priority based on the past leakage power estimation result can be reused, and therefore the task allocation process can be speeded up. .

  Here, the multi-chip system may further include a thermal resistance measurement unit that measures the degree of heat passing from each chip to the outside of the multi-chip system and holds the heat resistance information in the second holding unit. Good.

  According to this configuration, since the thermal resistance can be measured by the thermal resistance measurement unit at any time, the reduction in power consumption can be optimized even when the thermal resistance of the chip changes dynamically or statically. . For example, even if the mounting form of the multi-chip system is not finalized at the time of shipment from the factory, or even if the mounting form of the multi-chip system is changed after shipment from the factory, the reduction in power consumption is optimized by measuring the thermal resistance. can do.

  Here, the multi-chip system may further include a leakage current measuring unit that measures the characteristics of the leakage current of each chip and holds the leakage current information in the first holding unit.

  According to this configuration, since the leakage current measurement unit can measure the leakage current at any time, even if the leakage current of the chip changes due to fluctuations in power supply voltage or aging, etc., the reduction in power consumption is optimized. be able to.

  Here, the leakage current information of the transistor may indicate a source-drain current, and the leakage current information of the transistor may indicate a gate delay time.

  Here, one of the two or more chips may include the second holding unit, the power estimation unit, and the task management unit.

  A multichip system according to another aspect of the present invention includes two or more chips that execute a task, leakage current information for each chip indicating leakage current characteristics of transistors in the chip, and from the chip to the outside of the multichip system. Priority depends on the thermal resistance information for each chip indicating the degree of heat resistance of the chip, and a priority holding unit that holds the priority of chips indicating the order of small power consumption, and power consumption according to the priority And a task management unit for allocating tasks to the chips so as to be small.

  According to this configuration, task processing is allocated to the chip according to the leakage current and thermal resistance characteristics of the chip, and the total power of the multichip system can be reduced. In addition, the circuit scale (chip size) of the multichip system can be reduced, and the cost can be reduced.

  A communication device according to one aspect of the present invention includes the multichip system described above.

  Here, one of the two or more chips in the communication device may perform baseband signal processing, and the other one may perform application program processing.

  In addition, a video / audio apparatus according to one aspect of the present invention includes the multichip system described above.

  Here, one of the two or more chips in the video / audio device may perform video processing, and the other one may perform audio processing.

  An automobile according to one aspect of the present invention includes the multichip system described above.

  Here, one of the two or more chips in the automobile may perform transmission control, and the other one may perform navigation processing.

  As described above, according to the present invention, in the multi-chip system, the total power of the multi-chip system can be reduced.

It is a block diagram which shows the structural example of the multichip system in 1st Embodiment. It is a block diagram which shows the detailed structural example of the multichip system comprised by 3 packages. It is a figure which shows an example of the to-be-measured circuit (real circuit) of leakage current. It is a figure which shows an example of the to-be-measured circuit (PCM) of leak current. It is a figure which shows an example of the to-be-measured circuit (circuit for a measurement) of leakage current. It is a figure which shows an example of the to-be-measured circuit of gate delay time. It is a time chart of the circuit under test of the gate delay time. It is a figure which shows an example of the packaging in a multichip. It is a figure which shows an example of the table for leak electric power calculation. It is a flowchart which shows operation | movement of a multichip system. It is a figure which shows an example, such as an estimation result of chip temperature, a leakage current, and power consumption. It is a figure which shows an example, such as an estimation result of chip temperature, a leakage current, and power consumption. It is a figure which shows an example, such as an estimation result of chip temperature, a leakage current, and power consumption. It is a figure which shows an example, such as an estimation result of chip temperature, a leakage current, and power consumption. It is a figure which shows an example of the characteristic of the leak electric power with respect to temperature. It is a block diagram which shows the detailed structural example of the multichip system comprised by 2 packages. It is a block diagram which shows the structural example of the multichip system in 2nd Embodiment. It is a flowchart which shows the operation example of a multichip system. It is a block diagram which shows the structural example of the multichip system in 3rd Embodiment. It is a block diagram which shows the structural example of the multichip system in 4th Embodiment. It is a general-view figure of the communication apparatus provided with the multichip system. It is a general-view figure of the other communication apparatus provided with the multichip system. It is a general-view figure of AV equipment provided with the multichip system. It is a general-view figure of the other AV apparatus provided with the multichip system. It is a general-view figure of the mobile body provided with the multichip system. It is a general-view figure of the other mobile body provided with the multichip system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a multichip system according to the first embodiment. In the figure, a multi-chip system 100 is a multi-chip system having two or more chips that perform task processing, and includes a chip 1, a chip 2, a first holding unit 4, a second holding unit 5, a power estimation unit 6, and a power. A comparison unit 7 and a task management unit 8 are provided.

  Chip 1 and chip 2 are chips having task processing units 13 and 23 for performing predetermined task processing. The task processing units 13 and 23 are circuits that perform information processing such as computation and data retention. The chip 1 and the chip 2 may be molded in one package or may be mounted on a set substrate in another package.

  In FIG. 1, a first holding unit 4 is a memory that holds leakage current information for each chip indicating leakage current characteristics of a transistor due to manufacturing variations unique to each chip. The leak current information indicates, for example, the leak current per transistor in the chip, the leak current per 1000 transistors in the chip, or the leak current of all the transistors in the chip. Alternatively, the leakage current information may be information indicating the threshold value of the transistor and the gate delay time as information that replaces the leakage current. The leakage current information is set in the first holding unit 4 during inspection or during operation. If the leakage current information is to be acquired at the time of inspection, it is necessary to hold the leakage current information in the first holding unit 4 configured with a nonvolatile memory. If the circuit configuration can be measured during operation, the first configuration configured with a volatile memory is required. Information may be held in the 1 holding unit 4.

  This leakage current information can be obtained by measuring the current between the source and drain of the transistor. For example, as shown in FIG. 3, a static power supply current, which is a chip shipment inspection item that measures the current between the power supply and the GND in a state where the power supply is applied to the circuit that actually operates in the chip 1 or the chip 2 and the operation is stopped. It is arranged in the chip for the purpose of collecting inspection information, as shown in FIG. 4, and for measuring the PCM (Process Control Monitor) on the scribe plane of the wafer as shown in FIG. A technique for measuring a transistor is conceivable. It should be noted that the number of transistors should be large in order to accurately reflect chip variations.

  Further, the leakage current information can be indirectly obtained from the delay characteristics measured by the circuit as shown in FIG. 6A. In the circuit of FIG. 6A, as shown in FIG. 6B, (a) when the delay time is small, (b) when the delay time is standard (medium), and (c) when the delay time is large Is determined. In this circuit, it is possible to monitor with the added flip-flop circuit that the propagation distance of data in one clock cycle, that is, the delay time is different due to the difference in the finish of the gate pass transistor to low Vt or high Vt. it can. If the delay is large, it can be assumed that the chip has a high Vt and the leak current is small, and if the delay is small, it can be assumed that the leak current is large. Such a flip-flop for measuring the delay may be added to the gate path of the actual circuit, or may be arranged in the chip for the purpose of measuring the delay. Various means for measuring the delay are conceivable and are not limited to the means described in this embodiment. It should be noted that the number of transistors constituting the gate path should be large in order to accurately reflect chip variations.

  The second holding unit 5 is a memory that holds heat resistance information for each chip indicating the degree of heat passing from each chip to the outside of the multichip system, depending on the mounting form of each chip. This thermal resistance information can be obtained based on the results of thermal analysis performed when selecting a package or designing heat dissipation in a set device. For example, if the package shown in FIG. 7 is subjected to thermal analysis, the chip 2 in the upper part needs to release heat to the air through the resin, so that the thermal resistance increases, but the chip 1 in the lower part passes through the interposer set substrate. It is possible to obtain heat resistance information that the heat resistance is low because heat easily escapes. This thermal resistance information can also be considered as information indicating where the chip is mounted in the multi-chip configuration.

  The power estimation unit 6 estimates the leakage power of each chip when task processing is allocated to the chips 1 and 2 based on the leakage current information and the thermal resistance information. The power estimation unit 6 obtains the magnitude of the leakage power of the chip from the leakage current information and thermal resistance information of each chip using a table as shown in FIG. The horizontal axis of the table indicates leakage current due to manufacturing variation, and the vertical axis indicates thermal resistance information determined by the mounting form. “Leakage current” in the figure is classified into three stages: small, medium and large. Small, medium, and large leak currents correspond to high, medium, and low threshold voltage Vt of the transistor. The description example of (current value) indicates, for example, leakage current per 1000 transistors. This current value is converted into a leak current corresponding to the total number of transistors in the chip. “Thermal resistance” indicates an elevated temperature per 1 W, and is classified into three stages.

  Numerical values 1 to 9 in the table are numerical values indicating the magnitude of the leakage power, and a larger numerical value indicates that the leakage power is larger. The numerical value indicating the magnitude of the leakage power can be calculated from the power obtained by adding the leakage power depending on the task operating power and temperature, and the temperature in the chip. Details will be described later.

  The power comparison unit 7 compares power consumption including leakage power.

  The task management unit 8 allocates tasks to chips so that power consumption is reduced, and puts unallocated chips into a power saving state.

  Next, an operation example of the multichip system configured as described above will be described.

  FIG. 9 is a flowchart showing an operation example of the multi-chip system in the present embodiment. FIG. 10A and FIG. 10B are tables showing examples of chip temperature, leakage current, power consumption estimation results, and the like.

  10A and 10B, the leakage current and the thermal resistance are information unique to the chip, the leakage current is obtained from the leakage current information, and the thermal resistance is obtained from the thermal resistance information. Chip 1 is finished to low Vt with large leakage current due to manufacturing variations, and chip 2 is finished to medium Vt. Thermal resistance is 5 ° C / W for chip 1, 15 ° C / W for chip 2, and operating power is Both chip 1 and chip are set to 5 mW / MHz.

  Ta represents the maximum ambient temperature assumed in the environment where the multichip system is installed.

  The operating frequency Freq is the operating frequency of the chip and further indicates task allocation candidates. That is, the operating frequency is regarded as a band indicating the processing capacity of the chip, and means a band allocated to a task. In the example of FIGS. 10A and 10B, both chip 1 and chip 2 are chips that operate at a maximum operating frequency of 1 GHz, and the task processing amount can be processed at 1 GHz. That is, a task that can be processed by either one of the chips operating.

  P_act indicates operating power ignoring leakage power. Tj represents a chip temperature (for example, a junction temperature between the chip surface and the package). P_Leak is the leakage power, and P_total is the total power consumption obtained by adding the operating power P_act and the leakage power P_leak. The numerical value shown in the Total row is the sum of the power of chip 1 and chip 2.

  In FIG. 9, the task management unit 8 first sets task allocation candidates (S91). For example, the task management unit 8 sets allocation of a task to a chip 1 operating at an operating frequency of 1 GHz in the example of FIG. 10A as an allocation candidate. In the example of FIG. 10B, the task is set to be allocated to the chip 2 operating at the operating frequency of 1 GHz.

  Next, the power estimation unit 6 estimates power from the leakage power information and the thermal resistance information for each allocation candidate (loop 1) and for each chip (loop 2) (S94).

  Specifically, in step S94, the power estimation unit 6 estimates the chip temperature Tj (S941), estimates the leakage power P_leak from the chip temperature Tj (S942), and estimates the power P_total (S943). , Repeat until P_leak is almost converged.

  In the estimation of the chip temperature Tj in step S941, first, the chip temperature Tj is estimated from thermal resistance × total power + ambient temperature (Ta). In step S942, the leakage power at the chip temperature Tj is estimated from the characteristic of leakage power with respect to temperature shown in FIG. The characteristics in FIG. 12 are created by the power estimation unit 6 from the table shown in FIG.

  In step S943, the leakage power P_leak is added to the operating power P_act. Furthermore, in the end determination in step S944, it is determined whether the chip temperature Tj, the leakage power P_leak, or the total power P_total has sufficiently converged. If not sufficiently converged, S941 to S943 are executed again.

  In step S94, when the operating frequency Freq is 0, the operating power and the leakage power are 0 due to a general-purpose low-power technique such as shutting off the supply of the clock signal or shutting off the power supply. I reckon.

  In addition, in the end determination of step S944, it may be determined whether or not a predetermined number of times such as 5 times and 10 times has been repeated, or the difference between the previous chip temperature Tj and the current chip temperature Tj is equal to or less than a threshold value. It may be determined whether or not there is, or it may be determined whether or not the difference between the previous leakage power P_leak and the current leakage power P_leak is equal to or less than a threshold value.

  Furthermore, the power comparison unit 7 calculates the power consumption (sum of P_total) of the multichip chip system, compares the power consumption, and assigns priorities in ascending order of power consumption (S97). The priority may be a chip priority or an allocation candidate priority. From FIG. 10A, the total power of chip 1 and chip 2 when processing is performed with chip 1 is 5.6 W. On the other hand, when processing is performed with the chip 2 from FIG. In this case, the priority of the allocation candidates is in the order of the allocation candidates in FIG. 10A and the allocation candidates in FIG. 10B. The priority of chips is the order of chip 1 and chip 2. The power comparison unit 7 may give the leakage power or the priority of the chip, and in the case of FIGS. 10A and 10B, the order is the chip 1 and the chip 2.

  Next, the task management unit 8 selects a candidate or chip with the lowest power consumption according to the priority, and allocates a task to the chip according to the selection (S98). At this time, if there is a chip to which no task is allocated, the power saving state is set. The power saving state is caused by reducing the frequency of the clock signal, cutting off the supply of the clock signal, cutting off the power supply, or the like. As described above, when one of the two chips having the same processing performance is processed, the result of the total power of the multi-chip varies depending on the leakage current information and the thermal resistance information. In this example, the power allocated to the chip 1 can be reduced by assigning tasks to the chip 1. If the task cannot be processed by only one chip, the chip 1 is operated at 1 GHz, and the portion that cannot be processed by the chip is allocated to the chip 2, thereby reducing the total power of the multichip system.

  11A and 11B are tables showing other examples of chip temperature, leakage current, power consumption estimation results, and the like. Here, an example will be described in which task 1 requiring a 1000 MHz band (processing capability) and task 2 requiring a 500 MHz band are allocated to chip 1 and chip 2. Note that the chip-specific information and the maximum ambient temperature Ta are the same as those in FIGS. 10A and 10B.

  In FIG. 11A, allocation candidates are set to (task 1, chip 1, 1000 MHz) and (task 2, chip 2, 500 MHz), and in FIG. 11B, allocation candidates are (task 1, chip 2, 500 MHz) and (task 2, chip 1, 1000 MHz). That is, the task management unit 8 sets a plurality of sets of (task processing, chip, minimum operating frequency required for executing the task processing in the chip) as allocation candidates.

  For this allocation candidate, the power estimation unit 6 estimates the chip temperature Tj, the leakage power P_leak, and the power P_total according to the flow shown in FIG.

  In the estimation result of FIG. 11A, the total power consumption is 8.3 W, and in the estimation result of FIG. 11B, the total power consumption is 8.8 W. In this case, the power comparison unit 7 assigns priorities to the allocation candidates in the order of the allocation candidates in FIG. 11A and the allocation candidates in FIG. 11B, or chip 1 and chip 2 for both task 1 and task 2. Chip priority is given in the order of 2. As shown in FIG. 11A, the task management unit 8 allocates task 1 to chip 1, assigns its operating frequency to 1000 MHz, assigns task 2 to chip 2, and sets its operating frequency to 500 MHz so that power consumption is reduced. To do.

  As described above with reference to FIGS. 11A and 11B, by setting an allocation candidate including the operating frequency (processing capability) for each chip, each chip in the execution of one task process or a plurality of task processes is set. The power consumption can be optimized including the optimization of the operating frequency.

  In FIG. 1, the number of chips that execute task processing is not limited to two, and may be three or more. The two chips in FIG. 1 may be molded in one package or may be mounted in another package. The multichip system 100 of FIG. 1 may be mounted in one package, or may be mounted as two or more packages.

  Next, an example in which the multichip system 100 of FIG. 1 is configured with three packages will be described.

  FIG. 2 is a block diagram showing a more detailed configuration example of a multichip system including three packages. The multi-chip system 101 includes three packages including a chip 10, a chip 20, and a controller 3, and is functionally equivalent to the multi-chip system 100 of FIG. 1, but differs in the following points. Hereinafter, description of the same points will be omitted, and different points will be mainly described.

  The leakage current information holding unit 14 and the leakage current information holding unit 24 correspond to the first holding unit 4 in FIG. That is, the leakage current information holding unit 14 holds the leakage current information of the chip 1, and the leakage current information holding unit 24 holds the leakage current information of the chip 2.

  The chip 10 has a configuration in which a leakage current information holding unit 14 is added to the chip 1 of FIG.

  The chip 20 has a configuration in which a leakage current information holding unit 24 is added to the chip 2 of FIG.

  The power estimation unit 16 and the power estimation unit 26 correspond to the power estimation unit 6 in FIG. That is, the power estimation unit 16 estimates the chip temperature, leakage power, and power consumption of the chip 10. The power estimation unit 26 estimates the chip temperature, leakage power, and power consumption of the chip 20.

  The controller 3 includes a second holding unit 5, a power estimation unit 16, a power estimation unit 26, a power comparison unit 7, and a task management unit 8. The controller 3 and the chip 10 and the controller 3 and the chip 2 are connected by wiring or communication lines.

  Further, a multi-chip system having a two-package configuration will be described as a multi-chip system having a different mounting form from FIGS.

  FIG. 13 is a block diagram showing a more detailed configuration example of a multi-chip system including two packages.

  The multi-chip system 102 shown in FIG. 1 includes two packages of chip 1 and chip 20. In FIG. 13, compared with FIG. 12, the chip 11 includes a task processing unit 13, a leakage current information holding unit 14, a task management unit 8, a power comparison unit 7, a power estimation unit 16, a power estimation unit 26, and a second holding. Part 5 is provided. In this configuration, the task enters the chip 11 provided with the task management unit 8, and the task is allocated to each chip. The specific example in which the task management unit is provided in any one of the chips constituting the multichip system 102 operates in the same manner as described with reference to FIGS. 1 and 2 above, and configures the multichip system. This configuration is also an option from the viewpoint of mounting costs for the purpose.

(Second Embodiment)
In the present embodiment, the multi-chip system further includes a priority holding unit (8a) that holds the priority given by the power comparison unit 7, and the task management unit holds the priority held in the priority holding unit. A configuration for allocating tasks to chips according to the degree will be described. By holding the priority in the priority holding unit, it is possible to reuse the priority based on the past leakage power estimation and to speed up the task allocation process.

  FIG. 14 is a block diagram showing a configuration of multichip system 200 in the present embodiment. This figure is different from FIG. 1 in that a priority holding unit 81 is added. Hereinafter, description of the same points will be omitted, and different points will be mainly described.

  The priority holding unit 81 holds the priority assigned by the power comparison unit 7. This priority is either or both of the chip priority and the allocation candidate priority.

  FIG. 15 is a flowchart showing an operation example of the multi-chip system in the present embodiment. The figure differs from FIG. 9 in that step S5 is added.

  In step S5, the task management unit 8 determines whether or not the priority is held in the priority holding unit 81. When it is determined that the priority is held, the task management unit 8 proceeds to step S98 and determines that the priority is not held. If so, the process proceeds to step S92. In step S98, the task management unit 8 approaches the task allocation according to the priority, selects a candidate with the lowest power consumption, and allocates the task.

  According to the multi-chip system 200 of the present embodiment, the priority based on the estimation of the past leakage power is reused, so that the task allocation process can be speeded up.

  Note that the priority holding unit 81 may hold the leak power estimated in the past or the power consumption including the leak power instead of the priority of the chip. 14 can be obtained by adding the priority holding unit 81 to the configurations of FIGS. 2 and 13 instead of FIG.

(Third embodiment)
In the present embodiment, a multi-chip system including a leakage current measurement unit that measures leakage current and a thermal resistance measurement unit that measures thermal resistance will be described.

  FIG. 16 is a block diagram showing a configuration of multi-chip system 300 in the present embodiment. This figure is different from FIG. 14 in that a leakage current measuring unit 40 and a thermal resistance measuring unit 50 are added. Hereinafter, description of the same points will be omitted, and different points will be mainly described.

  The leakage current measuring unit 40 measures the characteristics of the leakage current of each chip and stores the leakage current information in the first holding unit 4. The leakage current measuring unit 40 measures the leakage current using, for example, a circuit under measurement such as FIG. 3, FIG. 5, or FIG. 6A. In other words, the leakage current measuring unit 40 may measure the current between the power supply and the GND of the circuit (FIG. 3) that actually operates in the chip, and is arranged in the chip for the purpose of obtaining finished information. The leakage current of the transistor (FIG. 5) may be measured. Preferably, the number of transistors is large in order to accurately reflect chip variations.

  Further, the leakage current information resulting from the manufacturing variation of the present invention may indicate the gate delay time. In this case, the leakage current measuring unit 40 may measure the gate delay time from a circuit that performs actual operation, or may be a circuit under measurement (FIG. 6A) arranged in a chip for the purpose of obtaining finished information. . Preferably, many transistors are used in order to accurately reflect chip variations. The timing for measuring the transistor may be during inspection or during actual operation. When it is measured at the time of inspection, it includes storing in a non-volatile memory in the measured chip.

  The thermal resistance measurement unit 50 measures the difficulty of passing heat from the chip 1 to the outside of the multi-chip system 300 (that is, thermal resistance), and measures the difficulty of passing heat from the chip 2 to the outside of the multi-chip system 300 to obtain thermal resistance information. To be held by the second holding unit 5.

  The timing measured by the leakage current measuring unit 40 and the thermal resistance measuring unit 50 may be every time task processing is started or every certain period. The measurement timing of the leakage current measurement unit 40 and the measurement timing of the thermal resistance measurement unit 50 may be different.

  According to the multi-chip system 300 of the present embodiment, the thermal resistance measurement unit 50 can measure the thermal resistance at any time, so even if the thermal resistance of the chip is changed dynamically or statically, the power consumption can be reduced. Reduction can be optimized. For example, power consumption is optimized by measuring thermal resistance even when the mounting form of the multi-chip system is not fixed at the time of factory shipment or when the mounting form or environment of the multi-chip system changes after factory shipment. be able to.

  In addition, since the leakage current can be measured by the leakage current measuring unit 40 at any time, the reduction in power consumption can be optimized when the leakage current of the chip changes due to a change in power supply voltage or aging.

  Note that, in place of FIG. 16, the same effect as in FIG. 16 can be obtained by adding a leakage current measurement unit 40 and a thermal resistance measurement unit 50 to the configurations of FIGS. 2 and 13.

(Fourth embodiment)
In the present embodiment, a configuration in which a function for setting priority is separated from the multichip system in each of the above embodiments will be described.

  FIG. 16 is a block diagram showing a configuration of the multichip system 400 and the priority setting device according to the present embodiment. The multichip system 400 shown in the figure is different from the multichip system 300 shown in FIG. 16 in that the components of the portion (priority setting device 500) indicated by the broken line are deleted.

  The priority setting device 500 assigns the thermal resistance and leakage current of the multi-chip system 400 from estimation to chip priority (S91 to S97 in FIG. 9), and causes the priority holding unit 81 to hold the priority. The priority setting device 500 may be a part of a manufacturing device in a factory that manufactures the multichip system 400. Alternatively, a dedicated device for assisting the multichip system 400 may be used. In the priority setting device 500, for example, the form in which the multi-chip system 400 is mounted is clear in advance, and the thermal resistance information can be estimated before factory shipment, or the mounting form of the multi-chip system 400 is changed. For example, the priority is set in the priority holding unit 81.

  According to this configuration, in addition to the effects of the above-described embodiment, the circuit scale (chip size) of the multichip system 400 can be reduced and the cost can be reduced.

(Applied products)
The multichip system according to the present invention is applicable to all information devices such as portable information terminals and portable music players.

  FIG. 18A shows an overview of a communication device provided with a multichip system according to the present invention. The mobile phone 130 includes a baseband chip 131 and an application chip 132. The baseband chip 131 and the application chip 132 have the same configuration as the two chips shown in each embodiment.

  Since the multi-chip system according to the present invention can reduce power more than before, the power can also be reduced for the baseband chip 131, the application chip 132, and the mobile phone 130 including these. The multi-chip system according to the present invention can be applied to communication devices such as a transmitter, a receiver, and a modem device in a communication system. That is, according to the present invention, it is possible to reduce the power consumption of any communication device regardless of whether it is wired / wireless, optical communication / electrical communication, or digital method / analog method.

  FIG. 18B shows an overview of another communication device equipped with the multichip system according to the present invention. This figure is different from FIG. 18A in that two multichip systems are provided instead of one. That is, the mobile phone 135 includes a baseband multichip 136 and an application multichip 137. The baseband chip 131 is a multi-chip system including chips 136a and 136b having the same configuration as the two chips shown in the embodiments. The application multichip 137 is a multichip system including chips 137a and 137b having the same configuration as the two chips shown in the embodiments.

  Since the multichip system according to the present invention can reduce electric power more than before, the baseband multichip 136, the application multichip 137, and the mobile phone 135 including these can also reduce electric power. The multi-chip system according to the present invention can be applied to communication devices such as a transmitter, a receiver, and a modem device in a communication system. That is, according to the present invention, it is possible to reduce the power consumption of any communication device regardless of whether it is wired / wireless, optical communication / electrical communication, or digital method / analog method.

  In FIG. 18B, a single multichip system may be configured by four chips 136a, 136b, 137a, and 137b.

  FIG. 19A shows an overview of an AV device (video / audio device) provided with a multichip system according to the present invention. The television receiver 110 includes an image / audio processing chip 111 and a display sound source control chip 112. The audio / video processing chip 111 and the display sound source control chip 112 have the same configuration as the two chips shown in each embodiment. Since the multi-chip system according to the present invention can reduce power more than before, the video / audio processing chip 111, the display sound source control chip 112, and the television receiver 110 including these can also reduce power. The multichip system according to the present invention can be applied to all AV equipment such as an optical disk recording device, a digital still camera, and a digital video camera.

  FIG. 19B shows an overview of another AV device (video / audio device) provided with the multichip system according to the present invention. The figure differs from FIG. 19A in that two multichip systems are provided instead of one.

  That is, the television receiver 115 includes an image / audio processing multichip 116 and a display sound source control multichip 117. The image / audio processing multichip 116 is a multichip system including chips 116a and 116b having the same configuration as the two chips shown in the embodiments. The display sound source control multichip 117 is a multichip system including chips 117a and 117b having the same configuration as the two chips shown in the embodiments.

  Since the multi-chip system according to the present invention can reduce power more than before, the video / audio processing chip 111, the display sound source control chip 112, and the television receiver 110 including these can also reduce power. The multichip system according to the present invention can be applied to all AV equipment such as an optical disk recording device, a digital still camera, and a digital video camera.

  In FIG. 19B, one multi-chip system may be configured by four chips of chips 116a, 116b, 117a, and 117b.

  FIG. 20A shows an overview of an automobile as a moving body equipped with a multichip system according to the present invention. The automobile 120 includes an electronic control unit (ECU) 121. The electronic control device 121 includes an engine / transmission control chip 122. In addition, the automobile 120 includes a navigation device 123. The navigation device 123 includes a navigation chip 124. The transmission control chip 122 and the navigation chip 124 have the same configuration as the two chips shown in each embodiment. Since the multichip system according to the present invention can reduce electric power more than before, the engine / transmission control chip 122 and the electronic control device 121 having the same can also reduce electric power. Similarly, the navigation chip 124 and the navigation device 123 including the navigation chip 124 can also reduce power. Then, as the electronic control device 121 reduces power, the power of the automobile 120 is also reduced. Note that the multichip system according to the present invention can be applied to all mobile objects including an engine, a motor, and the like, which are power sources, such as trains and airplanes.

  FIG. 20B shows an overview of an automobile as another moving body including the multichip system according to the present invention. This figure is different from FIG. 20A in that two multichip systems are provided instead of one. First, the automobile 125 includes an electronic control unit (ECU) 126. The electronic control unit 126 is a multi-chip system including an engine / transmission control multi-chip 127 including chips 127a and 128b having the same configuration as the two chips shown in the embodiments. The automobile 125 includes a navigation device 128. The navigation device 128 is a multi-chip system including a navigation chip 128 including chips 129a and 129b having the same configuration as the two chips shown in the embodiments.

  Since the multichip system according to the present invention can reduce electric power more than before, the engine / transmission control chip multi 126 and the electronic control device 12 including the same can also reduce electric power. Similarly, the navigation multichip 129 and the navigation device 128 including the navigation multichip 129 can also reduce power. Then, as the electronic control device 126 reduces power, the power of the automobile 120 is also reduced. Note that the multichip system according to the present invention can be applied to all mobile objects including an engine, a motor, and the like, which are power sources, such as trains and airplanes.

  In FIG. 20B, one multi-chip system may be configured by four chips 127a, 127b, 129a, and 129b.

  Moreover, each multichip system in FIGS. 18A to 20B may include three or more chips.

  18A to 20B illustrate an example in which two chips are arranged side by side, they may be arranged one above the other or may be arranged apart from each other.

  Although the multichip system 100 of the present invention has been described based on the embodiments, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which carried out the various deformation | transformation which those skilled in the art can think to this embodiment, and the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  The present invention is suitable for a multi-chip system or the like having two or more chips for performing task processing, and in particular, AV equipment such as an optical disk recording device, a digital still camera, a digital video camera, a transmitter, a receiver, and a modem device. It is suitable for communication devices such as automobiles, trains, airplanes, etc., and mobile bodies (transportation aircraft) equipped with engines and motors that are approximately power sources.

1, 2, 10, 11, 20 Chip 3 Controller 4 First holding unit 5 Second holding unit 6, 16, 26 Power estimation unit 7 Power comparison unit 8 Task management unit 13, 23 Task processing unit 14, 24 Leakage current information Holding unit 16a, 26a Table 40 Leakage current measuring unit 50 Thermal resistance measuring unit 81 Priority holding unit 100, 101, 102, 200, 300, 400 Multichip system 110, 115 Television receiver 111 Image sound processing chip 112 Display sound source Control chip 116 Video / audio processing multichip 116a, 116b Chip 117 Display sound source control multichip 117a, 117b Chip 120, 125 Automobile 121 Electronic controller 122 Transmission control chip 123 Navigation device 124 Navigation chip 127 Trans Mission Control multichip 127a, 127b chip 129 navigation multichip 129a, 129b chips 130 and 135 mobile telephone 131 baseband chip 132 application chip 136 baseband multichip 136a, 136 b chip 137 application multichip 137a, 137b chip 500 priority setting device

Claims (16)

A multi-chip system having two or more chips to perform a task,
A first holding unit for holding leakage current information for each chip indicating leakage current characteristics of transistors in the chip;
A second holding unit for holding thermal resistance information for each chip indicating the degree of heat passing from each chip to the outside of the multichip system;
Based on the leakage current information and thermal resistance information, a power estimation unit that estimates the leakage power of each chip when the task processing is allocated;
A power comparison unit for comparing power consumption including the leakage power;
A multi-chip system comprising: a task management unit that allocates tasks to chips so that power consumption is reduced according to the comparison result. The power estimation unit
It has a table showing a characteristic curve indicating the correspondence between chip temperature and leakage power,
The chip temperature is estimated by adding the product of the thermal resistance value indicated by the thermal resistance information and the power consumption of the chip, and the assumed maximum value of the ambient temperature,
The multichip system according to claim 1, wherein the leakage power is estimated from the estimated chip temperature and the table. The multichip system according to claim 2, wherein the power estimation unit repeats the estimation of the chip temperature and the estimation of the leakage power a predetermined number of times. The power estimation unit repeats the estimation of the chip temperature and the estimation of the leakage power until a predetermined condition is satisfied,
The multi-chip system according to claim 2, wherein the predetermined condition is that a difference between a previously estimated chip temperature or leakage current and a current estimated chip temperature or leakage current is equal to or less than a threshold value. The multi-chip system according to any one of claims 1 to 4, wherein the task management unit sets a chip to which the task processing is not allocated to a power saving state. The task management unit sets a plurality of combinations of task processing, a chip, and a minimum operating frequency required to execute the task processing in the chip as allocation candidates,
The multichip system according to any one of claims 1 to 5, wherein the power estimation unit estimates a leak current for each of the allocation candidates. The power comparison unit further compares the leakage power or power consumption for each chip, and gives priority to the order of smaller results of comparison,
The multi-chip system further includes a priority holding unit that holds the priority,
The multi-chip system according to any one of claims 1 to 6, wherein the task management unit allocates tasks to chips according to the priority held in the priority holding unit. The multichip system further includes:
The heat resistance measurement unit according to claim 1, further comprising: a thermal resistance measurement unit that measures the degree of heat passing from each chip to the outside of the multichip system and holds the heat resistance information in the second holding unit. Multi-chip system. The multichip system further includes:
The multichip system according to any one of claims 1 to 8, further comprising: a leakage current measurement unit that measures a leakage current characteristic of each chip and causes the first holding unit to hold the leakage current information as the leakage current information. The multichip system according to claim 1, wherein the leakage current information of the transistor indicates a source-drain current. The multichip system according to claim 1, wherein the leakage current information of the transistor indicates a gate delay time. The multichip system according to any one of claims 1 to 11, wherein one of the two or more chips includes the second holding unit, the power estimation unit, and the task management unit. A multi-chip system,
Two or more chips that perform the task;
The priority depends on the leakage current information for each chip indicating the leakage current characteristics of the transistors in the chip and the thermal resistance information for each chip indicating how hard the heat is from the chip to the outside of the multichip system. A priority holding unit that holds the priority of the chip indicating the order of the power, and
A multi-chip system comprising: a task management unit that allocates tasks to chips so that power consumption is reduced according to the priority.   A communication device comprising the multichip system according to claim 1.   A video / audio apparatus comprising the multichip system according to claim 1.   An automobile comprising the multichip system according to claim 1.

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