JP2012137832A - Data transfer device and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device capable of improving validity of data, and in which a writing side and a reading side can freely read/write, without constraint of access to each other.SOLUTION: A data transfer device comprises: a memory 11 composed of at least two surfaces; a data transmission unit 10 switching the memory 11 of a writing destination in a prescribed order and transmitting data in a prescribed period to write the data in the memory 11; a data reception unit 12 simultaneously receiving data from the memory including at least two surfaces in a period which does not depend on the period for writing; a determination information addition unit 13 adding determination information unique to each piece of data, to the data which the data transmission unit 12 transmits to the memory; and a determination information inspection unit 15 determining whether or not the data is valid using the determination information added to the data which the data reception unit 12 receives from the memory 11, and notifying the determination result to the data reception unit.

Description

  The present invention relates to a data transmission apparatus and method for writing and reading data to and from a memory without depending on each other.

  For example, an apparatus is known in which data that is updated as needed is fetched from an external network and processed by an arithmetic processing unit. In this apparatus, received data is temporarily stored in a memory or storage, and an arithmetic processing unit reads the data from the memory and performs arithmetic processing.

  In this case, there is a demand for the operations on the memory writing side and the memory reading side to be performed freely without depending on each other's operations. In addition, when the data writing speed and the reading speed are different or the periods are different, a dual port memory which is a memory (RAM) provided with two ports for data input / output may be used.

  On the other hand, memories such as SRAM (Static Random Access Memory) and SDRAM (Synchronous DRAM), which can be read (read) / written (written) at high speed, have become mainstream. For this reason, the dual port memory has declined, and there is a problem with long-term stable supply. In addition, when data of the same address is read / written simultaneously in both ports of the dual port memory, processing may conflict and the data may become indefinite.

  There is a method of performing exclusive access control using a SRAM or SDRAM to switch data lines and perform input / output by controlling between a writing side and a reading side. When accesses are made simultaneously from the writing side and the reading side, either one of them must wait for access in this method.

  As a problem of both the SRAM / SDRAM and the dual port memory, in one access cycle to the memory, data having a significant meaning with a data length longer than the data bit width (8 bits, 16 bits, etc.) is referred to as “data string”. ) Transfer, if data is updated by a write access to a data string in the same address area during a read access to a certain data string, the old data (previously written data) New data (data written this time) will be mixed.

  Therefore, conventionally, a technique for determining whether or not data that has been rewritten this time and data that has been rewritten last time is mixed in the read data frame has been disclosed (see, for example, Patent Document 1). .

JP 2003-32317 A

  In order to avoid the mixing of data, it is conceivable to divide the memory area into two parts by dividing the address area of the memory or by using physically different memories. As a result, when a write access is made to one memory area, a read access can be made to the other memory area.

  For example, there is a method of avoiding mixing of data by permitting surface switching on the reading side after completion of writing in units of data strings and not reading the data strings during a significant data string update. It is done.

  However, in this case, the memory cannot be switched on the reading side unless writing of the data string is completed. For this reason, there is a restriction that write access and read access must confirm each other's situation.

  The present invention has been made to solve the above-described problem, and the writing side and the reading side are not restricted by each other's access and can be freely read and written to improve the effectiveness of data. An object of the present invention is to provide a data transfer apparatus and a data transfer method capable of performing the above.

  In order to solve the above-described problem, the data transfer device according to the present invention switches a plurality of memories having at least two surfaces and the write destination memory in a predetermined order and transmits data at a predetermined cycle. A data transmission unit for writing to the memory, a data reception unit for simultaneously receiving the data from the memory on at least two of the plurality of memories in a cycle independent of the cycle of the writing, and the data transmission unit A determination information adding unit for adding determination information unique to each data to the data to be transmitted to the memory, and the data using the determination information added to the data received from the memory by the data receiving unit. And a determination information inspection unit that determines whether the data is valid and notifies the data reception unit of the determination result.

  In the data transfer apparatus and method according to the present invention, the writing side and the reading side can be freely read / written without being restricted by mutual access. In addition, the validity of the data can be improved.

1 is a block diagram showing a first embodiment of a data transfer apparatus according to the present invention. Explanatory drawing which shows the structural example of a dual port memory. Explanatory drawing which shows the structural example of what implement | achieved the function equivalent to a dual port memory using SRAM or SDRAM. Explanatory drawing which shows especially the 1st memory of a data transfer apparatus, the determination information production | generation addition part, and the determination information extraction test | inspection part. The figure which shows an example of the memory structure of a 1st memory. The figure which shows the example of data string arrangement | positioning to the 1st memory of the data strings 1-3. The figure which shows the example of data sequence arrangement | positioning to the 1st memory of the data sequence (data sequence 2) with which the sequence number and the reverse sequence number were added to the header and footer. The figure which showed the example when the synchronism of the data sequence 2 is not maintained along the time-axis. The figure which shows the example of data sequence arrangement | positioning in case the synchronism of the data sequence 2 in a 1st memory is not maintained. Explanatory drawing which shows the data transfer apparatus as a comparative example. The timing diagram in case the switching timing of the write side and read side of a memory has a dependency. The timing diagram when the switching timing of the write side and read side of the memory is not dependent. The timing diagram of the write access of the data transfer apparatus in 1st Embodiment, and read access. 5 is a flowchart for explaining processing on the write side of the data transfer apparatus according to the first embodiment. 6 is a flowchart for explaining processing on the read side of the data transfer apparatus according to the first embodiment. The timing diagram of the write access and read access of a data transfer apparatus in the case of reading from two memories simultaneously. FIG. 5 is a timing chart of write access and read access of the data transfer apparatus when reading is performed from two memories at the same time and synchronization is not ensured. FIG. 4 is a timing chart of write access and read access of the data transfer apparatus when reading is performed from two memories at the same time and synchronization can be ensured. The flowchart explaining the process by the side of a read in case a data transfer apparatus reads simultaneously with respect to the memory of 2 surfaces. The figure which shows the data string arrangement | positioning example of the data for determining the validity of data. The block diagram which shows 2nd Embodiment of the data transfer apparatus which concerns on this invention. The timing diagram of the write access and read access of the data transfer apparatus in 2nd Embodiment.

  Embodiments of a data transfer apparatus and method according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a first embodiment of a data transfer apparatus according to the present invention.

  The data transfer apparatus 1 receives, for example, data updated from time to time received from an external network at the data receiving unit 10, and the first memory 11a to the third memory 11c (particularly the first to third memories 11a to 11c). If there is no distinction, the data is simply temporarily stored in “memory 11”). The data transfer device 1 reads out the data stored in the memory 11 by the arithmetic processing unit 12 and performs arithmetic processing.

  The data receiving unit 10 receives data updated as needed from an external network. The data receiving unit 10 supplies the received data to the determination information generation / addition unit 13. The data receiving unit 10 supplies an address for writing data (address A) and a control signal (write A) for causing the memory 11 to write (write) to the memory 11 via the selector (SELA) 14a. Further, the data receiving unit 10 supplies a surface switching signal (surface switching A) for instructing the selector 14a to switch the memory 11 that stores data. In the first embodiment, the data receiving unit 10 is a data transmitting unit that switches the write destination memory in a predetermined order, transmits data at a predetermined cycle, and writes the data to the memory 11.

  The determination information generation / addition unit 13 generates a sequence number and an inverted sequence number as determination information, adds them to the data supplied from the data reception unit 10 and supplies the data to the selector 14a.

  The selector 14 a switches the memory 11 that stores data based on the surface switching signal notified from the data receiving unit 10.

  The memory 11 is a memory that can execute writing and reading simultaneously. The memory 11 is configured by, for example, a dual port memory or a memory that realizes a function equivalent to a dual port memory using a memory such as SRAM (Static Random Access Memory) or SDRAM (Synchronous DRAM). The memory 11 is provided with at least three surfaces, and each is a physically different memory.

  FIG. 2 is an explanatory diagram showing a configuration example of the dual port memory 20.

  FIG. 3 is an explanatory diagram showing an example of the configuration in which a function equivalent to a dual port memory is realized using SRAM or SDRAM.

  The dual port memory 20 is a memory (RAM) provided with two ports for data input / output.

  Even if the memory “which realized the function equivalent to the dual port memory using SRAM or SDRAM” is the memory 21 that cannot be written and read simultaneously like SRAM and SDRAM, the data / control bus on the A side and B By having the access arbitration unit 22 that performs arbitration with the data / control bus on the side, a function equivalent to a dual port memory can be realized.

  For example, the access arbitration unit 22 gives the access right of the memory 21 to the A side when an access on the A side occurs, and gives the access right of the memory 21 to the B side when an access on the B side occurs. In addition, when the other access occurs during one access, the access arbitration unit 22 temporarily waits for the other access, and gives an access right to the other after the end of the one access. The method of giving the access right is first-come-first-served basis or always alternates.

  Determination information extraction / inspection units 15a to 15c (simply referred to as “determination information extraction / inspection unit 15” unless otherwise distinguished) extract the sequence number and inverted sequence number added to the data string by the determination information generation / addition unit 13. The data string is checked to see if it is valid, and the result is supplied to the arithmetic processing unit 12.

  The selector (SELB) 14b performs switching of the memory from which data is read based on the surface switching signal (surface switching B) supplied from the arithmetic processing unit 12.

  The arithmetic processing unit 12 reads (reads) the data string from the memory 11 via the selector 14b, and performs a required arithmetic process on the read data string. The arithmetic processing unit 12 supplies an address for reading data (address B) and a control signal (read B) for reading data from the memory 11 to the memory 11 via the selector (SELB) 14b. The arithmetic processing unit 12 reads data at an arbitrary timing (cycle) without depending on the reception timing (write timing) of the data reception unit 10. In the first embodiment, the arithmetic processing unit 12 is a data receiving unit that simultaneously receives data from at least two memories in a cycle that does not depend on the write cycle.

  Next, details of the memory 11, the determination information generation / addition unit 13, and the determination information extraction / inspection unit 15 will be described.

  FIG. 4 is an explanatory diagram specifically illustrating the first memory 11a, the determination information generation / addition unit 13, and the determination information extraction / inspection unit 15a of the data transfer apparatus 1. Since the first to third memories 11a to 11c and the determination information extraction / inspection units 15a to 15c have substantially the same configuration, only the first memory 11a and the determination information extraction / inspection unit 15a will be described in FIG. The description of the selector 14a is omitted.

  FIG. 5 is a diagram illustrating an example of the memory structure of the first memory 11a.

  FIG. 6 is a diagram illustrating an example of data string arrangement of the data strings 1 to 3 in the first memory 11a.

  For example, addresses 0 to n-1 (addresses A0, A1,..., An-2, An-1) are assigned to the first memory 11a, and each data width is composed of k bits (0 to bk-1). It is memory. When a data string (data having a meaningful meaning with a data length longer than the data bit width (here, k bits)) directly stored in the first memory 11a is stored in the data string Address 1 is assigned addresses A0 to Ap-1, data string 2 is assigned addresses Ap to A2p-1, and data string 3 is assigned address areas A2p to A3p-1.

  The determination information generation / addition unit 13 adds a sequence number to the header (head) of the write data A supplied from the data reception unit 10. The determination information generation / addition unit 13 adds an inverted sequence number obtained by bit-inverting the sequence number added to the header to the footer (tail) of the write data A. That is, the determination information generation / addition unit 13 generates write data with a header / footer to which a header and a footer are added.

  FIG. 7 is a diagram illustrating a data string arrangement example in the first memory 11a of the data string (data string 2) in which the sequence number and the inverted sequence number are added to the header and the footer.

  The sequence number is a unique number in the entire area of the first memory 11a, and is a unique number that can identify whether the data is new or old before and after the data string is updated in the same address area. For example, when 10 data strings 1 to 10 are allocated to the entire area of the first memory 11a, 0a, 0b, 0c... (In this case in hexadecimal numbers) each time data is updated in the header of the data string 1. (In fact, it is 8-bit information.) And an inverted sequence number of f5, f4, f3... Is added to the footer. The sequence number 1a, 1b, 1c,... Is added to the header of the data string 2, and the reverse sequence numbers e5, e4, e3,.

  The determination information extraction / inspection unit 15a sequentially reads the sequence number added to the header of the data string read from the first memory 11a, the data string, and the inverted sequence number added to the footer. The determination information extraction / inspection unit 15a compares data obtained by further bit-inverting the inverted sequence number added to the footer and the sequence number added to the header, and determines whether or not these data match.

  FIG. 8 is a diagram illustrating an example in which the synchronization of the data string 2 is not maintained along the time axis.

  FIG. 9 is a diagram illustrating a data string arrangement example when the synchronization of the data string 2 in the first memory 11a is not maintained.

  The sequence number added to the header and the inverted sequence number added to the footer match when added by the determination information generation / addition unit 13. On the other hand, as shown in FIG. 8, the data sequence is written to the first memory 11a while the header sequence number, the data sequence, and the inverted sequence number of the footer are being read sequentially. It can happen that it is updated.

  Specifically, immediately after the read access is started with respect to the data string stored in the first memory 11a, the write access is started at a speed slightly higher than the read speed. When writing is completed before reading is completed, old data before update and new data after update are mixed in the data being read.

  For example, such a problem does not occur when the data string n is read on the read side and the data string n-1 is written on the write side.

  In this case, as shown in FIG. 9, the data in the data string 2 includes a mixture of data before update and data after update. The inverted sequence number added to the footer is data obtained by bit-inverting the sequence number assigned to the updated new write data. For this reason, the sequence number of the header does not match the data obtained by bit-inverting the inverted sequence number of the footer.

  The determination information extraction inspection unit 15a compares the data obtained by further inverting the inverted sequence number added to the footer with the sequence number added to the header, and determines that these data match, the read data is synchronized. A signal indicating that the performance is secured and effective is supplied to the arithmetic processing unit 12.

  On the other hand, if the determination information extraction / inspection unit 15a determines that these data do not match, the determination information extraction / inspection unit 15a determines that the data synchronism is not secured, and supplies a signal indicating that the data is invalid to the arithmetic processing unit 12. To do. The determination information extraction / inspection unit 15a may supply a signal indicating that the data is invalid together with the data to the arithmetic processing unit 12 or may supply only a signal indicating that the data is invalid.

  The determination information extraction / inspection unit 15a holds the sequence number of the data string determined to be valid. The determination information extraction inspection unit 15a compares the held sequence number with the sequence number added to the data read from the first memory 11a in the next cycle. The determination information extraction / inspection unit 15a outputs a skip signal to the arithmetic processing unit 12 when the stored sequence number matches the sequence number added to the read data string. Thereby, the determination information extraction inspection unit 15a notifies that the same data as the data that has not been updated and has already been read is accumulated in the first memory 11a, and the arithmetic processing unit 12 is unnecessary. It is possible to prevent reading.

  In the data transfer apparatus 1 of FIG. 1, the example in which the data receiving unit 10 is the data transmission side (write side) and the arithmetic processing unit 12 is the data reception side (read side) has been described. You can also replace the lead side.

  Next, an operation in the case where the memory 11 is switched when the data transfer apparatus 1 performs writing and reading will be described.

  Prior to the description of the operation of the data transfer apparatus 1 in the first embodiment, a problem of the data transfer apparatus that can be assumed will be described.

  FIG. 10 is an explanatory diagram showing a data transfer apparatus 100 as a comparative example. The data transfer apparatus 100 has two memories. The two-plane memory is switched by the plane switching signal so that one of the memories is the write side and the other is the read side. The dual port memories 101a and 101b and the selectors 102a and 102b are substantially the same as the memory 11 and the selectors 14a and 14b in FIG.

  FIG. 11 is a timing chart when the switching timing of the write side and the read side of the memory has a dependency relationship. FIG. 12 is a timing chart when the switching timing of the write side and the read side of the memory is not dependent.

  In the memories 101a and 101b, the address area is divided, or the memory area is divided into two by having physically different memories. As a result, when the data transfer apparatus 100 has write access to one memory area, the data transfer apparatus 100 performs read access to the other memory area.

  Switching between memory areas for writing and reading access is performed by permitting surface switching to the read side by a surface switching signal after completion of writing in units of data strings. As a result, as shown in FIG. 11, during the update of a significant data string, the timing of write access and read access is switched simultaneously so that the data string is not read.

  However, if the write access of the data string is not completed on the write side, the surface cannot be switched on the read side, so there is a restriction that the write access and the read access must confirm each other's situation.

  On the other hand, as shown in FIG. 12, when the surface switching of the dual port memory of two surfaces is performed at an arbitrary timing on the write side and the read side, the write access and the read access indicated by the arrow A in the figure are performed on the same surface Cannot synchronize the data column.

  On the other hand, the data transfer device 1 according to the first embodiment prevents the data before and after the update from being mixed in the read data by providing three surfaces of the memory 11, that is, maintains the synchronization. can do.

  FIG. 13 is a timing diagram of write access and read access of the data transfer apparatus 1 according to the first embodiment.

  On the write side, the data transfer device 1 writes data in the order of the first memory (first surface) 11a, the second memory (second surface) 11b, and the third memory (third surface) 11c. On the read side, the first memory 11a, the second memory 11b, and the third memory 11c are simultaneously read at an arbitrary timing of the arithmetic processing unit 12. Hereinafter, the flow of processing on the write side and read side will be described with reference to flowcharts.

  FIG. 14 is a flowchart for explaining processing on the write side of the data transfer apparatus 1 in the first embodiment.

  In step S <b> 1, the data transfer apparatus 1 determines whether or not the data receiving unit 10 has received data that is updated as needed from an external network. If the data transfer apparatus 1 determines that data has not been received, the data transfer apparatus 1 waits until it is received. On the other hand, when receiving data, the data transfer apparatus 1 supplies the received data to the determination information generation / addition unit 13 in step S2.

  In step S3, the determination information generation / addition unit 13 generates a sequence number and adds it to the header of the received data. The determination information generation / addition unit 13 adds an inverted sequence number obtained by bit-inverting the sequence number to the data footer.

  In step S <b> 4, the determination information generation / addition unit 13 writes data in the memory 11 based on the surface switching signal A.

  FIG. 15 is a flowchart illustrating processing on the read side of the data transfer apparatus 1 in the first embodiment. This processing on the read side is executed at an arbitrary timing of the arithmetic processing unit 12.

  In step S11, the determination information extraction inspection units 15a to 15c simultaneously read data from the first to third memories 11a to 11c based on the control of the arithmetic processing unit 12. In step S12, the determination information extraction / inspection units 15a to 15c extract the sequence number and the inverted sequence number from the read data.

  In step S13, the determination information extraction / inspection units 15a to 15c determine whether or not the data read from the extracted sequence number and inverted sequence number is valid. If the determination information extraction / inspection unit 15 determines that the data is valid, it supplies a signal indicating that the data is valid to the arithmetic processing unit 12 in step S14. On the other hand, when determining that the data is invalid, the determination information extraction / inspection unit 15 supplies a signal indicating that the data is invalid in step S15.

  In addition, when there are a plurality of valid data among the data read from the plurality of memories 11, the latest data received from the external network can be obtained by using the data sequence to which the latest sequence number is assigned. It can be used for arithmetic processing. In this case, the arithmetic processing unit 12 or the selector 14b has a function of receiving the read data and the sequence number and determining the newness of the data from the sequence number.

  In step S16, the determination information extraction / inspection units 15a to 15c determine whether or not the sequence number added to the previously read data string matches the sequence number added to the data string read this time. Judgment is made. If the determination information extraction / inspection units 15a to 15c determine that the sequence numbers do not match, the process ends.

  On the other hand, if it is determined that the sequence numbers match, the determination information extraction / inspection unit 15 generates a skip signal and outputs it to the arithmetic processing unit 12 in step S17.

  Although an example in which three memories 11 are provided has been described, the number of the memories 11 may be three or more. In this case, the number of memories to be read simultaneously may be at least three.

  According to the data transfer apparatus 1, it is possible to acquire effective data with ensured synchronism by simultaneously reading data from the memories 11 provided on the three surfaces. Specifically, as shown in FIG. 13, when writing (writing) to the first memory (first surface) 11a is performed, the data read from the first memory 11a is in the section indicated by the arrow B. Since writing and reading conflict, data before and after updating are mixed. On the other hand, the data read from the second memory 11b and the third memory 11c is synchronized in the section indicated by the arrow B.

  When the write access and the read access are performed at an arbitrary timing on the write side and the read side, there is a possibility that the memory 11 to be written is switched while the read side is reading data. In FIG. 13, the read side switches from the first memory 11a to the second memory 11b while the read side is reading from the first to third memories 11a to 11c. In this case, since the data read from the second memory 11b competes for writing and reading in the section indicated by the arrow C, the data before and after the update are mixed.

  On the other hand, the data transfer device 1 according to the first embodiment does not write to the third memory 11c even when the memory to which writing is performed during reading is switched from the first memory 11a to the second memory 11b. Since there is no contention with reading, it is possible to read effective data with ensured synchronization.

  The above-described data transfer device 1 reads data simultaneously from three memories. On the other hand, as described below, the two surfaces may be read simultaneously by considering the reading order.

  FIG. 16 is a timing diagram of write access and read access of the data transfer apparatus 1 when reading from the memory 11 on two sides at the same time.

  On the write side, the data transfer device 1 sequentially writes data to the first memory (first surface) 11a, the second memory (second surface) 11b, and the third memory (third surface) 11c. On the read side, at each read timing of the arithmetic processing unit 12, data is read simultaneously from two of the first memory 11a, the second memory 11b, and the third memory 11c. For example, the first memory from which data is read is switched in the order of the first memory 11a, the second memory 11b, and the third memory 11c. The second memory from which data is read is switched in the order of the third memory 11c, the first memory 11a, and the second memory 11b.

  When writing to the first memory (first surface) 11a is performed, the data read from the first memory 11a is data before and after the update because the reading and writing compete in the section indicated by the arrow D. Will be mixed. On the other hand, the data read from the third memory 11c is ensured in synchronism.

  FIG. 17 is a timing diagram of write access and read access of the data transfer apparatus 1 in the case where reading is simultaneously performed from two memories 11 and synchronization is not ensured.

  When reading from the two memories 11 at the same time, depending on the combination of the memories 11 to be read, there is a possibility that the data read from either memory 11 is mixed before and after the update.

  For example, the first memory from which data is read is switched in the order of the second memory 11b, the third memory 11c, and the first memory 11a, and the second memory is switched to the first memory 11a and the second memory 11a. This is a case where the memory 11b and the third memory 11c are switched in this order.

  In this case, when writing to the first memory (first surface) 11a is performed, the data read from the first memory 11a competes between writing and reading in the section indicated by the arrow E. Further, when the memory 11 to be written is switched from the first memory 11a to the second memory 11b, the second memory 11b of the memory 11 being read is written and read in the section indicated by the arrow F. Will compete.

  FIG. 18 is a timing diagram of write access and read access of the data transfer apparatus 1 in the case where reading is simultaneously performed from two memories and synchronization can be ensured.

  The operation on the write side shown in FIG. 18 is substantially the same as that described with reference to FIGS. Regarding the read side operation, when it is determined that both of the simultaneously read data are invalid, valid data is read at the next read timing determined to be invalid by considering the combination of memories to be read next time. A section indicated by an arrow in FIG. 18 is a section in which writing and reading compete.

  Hereinafter, the processing on the read side will be described with reference to flowcharts.

  FIG. 19 is a flowchart for explaining processing on the read side when the data transfer apparatus 1 reads data from two memories simultaneously. In addition, illustration and description were abbreviate | omitted about the step which the determination information extraction test | inspection part 15 produces | generates a skip signal.

  Steps S21 to S25 are substantially the same as the reading step S11 to the invalid signal transmission step S15 in FIG.

  In step S <b> 26, the data transfer apparatus 1 determines whether all the read data is determined to be invalid. This determination is performed by the selector 14b or the arithmetic processing unit 12. If the data transfer apparatus 1 determines that all data is not invalid, that is, if it is determined that valid data is obtained at the current read timing, the process is terminated.

  On the other hand, if the data transfer apparatus 1 determines that all data is invalid, in step S27, regarding the memory 11 that reads data at the next read timing, one of the memories that has been read this time is replaced with the other memory. Shift to a different memory.

  For example, in FIG. 18, the first memory from which data is read is switched in the order of the second memory 11b, the third memory 11c, and the first memory 11a, and the second memory is the first memory. Assume that switching is performed in the order of 11a, second memory 11b, and third memory 11c. When data is read from the two memories 11, the second memory 11 b and the first memory 11 a, the next read timing is normally the third memory 11 c and the second memory as shown in FIG. 17. Data is read from the memory 11b.

  However, if it is determined that the data in both the second memory 11b, which is the first memory, and the first memory 11a, which is the second memory, are invalid, the data transfer device 1 The first memory (second memory 11b) which is a memory is shifted to the third memory 11c which is a different memory from the second memory (first memory 11a) which is the other memory.

  In other words, one memory (first memory 11a) is not shifted, and the other memory (second memory 11b) is shifted to the next-ranked memory (third memory 11c). The memory on the shift side is a memory in which the next rank memory is a memory that is not read at the current read timing.

  Therefore, reading is performed at the next timing from the memory 11 (third memory 11c) from which data has not been read at the current reading timing and the memory 11 (first memory 11a) from which data has been read. Therefore, effective data can be reliably read from either one of the memories 11 from the next time.

  According to the data transfer device 1, the validity of the data to be read can be improved. Further, since the number of the memory 11 that simultaneously reads data can be reduced to two, the capacity of a buffer (not shown) for temporarily storing the data read from the memory 11 can be reduced.

  Note that the determination information for determining the validity of the data string is not limited to the sequence number and the inverted sequence number.

  FIG. 20 is a diagram illustrating an example of data string arrangement for determining the validity of data.

  Based on the data string supplied from the data receiver 10, the determination information generation / addition unit 13 generates an inverted data string obtained by bit-inversion of the data string. The area of the memory 11 in which the inverted data string is stored is determined in advance on the write side and the read side. For example, the area for storing the inverted data string is determined as n + 100 obtained by adding 100 to the address n of the data string.

  The determination information extraction / inspection unit 15 sequentially reads the data string and the inverted data string from the predetermined address area. The determination information extraction inspection unit 15 compares the read data string with data obtained by further inverting the inverted data string. If the determination information extraction and inspection unit 15 determines that these data match, the determination information extraction / inspection unit 15 supplies a signal indicating that the synchronization is ensured and is valid data to the arithmetic processing unit 12. If the determination information extraction / inspection unit 15 determines that these data do not match, the determination information extraction / inspection unit 15 determines that the synchronization of the data is not secured, and supplies a signal indicating that the data is invalid to the arithmetic processing unit 12.

[Second Embodiment]
An embodiment of a data transfer device 40 according to the present invention will be described with reference to the accompanying drawings.

  FIG. 21 is a block diagram showing a second embodiment of the data transfer apparatus according to the present invention.

  The data transfer device 40 in the second embodiment differs from the first embodiment in that it has first and second memories 11a and 11b which are two physically different memories, and a delay instead of the selector 14a. This is a point having a control unit 46. Components and parts corresponding to those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The delay control unit 46 generates a delay so that the same data as the data written to the first memory 11a is written to the second memory 11b after a predetermined time has elapsed after the writing to the first memory 11a. Let The delay time is determined by, for example, the read timing of the arithmetic processing unit 12 and various factors.

  The data receiving unit 10 writes the same data in different memories 11 with a delay time at one write timing (data update timing).

  FIG. 22 is a timing diagram of write access and read access of the data transfer device 40 in the second embodiment.

  On the write side, after the data is written to the first memory 11a by the action of the delay control unit 46, the same data is written to the second memory 11b after the delay time T has elapsed.

  On the read side, the first memory 11a and the second memory 11b simultaneously read at a timing independent of writing. In the section indicated by the arrow G, writing and reading with respect to the first memory 11a compete with each other, and effective data cannot be obtained. However, for the second memory 11b, by providing the delay time T, effective data can be obtained without contention between writing and reading. As a result, the arithmetic processing unit 12 can select valid data from the read data and use it for the arithmetic processing.

  In addition, although the example which provided the memory of 2 surfaces was demonstrated for the data transfer apparatus 40, you may have a memory of 2 surfaces or more.

DESCRIPTION OF SYMBOLS 1, 40 Data transfer apparatus 10 Data receiving part 11a-11c 1st-3rd memory 12 Arithmetic processing part 13 Determination information production | generation addition part 14a Selector (SELA)
14b Selector (SELB)
15a to 15c Determination information extraction and inspection unit 46 Delay control unit

Claims (9)

A plurality of memories of at least two sides;
A data transmission unit that switches the memory of the write destination in a predetermined order and transmits data in a predetermined cycle and writes the data in the memory;
A data receiver that receives the data simultaneously from at least two of the plurality of memories in a cycle that does not depend on the write cycle;
A determination information adding unit that adds determination information unique to each data to the data that the data transmitting unit transmits to the memory;
A determination information inspecting unit that determines whether the data is valid using the determination information added to the data received from the memory by the data receiving unit and notifies the data receiving unit of a determination result; A data transfer device comprising: The data receiving unit receives data simultaneously from at least two of the memories, and when a determination result indicating that both data are invalid is notified, a memory that reads the data in the next read cycle, 2. The data transfer device according to claim 1, wherein one of the memories read this time is switched to a memory different from the other memory. The data receiving unit switches each memory from which the data is read out in a predetermined order, and the memory to be switched in the next reading cycle is such that the memory in the next order is read in the current reading cycle. 3. The data transfer device according to claim 2, wherein the data transfer device is a memory that is not used. The data transfer device according to claim 1, wherein the data transmission unit writes the same data to the two or more different memories with a delay time in one writing period. The determination information is a sequence number that is a unique number that can identify whether the data is new or old before and after the data is updated.
The determination information adding unit adds the sequence number to the header of the data, adds an inverted sequence number obtained by bit-inverting the sequence number to the header of the data,
The determination information inspection unit reads the sequence number and the inverted sequence number, compares the sequence number with information obtained by bit-inverting the inverted sequence number, and if the data match, the data is valid. The data transfer device according to claim 1 for determination. 6. The data transfer device according to claim 5, wherein the data receiving unit uses a data string to which the latest sequence number is assigned when there are a plurality of the data determined to be valid in the simultaneously received data. The determination information inspecting unit holds the sequence number read this time, and when the held sequence number matches the sequence number read next time, the data receiving unit stops reading the data 6. The data transfer device according to claim 5, wherein The determination information is inverted data obtained by bit inverting the data,
The determination information adding unit accumulates the inverted data in a predetermined area of the memory,
The determination information inspection unit reads the inverted data from the predetermined area, compares the data with information obtained by bit-inverting the inverted data, and determines that the data is valid if they match. The data transfer device according to claim 1. Preparing a plurality of memories of at least two sides;
Switching the write destination memory in a predetermined order, and transmitting data in a predetermined cycle and writing to the memory;
Receiving the data simultaneously from at least two of the plurality of memories in a cycle independent of the write cycle; and
Adding determination information specific to each data to the data to be transmitted to the memory;
And determining whether or not the data is valid using the determination information added to the data received from the memory, and notifying a determination result to a destination of the data. Data transfer method.

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