JP2012134251A - High-frequency semiconductor switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor switch capable of forming a good voltage distribution for a gate wire and improving insertion loss characteristics and harmonic characteristics.SOLUTION: A field effect transistor 50 included in a high-frequency semiconductor switch for switching over wireless communication, has: a source wire 60 electrically connected with a source region 100 that is formed on a substrate, and extending in one direction; a drain wire 70 electrically connected with a drain region 110 that is formed on the substrate, and extending in substantially parallel to the source wire; a gate 120 having a parallel part 122 provided between the source wire 60 and the drain wire 70, and extending in substantially parallel to the source wire 60 and the drain wire 70; a gate wire 80 for applying a voltage to the gate 120; and a gate via 82 electrically connecting between the gate 120 and the gate wire 80. The parallel part 122 has two end parts 126. Voltage application paths from the gate via 82 to the two end parts 126 are formed respectively.

Description

  The present invention relates to a high-frequency semiconductor switch, and more particularly to a high-frequency semiconductor switch used in a wireless communication device.

  High-frequency semiconductor switches are used for the front end of wireless communication devices such as mobile phones and personal computers. The high-frequency semiconductor switch switches a path for transmitting a reception signal received from an antenna and a path for transmitting a transmission signal transmitted from the antenna. For switching, the high-frequency semiconductor switch includes a plurality of FETs (Field Effect Transistors).

  The FET is connected to a transmission terminal to which a transmission signal is input or a reception terminal from which a reception signal is output. When transmitting a signal, a voltage is applied to the gate of the FET connected to the transmission terminal, and when receiving a signal, a voltage is applied to the gate of the FET connected to the reception terminal to transmit the signal. A path is formed.

  A comb-shaped FET is known (for example, see Patent Document 1). When viewed as a plane, a comb-shaped transistor has a source wiring connected to the source region and a drain wiring connected to the drain region formed in a comb shape, and the comb-shaped teeth are alternately arranged from the left and right. ing. The gate is also formed in a comb shape, and is arranged so that the teeth are parallel to the source wiring or the drain wiring.

JP-A-11-103072

  However, in the comb-shaped gate as described above, the teeth of the comb extend the same length or longer than the source region and the drain region. This causes a voltage drop due to the resistance component of the gate extending long, and a good voltage distribution cannot be obtained. As a result, the insertion loss characteristic and the harmonic characteristic are deteriorated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-frequency semiconductor switch in which a good voltage distribution is formed in a gate wiring and insertion loss characteristics and harmonic characteristics are improved.

  A field effect transistor included in a high-frequency semiconductor switch for switching wireless communication includes a source wiring, a drain wiring, a gate, a gate wiring, and a gate via. The source wiring is electrically connected to a source region formed on the substrate and extends in one direction. The drain wiring is electrically connected to a drain region formed on the substrate and extends substantially parallel to the source wiring. The gate has a parallel portion extending substantially parallel to the source wiring and the drain wiring between the source wiring and the drain wiring. The gate wiring applies a voltage to the gate. The gate via electrically connects the gate and the gate wiring. The parallel portion has two ends, and a path for applying a voltage is formed from the gate via to the two ends.

  According to the above configuration, the two ends are formed in the parallel portion, and the path through which the voltage is applied from the gate via is divided. Therefore, the voltage drop due to the length of the path can be reduced by the shorter path, and the gate voltage distribution can be made more uniform.

  Insertion loss characteristics and harmonic characteristics can be improved.

It is a figure which shows an example of schematic circuit structure of a high frequency semiconductor switch. This is the gate of the FET included in the switch. It is a top view which shows the gate, source region, and drain region which are located in the lower part of wiring. FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. It is a top view which shows the wiring of a comparison form. It is the gate of FET contained in the high frequency semiconductor switch of 2nd Embodiment. It is a gate located at the bottom of the wiring. It is a schematic sectional drawing of FET cut along the 11-11 line of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. In addition, the dimensional ratios in the drawings are exaggerated for convenience of explanation, and may be different from the actual ratios. In addition, the expression “to be formed on” in the description includes not only the case of being provided in direct contact but also the case of being provided indirectly through another substance. “Abbreviation” in the specification means including manufacturing error and manufacturing accuracy. For example, “substantially” parallel includes a case where it is not completely parallel due to manufacturing error and manufacturing accuracy.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a schematic circuit configuration of a high-frequency semiconductor switch.

  As shown in FIG. 1, the high-frequency semiconductor switch 10 includes four series switches 20a to 20d. The series switches 20a to 20d are provided between the antenna terminal 30 and the RF terminals 40a to 40d. Each of the series switches 20a to 20d includes at least one field effect transistor (hereinafter referred to as FET). A plurality of FETs included in the same series switch 20a-d can simultaneously apply a voltage to their gates, as shown. Therefore, the conduction between the antenna terminal 30 and the RF terminals 40a-d can be controlled by switching the application of the voltage to the gate for each of the series switches 20a-d. Note that a voltage is also applied to the body of the FET.

  In the example illustrated in FIG. 1, the RF terminals 40a to 40d are RF terminals 40a and 40b, which are transmission terminals (TX), and RF terminals 40c and 40d are reception terminals (RX). The transmission / reception terminal is, for example, a terminal having a different frequency for the frequency division duplex system or a terminal for switching at a predetermined time for the time division duplex system.

  For example, when the series switch 20a is turned on and the other series switches 20c to 20d are turned off, transmission of a frequency of 900 MHz is realized, the series switch 20c is turned on, and the other series switches 20a, b, When d is turned off, reception of a frequency of 900 MHz is realized. The number of series switches 20 and RF terminals 40 can be appropriately increased or decreased depending on the transmission / reception method and required diversity.

  Next, description will be made by paying attention to the structure of one FET among the plurality of FETs 50 included in the series switches 20a to 20d.

  FIG. 2 is a schematic plan view showing the gate, source and drain wirings of the FET included in the switch, and FIG. 3 is a plan view showing the gate, source region and drain region located below the wirings. FIG. 2 shows, for example, the wiring of the FET 50a circled by the dotted line in FIG. FIG. 3 shows the gate, source region, and drain region formed below the wiring of FIG.

  As shown in FIG. 2, the FET 50 a is provided with a source wiring 60, a drain wiring 70, a gate wiring 80 and a body wiring 90.

  The source wiring 60 and the drain wiring 70 are each formed in a comb shape. The source wiring 60 includes a comb-shaped handle portion 62 and a tooth portion 64 extending in a direction (one direction) substantially orthogonal to the handle portion 62. Vias 66 are formed in the tooth portions 64. The source wiring 60 is connected to the source region 100 shown in FIG. 3 through the via 66. The source region 100 is formed in the substrate and is divided on both sides of the gate 120 as shown in FIG. However, since the tooth portion 64 of the source wiring 60 is continuous in the upper part, a voltage is applied to both sides of the source region 100 divided from the source wiring 60.

  The drain wiring 70 is also formed similarly to the source wiring 60. It has a comb-shaped handle portion 72 and a tooth portion 74 extending in a direction substantially perpendicular to the handle portion 72 (one direction). Vias 76 are formed in the tooth portions 74. The drain wiring 70 is connected to the drain region 110 shown in FIG. 3 through the via 76. The drain region 110 is formed in the substrate and is divided on both sides of the gate 120 as shown in FIG. However, since the teeth 74 of the drain wiring 70 are continuous in the upper part, a voltage is supplied to both sides of the drain region 110 divided from the drain wiring 70.

  The gate wiring 80 is between the handle portion 62 of the source wiring 60 and the handle portion 72 of the drain wiring 70, and is substantially orthogonal to the tooth portions 64 and 74 and substantially parallel to the handle portions 62 and 72 when viewed from the plane. Preferably, the gate wiring 80 is located substantially at the center of the handle portions 62 and 72. A via (gate via) 82 is formed in the gate wiring 80. Via the via 82, the gate wiring 80 is connected to the gate 120 shown in FIG.

  As shown in FIG. 3, the gate 120 includes a parallel portion 122 that extends substantially parallel to the tooth portion 64 of the source wiring 60 and the tooth portion 74 of the drain wiring 70, and is formed in the same layer as the parallel portion 122 and orthogonal to the parallel portion 122. And one orthogonal portion 124 extending in the direction. The parallel portion 122 has two ends 126 and extends from one orthogonal portion 124 to both sides. The via 82 is provided on the orthogonal portion 124 at a position off the intersection of the parallel portion 122 and the orthogonal portion 124.

  Two body wirings 90 are formed on both sides of the gate 120, the source region 100, and the drain region 110, approximately parallel to the orthogonal portion 124 of the gate 120. A via (body via) 92 is formed in the body wiring 90. The body wiring 90 is electrically connected to the body region of the SOI substrate, which will be described later, via the via 92. The body region is formed under the gate 120. The vias 92 are provided on both sides of the parallel part 122 of the gate 120, for example, as shown in FIG. A voltage is applied to the body region via the via 92.

  Next, the three-dimensional positional relationship between the above-described wirings, regions, and vias will be described with reference to cross-sectional views.

  4 is a cross-sectional view taken along line 4-4 in FIG. 2, FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. 2, and FIG. 6 is cut along line 6-6 in FIG. FIG. 7 is a sectional view taken along line 7-7 in FIG. 4-7, illustration of some interlayer insulating films is omitted.

  As shown in FIGS. 4 to 7, the FET 50 is formed on an SOI substrate. An insulating film 140 of silicon oxide is formed on a silicon substrate 130 of a certain conductivity type (for example, P type). In the semiconductor layer 150 on the insulating film 140, a source region 100 and a drain region 110 having a conductivity type (for example, N type) different from that of the substrate are formed. A gate 120 is formed on the body region 150 between the source region 100 and the drain region 110 via an oxide film 160.

  The gate 120 is formed from a polysilicon layer. As shown in FIGS. 4 and 7, the gate wiring 80 is formed on the gate 120 and is electrically connected to the gate 120 through the via 82. The via 82 can be formed by pouring a metal material into a via hole formed by opening an interlayer insulating film.

  A source line 60 and a drain line 70 are formed on the gate 120 so as not to contact the gate 120. As shown in FIG. 5, the source wiring 60 and the drain wiring 70 are electrically connected to the source region 100 and the drain region 110 through vias 66 and 76, respectively. The vias 66 and 76 can be formed by pouring a metal material into a via hole formed by opening an interlayer insulating film.

  As shown in FIG. 6, the body wiring 90 is formed above both sides of the gate 120. The via 92 connected to the body wiring 90 is connected to the body region 150. The body wiring 90 is formed at the same height as the gate wiring 80 as shown in FIG.

  As shown in FIG. 7, the source line 60 is formed so as to straddle the gate line 80 and the gate 120. The source wiring 60 applies a voltage to the source region 100 divided by the body region 150 below the gate 120 through the via 66.

  Next, description will be made in comparison with a comparative embodiment for comparison with the present invention.

  FIG. 8 is a plan view showing the wiring of the comparative form.

  As shown in FIG. 8, in the comparative embodiment, the source wiring 160, the drain wiring 170, and the gate wiring 180 are each formed in a comb shape. Therefore, a voltage drop corresponding to the distance Lp from the gate via 182 provided in the gate wiring 180 to the tip 222 of the gate 220 occurs, and the voltage distribution is deteriorated. As a result, the insertion loss characteristic and the harmonic characteristic are deteriorated.

  On the other hand, as shown in FIG. 2, in this embodiment, the gate wiring 80 is formed between the source wiring 60 and the drain wiring 70, and the via 82 is also provided along the gate wiring 80. There are two ends 126 in the parallel portion 122 of the gate 120. Therefore, the distance L from the via 82 to the two tips 126 of the gate 120 is shorter than the distance Lp in FIG. In other words, since the two leading ends 126 are formed in the parallel portion 122 of the gate 120, the path from the via 82 to the leading end 126 is divided into two instead of one, and each distance is also shortened. As the distance is shortened, the voltage drop is reduced and the voltage distribution at the gate 120 becomes uniform. Since the voltage applied to the gate 120 is uniform, the inversion layer formed in the body region 150 is also uniform, and the insertion loss characteristic is improved. In addition, when the voltage distribution at the gate 120 becomes uniform, the distortion of the signal is eliminated, so that the harmonic characteristics are also improved.

  In particular, when the gate line 80 is arranged at the center of the source line 60 and the drain line 70, it becomes a right and left object, and the distance from the via 82 to the tip 120 of the gate 120 is about half of the distance Lp. Therefore, the voltage distribution in the gate 120 can be made more uniform, and the insertion loss characteristic and the harmonic characteristic can be improved.

  In addition, in the comparative embodiment shown in FIG. 8, one body wiring 190 is formed on one side. A body region to which a voltage is applied from body wiring 190 is formed under gate 220. Therefore, the distance from the via 192 to the tip of the body region is approximately the same distance Lp as the gate 120. The voltage applied to the body region also causes a voltage drop by the length of the distance Lp. In the comparative form, the voltage distribution applied to the body region is also deteriorated. As a result, the insertion loss characteristic and the harmonic characteristic are deteriorated.

  On the other hand, as shown in FIG. 2, in this embodiment, the body wiring 90 is formed on the left and right. Since a voltage is applied to the body region 150 below the gate 120 from the vias 92 on both sides (left and right in the figure), the distance at which the voltage drop occurs is about half of the distance Lp. As a result, the insertion loss characteristic and the harmonic characteristic can be improved as compared with the comparative example.

(Second Embodiment)
FIG. 9 is a schematic plan view showing the gate, source and drain wirings of the FET included in the high-frequency semiconductor switch of the second embodiment. FIG. 10 is a plan view showing the gate, source and drain regions located below the wirings. 11 is a schematic cross-sectional view of the FET taken along the line 11-11 in FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the FET 50 included in the high-frequency semiconductor switch of the second embodiment, the source wiring 260 and the drain wiring 270 are formed in a comb shape as in the first embodiment. The source wiring 260 and the drain wiring 270 have handle portions 262 and 272, tooth portions 264 and 274, and vias 266 and 276, respectively. As shown in FIG. 9, two gate wirings 280 are formed on both sides in parallel with the handle portions 262 and 272 of the source wiring 260 and the drain wiring 270.

  Two gate wirings 280 extend in a direction orthogonal to the extending direction (one direction) of the tooth portions 264 and 274 of the source wiring 260 and the drain wiring 270, and are formed so as to sandwich the gate 320 (parallel portion). The gate 320 is divided into two in the one direction, and extends so as to approach each other from each gate wiring 280. The gate 320 has two end portions 322 located on both sides of the body wiring 290.

  The gate wiring 280 has a gate via 282 and is electrically connected to the gate 320 through the via 282. The via 282 is provided at the intersection of the gate wiring 280 and the gate 320.

  The body wiring 290 is formed between the divided gates 320 substantially in parallel with the gate wiring 280 when viewed from above. The body wiring 290 extends in the center so as to pass between the divided source region 300 and drain region 310 as viewed from above. The body wiring 290 has a body via 292 and is connected to a body region 350 formed on the SOI substrate as shown in FIG. A voltage is applied from the body wiring 290 to the body region via the body via 292.

  In the FET 50 according to the second embodiment configured as described above, the gate 320 is divided into two in one direction, and each extends toward the center. Since the gate 320 is divided, the distance from the via 282 to the tip 322 of the gate 320 is about half that of the embodiment shown in FIG. As the distance to which the voltage is applied is shortened, the voltage drop is reduced and the voltage distribution at the gate 320 is uniform.

  In addition, since the body wiring 290 is formed at the center, the distance from the via 292 to the end of the body region 350 is about half that of the embodiment shown in FIG. Accordingly, the voltage drop is reduced as the distance to which the voltage is applied becomes shorter, and the voltage distribution in the body region 350 is uniform. As described above, also in the second embodiment, the voltage distribution of the FET 50 is uniform as compared with the comparative example of FIG. 8, and as a result, the insertion loss characteristic and the harmonic characteristic can be improved.

  In this specification, as viewed from the plane, as the first embodiment, the gate wiring is arranged in the center and the body wiring is arranged on both sides, and as the second embodiment, the body wiring is arranged in the center. In the above description, the gate wiring is arranged on both sides. In the present invention, the arrangement relationship only needs to be satisfied when viewed from the plane. The design of the positional relationship between the gate wiring, source wiring, drain wiring, and body wiring can be changed. For example, in the first embodiment, the body wiring 90 can be formed at a position higher than the source wiring 60 and the drain wiring 70.

  Although the case where the source wirings 60 and 260 and the drain wirings 70 and 270 are comb-shaped has been described, the present invention is not limited to this. Even if it is not a comb shape, it should just extend in the direction of at least one position. For example, one tooth portion 64 may be a source wiring 60 extending in one direction, and one tooth portion 74 may be a drain wiring 70 extending substantially parallel to the source wiring 60.

10 high frequency semiconductor switch,
20a-d series switch,
30 Antenna terminal,
40a-d terminals,
50 FET,
60, 260 source wiring,
62, 262 handle part,
64, 264 teeth,
66, 76, 82, 92, 282, 292, via,
70, 270 drain wiring,
72 handle part,
74 teeth,
80, 280 gate wiring,
90, 290 body wiring,
100, 300 source region,
110, 310 drain region,
120, 220, 320 gates,
122 parallel parts,
124 orthogonal part,
126, 322 end,
130 silicon substrate,
140 insulating film,
150, 350 body area,
160 Oxide film.

Claims (6)

A field effect transistor included in a high-frequency semiconductor switch for switching wireless communication,
A source wiring electrically connected to a source region formed in the substrate and extending in one direction;
A drain wiring electrically connected to a drain region formed on the substrate and extending substantially parallel to the source wiring;
A gate having a parallel portion extending substantially parallel to the source wiring and the drain wiring between the source wiring and the drain wiring;
A gate wiring for applying a voltage to the gate;
A gate via for electrically connecting the gate and the gate wiring;
Have
The parallel portion has two ends, and a field effect transistor in which a voltage application path is formed from the gate via to the two ends, respectively. The gate is formed in the same layer as the parallel part and also has an orthogonal part extending perpendicular to the parallel part,
The field effect transistor according to claim 1, wherein the via is provided on the orthogonal portion. One orthogonal portion is formed,
3. The field effect transistor according to claim 1, wherein the parallel portion extends from the orthogonal portion to both sides. A body region formed in the substrate below the gate;
Body wiring for applying a voltage to the body region;
A body via for electrically connecting the body region and the body wiring;
4. The field effect transistor according to claim 3, wherein the body wiring is formed on both sides of the gate substantially parallel to the orthogonal portion. The gate wiring extends in a direction perpendicular to one direction, and is formed so as to sandwich the parallel part,
2. The field effect transistor according to claim 1, wherein the parallel portion is divided into two and extends so as to approach each other from each gate wiring. A body region formed in the substrate below the gate;
Body wiring for applying a voltage to the body region;
A body via for electrically connecting the body region and the body wiring;
6. The field effect transistor according to claim 5, wherein the body wiring is formed between the divided parallel portions substantially parallel to the gate wiring.

Images