JP2012133853A - Sample-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-hold circuit by which a S/N ratio is improved.SOLUTION: The sample-hold circuit is provided with: an input terminal for inputting an input voltage; a plurality of capacitances for holding a sampling voltage based on the input voltage; a plurality of input switches respectively connected between the input terminal and the plurality of capacitances; and an output terminal for outputting hold voltages of the plurality of capacitances. The circuit is arranged to have a constitution so that the input voltage is sampled by the plurality of capacitances at different timings according to the plurality of input switches and the hold voltage of the plurality of capacitances is equalized and output to the output terminal.

Description

  The present invention relates to a sample and hold circuit that samples an input voltage and holds and outputs a voltage based on the sampled voltage.

In recent years, sample hold circuits are used in portable communication devices and the like to hold data signals. As such a sample and hold circuit, a circuit that samples and holds a charge according to an input voltage by charging and discharging with a switch is well known.
(For example, refer to Patent Document 1).

  FIG. 3 is a block diagram showing a conventional sample and hold circuit. The conventional sample and hold circuit includes a switch 301 and a capacitor 302. When the sample and hold circuit and the switch 301 are in the ON state, the charge corresponding to the input voltage Vs is sampled in the capacitor 302. When the switch 301 is off, the sampling voltage Vs is held and output.

Japanese Patent Laid-Open No. 11-224496

  However, in many cases, the input voltage is superimposed not only with the originally required signal component but also with an unnecessary noise component such as thermal noise. For this reason, the conventional sample and hold circuit has a problem that the S / N ratio is deteriorated.

  The present invention has been devised to solve the above-described problems, and realizes a sample-and-hold circuit having an improved S / N ratio.

  The sample and hold circuit of the present invention is a sample and hold circuit that samples an input voltage and outputs a voltage based on the sampled voltage. The sample and hold circuit includes a plurality of capacitors and a plurality of switches. The sample-and-hold circuit is characterized in that the switches are controlled to be turned on and off at different timings from each other.

  According to the sample-and-hold circuit of the present invention, it is possible to provide a sample-and-hold circuit that can reduce the influence of an unnecessary noise component superimposed on the input voltage and can perform a hold output and improve the S / N ratio.

It is a circuit diagram which shows the sample hold circuit of this embodiment. It is a figure which shows an example of the sampling of the input voltage of the sample hold circuit of this embodiment. It is a circuit diagram which shows the conventional sample hold circuit.

FIG. 1 is a circuit diagram showing a sample and hold circuit of the present embodiment.
The sample hold circuit of this embodiment includes a switch 101, a switch 102, a switch 103, a capacitor 104, and a capacitor 105. The input terminal IN is connected to one terminal of the capacitor 104 through the switch 101 and is connected to one terminal of the capacitor 105 through the switch 102. The output terminal OUT is connected to one terminal of the capacitor 104 and is connected to one terminal of the capacitor 105 through the switch 103. The other terminals of the capacitors 104 and 105 are connected to the ground terminal. The switches 101 to 103 are composed of, for example, MOS switches.

  The operation of the sample and hold circuit of this embodiment will be described below. Here, the voltage Vs is a signal component, and the voltages V1 and V2 are noise components.

  First, at the first timing, the switch 101 is turned on, and the switch 102 and the switch 103 are turned off. The input voltage Vin at the input terminal IN is held in the capacitor 104 as a value of voltage Vs + V1. Next, the switch 102 is turned on and the switches 101 and 103 are turned off at the second timing. The input voltage Vin of the input terminal IN is held in the capacitor 105 as a value of voltage Vs + V2. That is, the switch 101 and the switch 102 sample the input voltage Vin into the capacitor 104 and the capacitor 105 at different timings.

  Next, the switch 103 is turned on, and the switch 102 and the switch 103 are turned off. That is, since the capacitor 104 and the capacitor 105 are short-circuited, that is, connected in parallel, the voltage Vout obtained by averaging the voltage of the capacitor 104 and the voltage of the capacitor 105 is output to the output terminal OUT.

  Here, when the capacitance value of the capacitor 104 is C104 and the capacitance value of the capacitor 105 is C105, the voltage Vout is obtained by the following equation (1).

Vout =
{C101 × (Vs + V1) + C102 × (Vs + V2)} / (C101 + C102) =
Vs + {(C101) × V1 + (C102) × V2} / (C101 + C102) (1)
Assuming that C101 = C102, Equation (1) can be expressed as follows.

Vout = Vs + (V1 + V2} / 2 (2)
Since the voltages V1 and V2 are noise components sampled at different timings, the second term obtained by dividing the voltages V1 and V2 by the number of times of sampling 2 is a time-averaged noise component.

  FIG. 2 is a diagram illustrating an example of sampling of the input voltage of the sample and hold circuit of the present embodiment. In the input voltage Vin, an unnecessary noise component voltage Vn is superimposed on a signal component voltage Vs. The voltage Vn is caused by various disordered noise components such as thermal noise and external noise. Therefore, if the time average is sufficiently performed, the value can approach zero.

  In the above description of the operation of the sample and hold circuit of this embodiment, the first timing is t1 and the second timing is t2. From the figure, the input voltage Vin is the voltage Vs + V1 at the first timing t1, and the voltage Vs + V2 at the second timing t2. Then, these held voltages are output to the output terminal OUT at the third timing (not shown) at the voltage Vout represented by the expression (2). Here, since the value of the second term of the expression (2), which is a noise component, becomes zero when sufficiently time-averaged, the voltage Vout becomes a value close to the voltage Vs, which is a signal component.

  As described above, the sample-and-hold circuit of the present embodiment includes the two capacitors 104 and 105, samples and holds the input voltage Vin at different timings, and outputs the averaged output voltage so as to be superimposed on the input voltage Vin. It is possible to reduce the influence of unnecessary noise component Vn. That is, it is possible to provide a sample hold circuit with an improved S / N ratio.

  In the sample and hold circuit according to the present embodiment, the two capacitors 103 and 104 and the switches 102 and 103 corresponding to the capacitors 103 and 104 have been described. However, three or more capacitors and switches may be provided. In addition, the held voltage is time-averaged by short-circuiting the capacitor 104 and the capacitor 105 with the switch 103, but the present invention is not limited to this mode. For example, the switch 103 may not be provided, and the voltages of the capacitor 103 and the capacitor 104 may be input to a microcomputer, and averaging calculation may be performed by the microcomputer. Moreover, although each switch was demonstrated as a MOS switch, it is not limited to this form.

  Further, means for generating a plurality of sample and hold timings is not particularly limited. For example, a counter circuit that divides the input clock signal may be generated, or, for example, a plurality of delay circuits may be provided, and a plurality of delay circuits may be generated from the input pulse signal.

101, 102, 103, 301 Switch 104, 105, 302 Capacity

Claims (2)

An input terminal for inputting an input voltage;
A plurality of capacitors for holding a sampling voltage based on the input voltage;
A plurality of input switches respectively connected between the input terminal and the plurality of capacitors;
An output terminal for outputting a hold voltage of the plurality of capacitors, a sample hold circuit comprising:
The plurality of capacitors sample input voltages at different timings by the plurality of input switches,
A sample-and-hold circuit that averages hold voltages of the plurality of capacitors and outputs the result to the output terminal. And a plurality of output switches respectively connected between the output terminal and the plurality of capacitors.
2. The sample and hold circuit according to claim 1, wherein the plurality of capacitors are connected in parallel by the plurality of output switches and the hold voltage is averaged.

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