JP2012133638A - Electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus comprising a DRAM which performs a power saving mode control appropriate for the system.SOLUTION: An electronic apparatus comprises: a DRAM having a self-refresh mode and a power-down mode; and a memory controller for controlling the DRAM. The memory controller comprises: a first register for setting a start condition of the self-refresh mode; a second register for setting a start condition of the power-down mode; and control means for controlling execution of the self-refresh mode and the power-down mode according to the settings of the first register and the second register.

Description

  The present invention relates to an electronic device equipped with a DRAM.

  As an operation mode, a DRAM (Dynamic Random Access Memory) having a normal mode and a power saving mode is known. Further, it is known that the power saving mode includes a self-refresh mode and a power-down mode (for example, Patent Document 1).

JP 2003-59266 A

  The self fresh mode and the power down mode have, for example, the following advantages and disadvantages.

  In the self-refresh mode, when an instruction to start self-refresh is given, the DRAM autonomously repeats the refresh operation by a built-in or connected timer. During the execution of the self-refresh mode, it is only necessary to supply power to the DRAM, so that the clock supply to the DRAM can be stopped. Therefore, when using the self-refresh mode, an electronic device equipped with a DRAM supplies a clock and power to at least a part of a circuit other than the DRAM (for example, a CPU, an application specific integrated circuit (ASIC), a memory controller, etc.). It can be stopped and power consumption can be reduced.

  In the power down mode, the clock enable signal of the DRAM is set to low (inactive), but the clock of the electronic device is not stopped. Further, when the refresh operation is performed while using the power-down mode, it is necessary to return the DRAM from the power-down mode every time refresh is performed. Therefore, in the power down mode, the power consumption of the electronic device cannot be reduced as much as the self refresh mode.

  On the other hand, the return from the power-down mode to the normal mode has a shorter wait time than the return from the self-refresh mode to the normal mode. For this reason, the power-down mode is less likely to lower the DRAM access efficiency.

  As described above, the self-fresh mode and the power-down mode have the advantages and disadvantages described above, for example.

  Accordingly, an object of the present invention is to perform appropriate power saving mode control suitable for the system in an electronic device including a DRAM.

  One embodiment of the present invention for solving the above-described problem is an electronic device including a DRAM having a self-fresh mode and a power-down mode, and a memory controller that controls the DRAM. A first register for setting a start condition for a refresh mode, a second register for setting a start condition for the power down mode, and the self refresh mode and the power according to the settings of the first register and the second register Control means for controlling execution of the down mode.

  Here, the first register includes a first start register for instructing the start of the self-refresh mode, and the control means executes the self-refresh mode when the first start register is set. It may be characterized by starting.

  Further, the second register includes a second timer register for starting a second timer for determining the start of the power down mode, and the control means, when the second timer register is set, The second timer may be counted, and when the second timer expires a predetermined value, execution of the power down mode may be started.

  In addition, the first register includes a first timer register for starting a first timer for determining the start of the self-refresh mode, and the control means, when the first timer register is set, The first timer may be counted, and execution of the self-refresh mode may be started when the first timer expires a predetermined value.

  The second register includes a second start register for instructing the start of the power down mode, and the control unit starts executing the power down mode when the second start register is set. It may be characterized by.

  In addition, the first register includes a first end register that instructs the end of the self-refresh mode, and the second register includes a second end register that instructs the end of the power-down mode, When the first end register is set during the execution of the self-refresh mode, the control means ends the execution of the self-refresh mode, and the second end register is set during the execution of the power-down mode. In such a case, the execution of the power down mode may be terminated.

  In addition, when the control unit receives an access request to the DRAM during execution of the self-refresh mode or the power-down mode, the control unit ends execution of the self-refresh mode or the power-down mode. May be.

  In addition, the electronic device includes a CPU, and the CPU is configured so that one of the self-refresh mode and the power-down mode selected in advance according to performance required for the electronic device is in the electronic device. The first register or the second register may be set so as to be executed according to a start condition determined in advance according to required performance.

  Further, the CPU selects the self-refresh mode when the electronic device has high performance, and instructs the start of the self-refresh mode by the first start register, so that the electronic device has intermediate performance. The power-down mode is selected, and the second timer register is set to start the second timer, and when the electronic device has low performance, the self-refresh mode is selected, In addition, the first timer register may be set to start the first timer.

  Further, the control means sets the timing for setting the first start register or the timing when the first timer expires the predetermined value, and sets the timing for the second start register or the second timer expires the predetermined value. If the detected timing is detected within a predetermined period, execution of the self-refresh mode may be started in preference to the power-down mode.

  The electronic apparatus has a normal mode and a power saving mode as an operation mode of the CPU and the electronic apparatus, and the CPU is configured when the electronic apparatus shifts from the normal mode to the power saving mode. The first start register or the second start register may be set.

  The electronic device includes a first power saving mode and a second power saving mode that consumes less power than the first power saving mode as the power saving mode, and the CPU includes the first power saving mode. When shifting to the power mode, the second start register is set, and when shifting to the second power saving mode, the first start register is set.

  The electronic apparatus may be a printing apparatus.

1 is a block diagram illustrating a schematic configuration of a printing apparatus according to an example of an embodiment of the present invention. It is a block diagram which shows schematic structure of the memory control ASIC which concerns on an example of one Embodiment of this invention. It is a figure explaining the combination of the start condition and end condition of self-refresh and power-down which concern on an example of one Embodiment of this invention. It is a state transition diagram of a memory controller according to an example of an embodiment of the present invention. It is a figure explaining the count condition of the timer which concerns on an example of one Embodiment of this invention. It is a flowchart which shows the start and completion | finish (combination 1) of the self-refresh mode based on an example of one Embodiment of this invention. It is a flowchart which shows the start and completion | finish (combination 2) of the self-refresh mode based on an example of one Embodiment of this invention. It is a flowchart which shows the start and completion | finish (combination 3) of the self-refresh mode based on an example of one Embodiment of this invention. It is a flowchart which shows the start and completion | finish (combination 4) of the self-refresh mode based on an example of one Embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a printing apparatus is mentioned as an example of an electronic device.

  FIG. 1 is a block diagram illustrating a schematic configuration of a printing apparatus according to an example of an embodiment of the present invention.

  The printing apparatus 100 is an apparatus such as a printer, a copier, or a multifunction machine. The printing apparatus 100 is connected to the information processing apparatus 200.

  The information processing apparatus 200 includes a general CPU (not shown), a RAM, a ROM, an auxiliary storage device such as a hard disk, a display, an input device such as a keyboard and a mouse, a communication interface, and the like. Realized by computer. In the information processing apparatus 200, an application program and a driver program (for example, a printer driver program) are executed.

  The printing apparatus 100 includes a controller 110 as an electronic device control apparatus that controls various processes in the printing apparatus 100, an engine unit 160 that executes printing on a printing medium and reading of an original, and an operation that is an input / output interface with a user. A panel 170.

  The controller 110 includes a CPU 120, a memory control ASIC 130, an SDRAM (Synchronous DRAM) 140, and an I / O (Input / Output) control ASIC 150. The controller 110 controls various mechanisms such as the engine unit 160 and the operation panel 170, and realizes a printing function including various image processing, a facsimile function, a scanner function, a copy function, and the like. Of course, the controller 110 is not limited to this configuration. For example, the CPU 120 may be built in the memory control ASIC 130.

  The CPU 120 accesses the SDRAM 140 via the memory control ASIC 130, and executes various processes by reading and writing various data. The CPU 120 issues an access request for accessing the SDRAM 140 to the memory control ASIC 130.

  Although details will be described later, the CPU 120 issues a setting request regarding the power saving mode (self-refresh mode, power-down mode) of the SDRAM 140 to the memory control ASIC 130.

  The memory control ASIC 130 controls access to the SDRAM 140 from the CPU 120, I / O control ASIC 150, and engine unit 160. The memory control ASIC 130 may control DMA (Direct Memory Access) to the SDRAM 140 without using the CPU 120.

  Further, the memory control ASIC 130 issues a refresh command for refreshing the SDRAM 140.

  Although details will be described later, the memory control ASIC 130 has various registers for controlling the power saving mode of the SDRAM 140. The memory control ASIC 130 receives a setting request regarding the power saving mode of the SDRAM 140 from the CPU 120 and sets the various registers. The memory control ASIC 130 controls the power saving mode of the SDRAM 140 according to the settings of various registers.

  The SDRAM 140 is a memory that is controlled by the memory control ASIC 130. The SDRAM 140 has a plurality of cells (storage areas), and when a refresh command is issued from the memory control ASIC 130, the cell (or column) to be refreshed is refreshed.

  The SDRAM 140 can operate in a self-refresh mode and a power-down mode as power saving modes. The SDRAM 140 starts and ends the self-refresh mode and the power-down mode under the control of the memory control ASIC 130.

  The I / O control ASIC 150 controls transmission / reception of data to / from external devices (such as the operation panel 170 and the information processing apparatus 200). Although not shown, the I / O control ASIC 150 is connected to a communication interface conforming to, for example, Ethernet (registered trademark) or USB, and communicates with the information processing apparatus 200 via the communication interface.

  The engine unit 160 includes a paper supply / discharge mechanism, a printing mechanism, a scanning mechanism, and the like for realizing a printing function, a facsimile function, a scanner function, a copying function, and the like, and includes, for example, a printing engine, a scanner engine, and the like.

  The operation panel 170 is a unit for receiving user operations. The operation panel 170 includes, for example, a display such as an LCD and a touch panel provided on the display surface side of the display. The operation panel 170 may have various hard switches such as button keys.

  The outline of the hardware configuration of the printing apparatus 100 has been described above. Of course, this configuration is not limited to the above-described configuration because the main configuration has been described in describing the features of the present invention. In addition, other configurations included in a general printing apparatus are not excluded.

  Next, the schematic configuration of the memory control ASIC 130 and the characteristic configuration of the memory controller 133 will be described.

  FIG. 2 is a block diagram showing a schematic configuration of the memory control ASIC.

  The memory control ASIC 130 includes an interface unit 131, an arbitration circuit 132, and a memory controller 133. In the figure, a plurality of masters 1 to M that access the SDRAM 140 are illustrated. The master is a predetermined unit for accessing the SDRAM 140, and is not limited to unit units such as the CPU 120, the I / O control ASIC 150, and the engine unit 160, but may be a finer processing unit.

  The interface unit 131 receives an access request from a master such as the CPU 120, I / O control ASIC 150, engine unit 160, and notifies the arbitration circuit 132.

  The arbitration circuit 132 receives the notified access request and notifies the memory controller 133 of it. When receiving a plurality of access requests at the same timing, for example, the arbitration circuit 132 performs control to select one access request and notify the memory controller 133 of the selected access request.

  When the memory controller 133 accepts an access request from the arbitration circuit 132, the memory controller 133 issues a predetermined command to the SDRAM 140 to perform access control based on the access request.

  Further, the memory controller 133 issues a refresh command to the SDRAM 140 at a predetermined timing to refresh the SDRAM 140.

  The memory controller 133 according to the present embodiment receives a setting request regarding the power saving mode of the SDRAM 140 from the CPU 120 and controls the power saving mode of the SDRAM 140.

  In order to control the power saving mode of the SDRAM 140, the memory controller 133 includes a self-refresh start register 1331, a self-refresh timer ON register 1332, a self-refresh timer value register 1333, a self-refresh end register 1334, and a power-down start register. 1335, a power down timer ON register 1336, a power down timer value register 1337, and a power down end register 1338.

  The self-refresh start register 1331 holds a value indicating an instruction to start the self-refresh mode (for example, start: 1, reset state: 0). The self-refresh timer ON register 1332 holds values indicating ON or OFF of the self-refresh timer for determining the start of the self-refresh mode (for example, ON: 1, OFF: 0). The self-refresh timer value register 1333 holds the self-refresh timer value. The self-refresh end register 1334 holds a value indicating an instruction to end the self-refresh mode (for example, end: 1, reset state: 0).

  The power down start register 1335 holds a value (for example, start: 1, reset state: 0) indicating an instruction to start the power down mode. The power down timer ON register 1336 holds values indicating ON or OFF of the power down timer for determining the start of the power down mode (for example, ON: 1, OFF: 0). The power down timer value register 1337 holds the power down timer value. The power-down end register 1338 holds a value indicating an instruction to end the power-down mode (for example, end: 1, reset state: 0).

  The memory controller 133 incorporates a timer mechanism (not shown) or is connected to the timer mechanism.

  When “start” is set in the self-refresh start register 1331, the memory controller 133 starts executing the self-refresh mode. When “end” is set in the self-refresh end register 1334, the execution of the self-refresh mode is ended.

  In addition, when “ON” is set in the self-refresh timer ON register 1332, the memory controller 133 periodically counts the self-refresh timer using the timer mechanism, and sets the value to the self-refresh timer value register 1333. Hold on. Further, it is periodically determined whether or not the self-refresh timer exceeds a predetermined value, and when it exceeds, the execution of the self-refresh mode is started. The predetermined value can also be held in a register.

  Further, when “start” is set in the power down start register 1335, the memory controller 133 starts executing the power down mode. When “end” is set in the power down end register 1338, execution of the power down mode is ended.

  In addition, when “ON” is set in the power-down timer ON register 1336, the memory controller 133 periodically counts the power-down timer using the timer mechanism, and the value is stored in the power-down timer value register. 1337. In addition, it periodically determines whether or not the power-down timer exceeds a predetermined value, and when it exceeds, the execution of the power-down mode is started. The predetermined value can also be held in a register.

  Note that the control method (such as the control procedure of various signals) by which the memory controller 133 starts and ends the self-refresh and power-down of the SDRAM 140 is the same as the conventional method, and thus the description thereof is omitted.

  FIG. 3 is a diagram for explaining a combination of start and end conditions for self-refresh and power-down. Combinations 1 to 4 (Nos. 1 to 4 in the figure) relate to the self-refresh mode, and combinations 5 to 8 (Nos. 5 to 8 in the figure) relate to the power-down mode.

<Self-refresh mode>
<Combination 1>
Start condition: When “start” is set in the self-refresh start register 1331 End condition: When “end” is set in the self-refresh end register 1334 <Combination 2>
Start condition: When “start” is set in the self-refresh start register 1331 End condition: When there is an access request to the SDRAM 140 <Combination 3>
Start condition: When the self-refresh timer exceeds a predetermined value End condition: When “End” is set in the self-refresh end register 1334 <Combination 4>
Start condition: When the self-refresh timer exceeds a predetermined value End condition: When there is an access request to the SDRAM 140

<Power-down mode>
<Combination 5>
Start condition: When “Start” is set in the power-down start register 1335 End condition: When “End” is set in the power-down end register 1338 <Combination 6>
Start condition: When “Start” is set in the power down start register 1335 End condition: When there is an access request to the SDRAM 140 <Combination 7>
Start condition: When the power down timer exceeds a predetermined value End condition: When “End” is set in the power down end register 1338 <Combination 8>
Start condition: When the power-down timer exceeds a predetermined value End condition: When there is an access request to the SDRAM 140

  FIG. 4 is a state transition diagram of the memory controller. Note that (1) to (4) in the figure indicate the priority of processing (the one with the larger value) when a plurality of requests are received at the same timing (within a predetermined time) in each state (S1 to S4). Indicates a higher priority).

  For example, the memory controller 133 is reset after the power of the printing apparatus 100 is turned on, and shifts to an idle state (S1). When there is no request in the idle state (S1) ((4) no request), the memory controller 133 continues the idle state (S1).

  When an access request to the SDRAM 140 is received in the idle state (S1) ((1) there is a RAM access request), the memory controller 133 transitions to a RAM access state (S2).

  In the idle state (S1), when “start” is set in the self-refresh start register 1331 ((2) self-refresh requested (register setting)), or the self-refresh timer exceeds a predetermined value ((2) When there is a self-refresh request (timer expiration), the memory controller 133 transitions to a self-refresh execution state (S3).

  In the idle state (S1), when “start” is set in the power-down start register 1335 ((3) power-down requested (register setting)), or when the power-down timer exceeds a predetermined value ((3) When there is a power-down request (timer expiration), the memory controller 133 transitions to a power-down execution state (S4).

  In the RAM access state (S2), the self-refresh execution state (S3), and the power-down execution state (S4), when there is no request ((2) no request), the memory controller 133 Continue.

  When the access to the SDRAM 140 is completed in the RAM accessing state (S2) ((1) RAM access is completed), the memory controller 133 transitions to the idle state (S1).

  In the self-refresh execution state (S3), when “end” is set in the self-refresh end register 1334 ((1) register setting) or when there is an access request to the SDRAM 140 ((1) there is a RAM access request) ), The memory controller 133 transits to the idle state (S1).

  In the power down execution state (S4), when “end” is set in the power down end register 1338 ((1) register setting), when there is an access request to the SDRAM 140 ((1) there is a RAM access request) Or, when there is a self-refresh request (register setting or timer expiration) ((1) self-refresh request), the memory controller 133 transitions to the idle state (S1).

  FIG. 5 is a diagram illustrating timer count conditions. Each state of the memory controller 133 will be described. When both the self-refresh timer and the power-down timer are OFF, they are in a reset state.

<Idle state>
Self-refresh timer ON: Count Power-down timer ON: Count <RAM accessing state>
Self-refresh timer ON: Reset Power-down timer ON: Reset <Self-refresh running state>
Self-refresh timer ON: Reset Power-down timer ON: Reset <Power-down execution state>
Self-refresh timer ON: Count Power-down timer ON: Reset

  In the present embodiment, as described with reference to FIG. 4, when the self-refresh request and the power-down request are received at the same timing in the idle state, the memory controller 133 preferentially executes the self-refresh mode. Further, when a self-refresh request is accepted in the power-down execution state, the state returns to the idle state and shifts to the self-refresh execution state. Therefore, as shown in FIG. 5, the self-refresh timer is counted in the power-down execution state.

  Setting of values in the various registers (excluding self-refresh timer value register 1333 and power-down timer value register 1337), setting of self-refresh timer interval (predetermined value) and power-down timer interval (predetermined value) Is performed by the CPU 130. That is, it is defined by a software program. This software program is stored in, for example, a ROM (not shown) provided in the controller 110, and is expanded in the SDRAM 140 and executed by the CPU 120.

  For example, an electronic device that requires performance such as high speed and high quality may be programmed to use the power down mode. In addition, for example, in a device that requires lower power consumption, it may be programmed so that the self-refresh mode is used. More specifically, for example, when the systems are classified as follows, an appropriate mode can be executed as follows according to each system request.

<Low-end machine>
In addition to using the self-refresh timer, the self-refresh timer interval (predetermined value) is set as short as possible so that the execution of the self-refresh mode is started without being managed by the CPU. With such settings, high performance cannot be obtained, but power consumption can be reduced.
<Middle range machine>
The power down timer is used so that execution of the power down mode is started even if the CPU does not manage it. With such settings, it is possible to reduce power consumption while maintaining moderate performance.
<High-end machine>
The self-refresh mode is executed by the management of the CPU using the self-refresh register. With such a setting, when the entire electronic device is in the normal mode, the high performance state is maintained, and when the entire electronic device is in the sleep mode, the power consumption can be kept low.

  Note that the CPU may dynamically switch the power saving mode of the SDRAM during the operation of the electronic device. For example, when the electronic device shifts from the normal mode to the power saving mode A, the SDRAM shifts to the power down mode using the power down register under the control of the CPU, and the electronic device consumes more power than the power saving mode A. In the case of shifting to the power saving mode B having a low value, the SDRAM may be shifted to the self refresh mode using the self refresh register under the control of the CPU.

  Also, which mode, start condition, and end condition to use may be changed through the operation panel 170. Settings may be changed from the information processing apparatus 200.

  The outline of the configuration of the memory control ASIC 130 and the characteristic configuration of the memory controller 133 have been described above. Of course, these structures are not limited to the above-described structures because the main structures have been described in describing the features of the present invention. In addition, other configurations included in a general memory control ASIC and a memory controller are not excluded.

  Next, a characteristic operation of the memory controller 133 will be described. Below, the operation | movement of the combination 1-4 of FIG. 3 (No. 1-4 in a figure) is demonstrated with reference to FIGS. The operations of the combinations 5 to 8 (Nos. 5 to 8 in the figure) basically correspond to those in FIGS. 6 to 9 and “self-refresh” may be read as “power down”. Omitted.

  FIG. 6 is a flowchart showing the start and end (combination 1) of the self-refresh mode. This flow is started, for example, when the printing apparatus 100 is turned on.

  In S10, the memory controller 133 executes initialization processing of the SDRAM 140 in accordance with an instruction from the CPU 120, and sets the self-refresh timer ON register 1332 to “OFF”. Then, the process proceeds to S20.

  In S20, the memory controller 133 starts the normal mode. That is, it waits in an idle state. Then, the process proceeds to S30.

  In S30, the memory controller 133 determines whether there is an access request to the SDRAM 140 from a master such as the CPU 120. If there is no access request (S30: No), the process proceeds to S40. When there is an access request (S30: Yes), access (read, write, etc.) to the SDRAM 140 is executed and the determination is continued.

  In S <b> 40, the memory controller 133 determines whether or not “start” is set in the self-refresh start register 1331. If “start” is set (S40: Yes), the process proceeds to S50. If “start” is not set (S40: No), the process returns to S30.

  In S50, the memory controller 133 determines whether or not there is an access request to the SDRAM 140 at the same time that “start” is set in the self-refresh start register 1331 (within a predetermined time from the register setting). If there is no access request (S50: No), the process proceeds to S60. If there is an access request (S50: Yes), access (read, write, etc.) to the SDRAM 140 is executed, and the process returns to S30.

  In S60, the memory controller 133 starts executing the self-refresh mode of the SDRAM 140. Then, the process proceeds to S70.

  In S <b> 70, the memory controller 133 determines whether “end” is set in the self-refresh end register 1334 or whether there is an access request to the SDRAM 140. If there is a register setting or access request (S70: Yes), the process returns to S20. If there is no register setting or access request (S70: No), the determination is continued.

  FIG. 7 is a flowchart showing the start and end (combination 2) of the self-refresh mode. This flow is started, for example, when the printing apparatus 100 is turned on.

  The processing of S10 to S60 is the same as that in FIG. In S <b> 70 a, the memory controller 133 determines whether there is an access request to the SDRAM 140. If there is an access request (S70a: Yes), the process returns to S20. If there is no access request (S70a: No), the determination is continued.

  FIG. 8 is a flowchart showing the start and end (combination 3) of the self-refresh mode. This flow is started, for example, when the printing apparatus 100 is turned on.

  In S110, the memory controller 133 executes initialization processing of the SDRAM 140 in accordance with an instruction from the CPU 120, and sets the self-refresh timer ON register 1332 to “ON”. Also, the self-refresh timer value register 1333 is reset. Then, the process proceeds to S120.

  In S120, the memory controller 133 starts the normal mode. That is, it waits in an idle state. Then, the process proceeds to S30.

  In S <b> 130, the memory controller 133 determines whether there is an access request to the SDRAM 140 from a master such as the CPU 120. If there is no access request (S130: No), the process proceeds to S140. If there is an access request (S130: Yes), access (read, write, etc.) to the SDRAM 140 is executed, and the process proceeds to S170.

  In S140, the memory controller 133 counts the timer value in the self-refresh timer value register 1333 by a predetermined unit. Then, the process proceeds to S150.

  In S150, the memory controller 133 determines whether or not the self-refresh timer has exceeded a predetermined value. If it exceeds the predetermined value (S150: Yes), the process proceeds to S180. If the predetermined value is not exceeded (S150: No), the process proceeds to S160.

  In S160, the memory controller 133 determines whether there is an access request to the SDRAM 140 from a master such as the CPU 120. If there is no access request (S160: No), the process returns to S140. If there is an access request (S160: Yes), access (read, write, etc.) to the SDRAM 140 is executed, and the process proceeds to S170.

  In S170, the memory controller 133 resets the self-refresh timer value register 1333. Then, the process returns to S130.

  In S180, the memory controller 133 determines whether there is an access request to the SDRAM 140 from a master such as the CPU 120. If there is no access request (S180: No), the process proceeds to S190. If there is an access request (S180: Yes), access (read, write, etc.) to the SDRAM 140 is executed, and the process returns to S170.

  In S190, the memory controller 133 resets the self-refresh timer value register 1333. Then, the process proceeds to S200.

  In S200, the memory controller 133 starts execution of the self-refresh mode of the SDRAM 140. Then, the process proceeds to S210.

  In S <b> 210, the memory controller 133 determines whether “end” is set in the self-refresh end register 1334 or whether there is an access request to the SDRAM 140. If there is a register setting or access request (S210: Yes), the process returns to S120. If there is no register setting or access request (S210: No), the determination is continued.

  FIG. 9 is a flowchart showing the start and end (combination 4) of the self-refresh mode. This flow is started, for example, when the printing apparatus 100 is turned on.

  The processing of S110 to S200 is the same as that in FIG. In S210a, the memory controller 133 determines whether or not there is an access request to the SDRAM 140. If there is an access request (S210a: Yes), the process returns to S120. If there is no access request (S210a: No), the determination is continued.

  Each processing unit of the above flow is divided according to main processing contents in order to facilitate understanding of the processing of the memory controller 133. The present invention is not limited by the way of dividing the processing unit or the name. The processing of the memory controller 133 can be divided into more processing units according to the processing contents. Moreover, it can also divide | segment so that one process unit may contain many processes.

  The embodiment of the present invention has been described above. According to this embodiment, in an electronic device including a DRAM, appropriate power saving mode control suitable for the system can be performed.

  That is, in the present embodiment, the self-refresh mode and the power-down mode can be executed and ended according to various start conditions and end conditions. The start and end of execution of the self-refresh mode and the power-down mode are controlled by the memory controller. The execution and termination of the self-refresh mode and the power-down mode are instructed by a program (software) executed by the CPU.

  The mode, start condition, and end condition used for the electronic device are determined in advance according to the system requirements of the electronic device, and the electronic device is programmed to operate in the determined mode, start condition, and end condition. If this is done, the memory controller is set in accordance with instructions from the CPU, and power saving control is executed.

  As described above, the memory controller having the configuration as in the present embodiment can provide appropriate power saving mode control suitable for the system in an electronic device including a DRAM.

  The above embodiments are intended to exemplify the gist of the present invention and do not limit the present invention. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

100: printing device, 110: controller, 120: CPU, 130: memory control ASIC, 131: interface unit, 132: arbitration circuit, 133: memory controller, 140: SDRAM, 150: I / O control ASIC, 160: engine unit , 170: operation panel, 200: information processing device, 1331: self-refresh start register, 1332: self-refresh timer ON register, 1333: self-refresh timer value register, 1334: self-refresh end register, 1335: power-down start register, 1336 : Power-down timer ON register, 1337: Power-down timer value register, 1338: Power-down end register

Claims (13)

An electronic device comprising a DRAM having a self-fresh mode and a power-down mode, and a memory controller for controlling the DRAM,
The memory controller is
A first register for setting a start condition of the self-refresh mode;
A second register for setting a start condition of the power down mode;
Control means for controlling execution of the self-refresh mode and the power-down mode according to the settings of the first register and the second register;
An electronic device characterized by that. The electronic device according to claim 1,
The first register includes a first start register that instructs the start of the self-refresh mode,
The control means starts executing the self-refresh mode when the first start register is set;
An electronic device characterized by that. The electronic device according to claim 2,
The second register includes a second timer register for starting a second timer for determining the start of the power down mode,
The control means counts the second timer when the second timer register is set, and starts executing the power-down mode when the second timer expires a predetermined value.
An electronic device characterized by that. The electronic device according to claim 3,
The first register includes a first timer register for starting a first timer for determining the start of the self-refresh mode,
The control means counts the first timer when the first timer register is set, and starts executing the self-refresh mode when the first timer expires a predetermined value.
An electronic device characterized by that. The electronic device according to claim 4,
The second register includes a second start register for instructing start of the power down mode,
The control means starts execution of the power down mode when the second start register is set.
An electronic device characterized by that. The electronic device according to claim 5,
The first register includes a first end register that instructs the end of the self-refresh mode,
The second register includes a second end register for instructing the end of the power down mode,
When the first end register is set during the execution of the self-refresh mode, the control means ends the execution of the self-refresh mode, and the second end register is set during the execution of the power-down mode. The power-down mode is terminated.
An electronic device characterized by that. The electronic device according to claim 6,
When the control means receives an access request to the DRAM during execution of the self-refresh mode or the power-down mode, the control means ends execution of the self-refresh mode or the power-down mode.
An electronic device characterized by that. It is an electronic device as described in any one of Claims 5-7,
A CPU,
In the CPU, one of the self-refresh mode and the power-down mode selected in advance according to the performance required for the electronic device is determined in advance according to the performance required for the electronic device. Setting the first register or the second register to be executed according to a start condition;
An electronic device characterized by that. The electronic device according to claim 8,
The CPU
If the electronic device is high-performance, select the self-refresh mode, and instruct the start of the self-refresh mode by the first start register,
If the electronic device has intermediate performance, select the power-down mode and set the second timer to start the second timer,
If the electronic device has low performance, select the self-refresh mode, and set the first timer to start by the first timer register,
An electronic device characterized by that. An electronic device according to any one of claims 5 to 9,
The control means includes a setting timing for the first start register or a timing when the first timer expires the predetermined value, and a setting timing for the second start register or a timing when the second timer expires the predetermined value. Is detected within a predetermined period, the execution of the self-refresh mode is started in preference to the power-down mode,
An electronic device characterized by that. It is an electronic device as described in any one of Claims 5-7,
CPU,
As an operation mode of the electronic device, it has a normal mode and a power saving mode,
The CPU sets the first start register or the second start register when the electronic device shifts from the normal mode to the power saving mode.
An electronic device characterized by that. The electronic device according to claim 11,
The power saving mode includes a first power saving mode and a second power saving mode that consumes less power than the first power saving mode,
The CPU sets the second start register when shifting to the first power saving mode, and sets the first start register when shifting to the second power saving mode.
An electronic device characterized by that. The electronic apparatus according to claim 1,
The electronic device is a printing device.
An electronic device characterized by that.

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