JP2012129407A - Method for manufacturing solar cell element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a solar cell element which is prepared using a conductive paste having a lead-free glass frit and has high conversion efficiency.SOLUTION: In the method for manufacturing the solar cell which includes an application step of applying a conductive paste containing a glass frit which contains bismuth oxide as a main component on one main surface of a semiconductor substrate 1, and a baking step of baking the semiconductor substrate having the conductive paste applied thereon, in the baking step, the maximum temperature for heating is set at 700°C or higher, and a heating time in a temperature range equals to 500°C or higher is set at 10 seconds or less.

Description

  The present invention relates to a method for manufacturing a solar cell element.

  As a method for forming an electrode of a solar cell element provided with a silicon substrate, there is a method of applying and baking a conductive paste. The conductive paste includes, for example, a metal powder containing silver as a main component, glass frit, and an organic vehicle. Glass frit is contained in order to improve the adhesive strength between the silicon substrate and the electrode. In addition, a conductive paste is applied on an antireflection layer such as a silicon nitride film and baked so that an electrode formed of the conductive paste penetrates the antireflection layer and is electrically connected to the silicon substrate. Glass frit is also contained when performing “through”.

Conventionally, many glass frit containing lead oxide (PbO) has been used as a main component. However, lead-free glass frit has been studied in view of environmental concerns. As a lead-free glass frit, for example, one containing bismuth oxide (Bi ₂ O ₃ ) as a main component has been studied. (For example, see Patent Documents 1 to 4)

Special table 2008-543080 gazette JP 2008-109016 A JP 2009-231827 A JP 2010-087501 A

  However, the solar cell element using the glass frit whose main component is bismuth oxide in the above-mentioned document can obtain only a low conversion efficiency compared with the solar cell element using the glass frit whose main component is lead oxide. There wasn't.

  An object of this invention is to provide the manufacturing method of the solar cell element which has the high conversion efficiency produced using the electrically conductive paste which has a lead-free glass frit.

  In order to solve the above-described problem, a method for manufacturing a solar cell element according to one embodiment of the present invention includes a coating step of applying a conductive paste containing glass frit mainly composed of bismuth oxide to one main surface of a semiconductor substrate. And a baking step of baking the semiconductor substrate on which the conductive paste is applied. And in the said baking process, while making the highest temperature of heating into 700 degreeC or more, the heating time in the temperature range of 500 degreeC or more shall be 10 seconds or less.

  According to the method for manufacturing a solar cell element, a solar cell element having high conversion efficiency can be provided.

(A) is the top view which looked at an example of the solar cell element which concerns on one form of this invention from the 1st surface side. It is the top view which looked at the solar cell element shown in FIG. 1 from the 2nd surface side. It is the sectional view on the AA line in FIG. It is a schematic diagram explaining an example of the solar cell module which concerns on one form of this invention, and is a figure which shows the solar cell module provided with multiple solar cell elements of FIG. 1, (a) is a cross-sectional exploded view. (B) is the top view which looked at the solar cell module from the light-receiving surface side.

  Hereinafter, a method for manufacturing a solar cell element according to an embodiment of the present invention will be described in detail with reference to the drawings.

<Basic configuration of solar cell element>
As shown in FIGS. 1 to 3, the solar cell element 10 includes a light receiving surface (upper surface in FIG. 3, hereinafter referred to as a first surface) 10 a on which light is incident and a non-surface corresponding to the back surface of the first surface 10 a. It has a light receiving surface (the lower surface in FIG. 3, hereinafter referred to as a second surface) 10b. The solar cell element 10 includes a plate-like semiconductor substrate 1. As shown in FIG. 3, the semiconductor substrate 1 includes, for example, a first semiconductor layer 2 which is a one-conductivity-type semiconductor layer, and a reverse-conductivity-type provided on the first surface 10a side of the first semiconductor layer 2. And a second semiconductor layer 3 which is a semiconductor layer. The solar cell element 10 further includes a first electrode 6 that is provided on the first surface 10 a side and is electrically connected to the second semiconductor layer 3.

<Specific examples of solar cell elements>
FIGS. 1 to 3 are views showing a solar cell element 10 manufactured using the method for manufacturing a solar cell element according to an embodiment of the present invention. As shown in FIG. 3, in this embodiment, the solar cell element 10 includes a semiconductor substrate 1 (first semiconductor layer 2 and second semiconductor layer 3), a third semiconductor layer 4, an antireflection layer 5, and a first electrode 6. And a second electrode 7.

  As described above, the semiconductor substrate 1 includes the first semiconductor layer 2 and the second semiconductor layer 3 provided on the first surface side of the first semiconductor layer 2.

  As the first semiconductor layer 2, a plate-like semiconductor having one conductivity type (for example, p-type) can be used. As the semiconductor constituting the first semiconductor layer 2, crystalline silicon such as single crystal silicon or polycrystalline silicon is used. The thickness of the first semiconductor layer 2 can be, for example, 250 μm or less, and further 150 μm or less. Although the shape of the 1st semiconductor layer 2 is not specifically limited, From a viewpoint on a manufacturing method, it is good also as a square shape by planar view.

  An example in which a crystalline silicon substrate exhibiting p-type conductivity is used as the first semiconductor layer 2 (plate-like semiconductor) will be described. When the first semiconductor layer 2 made of a crystalline silicon substrate is p-type, for example, boron or gallium can be used as the dopant element.

  The second semiconductor layer 3 that forms a pn junction with the first semiconductor layer 2 is a layer having a conductivity type opposite to that of the first semiconductor layer 2, and is provided on the first surface 10 a side of the first semiconductor layer 2. . If the first semiconductor layer 2 exhibits p-type conductivity, the second semiconductor layer 3 is formed to exhibit n-type conductivity. On the other hand, if the first semiconductor layer 2 exhibits n-type conductivity, the second semiconductor layer 3 is formed to exhibit p-type conductivity. In the silicon substrate in which the first semiconductor layer 2 exhibits p-type conductivity, when the second semiconductor layer 3 is formed in the surface layer of the silicon substrate, for example, the second semiconductor layer 3 is the first surface of the silicon substrate. It can be formed by diffusing impurities such as phosphorus on the 10a side.

The antireflection layer 5 is formed on the first surface 10 a side of the semiconductor substrate 1. The antireflection layer 5 is made of, for example, a silicon nitride film, a titanium oxide film, a silicon oxide film, a magnesium oxide film, an indium tin oxide film, a tin oxide film, or a zinc oxide film. The thickness of the antireflection layer 5 is appropriately selected depending on the material so that a non-reflection condition can be realized for appropriate incident light. In the case where the semiconductor substrate 1 is a silicon substrate, for example, the antireflective layer 5 can have a refractive index of about 1.8 to 2.3 and a thickness of about 500 to 1200 mm. Further, when the antireflection layer 5 is made of a silicon nitride film, it can also have a passivation effect.

The third semiconductor layer 4 is formed on the second surface 10 b side of the semiconductor substrate 1 and has the same conductivity type as the first semiconductor layer 2. And the density | concentration of the dopant which the 3rd semiconductor layer 4 contains has a density | concentration higher than the density | concentration of the dopant which the 1st semiconductor layer 2 contains. That is, the dopant element is present in the third semiconductor layer 4 at a concentration higher than the concentration of the dopant element doped to exhibit one conductivity type in the first semiconductor layer 2. The third semiconductor layer 4 has a role of reducing a decrease in conversion efficiency due to carrier recombination in the vicinity of the second surface 10b of the semiconductor substrate 1, and on the second surface 10b side of the semiconductor substrate 1. It forms an internal electric field. When the first semiconductor layer 2 of the semiconductor substrate 1 is p-type, the third semiconductor layer 4 can be formed, for example, by diffusing a dopant element such as boron or aluminum on the second surface 10b side. At this time, the concentration of the dopant element contained in the third semiconductor layer 4 can be about 1 × 10 ^{18 to} 5 × 10 ²¹ atoms / cm ³ .

  The first electrode 6 is an electrode provided on the first surface 10a side of the semiconductor substrate 1, and as shown in FIG. 1A, the first output extraction electrode 6a and a plurality of linear first current collectors. And an electrode 6b. At least a part of the first output extraction electrode 6a intersects the first current collection electrode 6b. On the other hand, the 1st current collection electrode 6b is linear, and has the width | variety of about 50-200 micrometers in a transversal direction, for example. The first output extraction electrode 6a has, for example, a width of about 1.3 to 2.5 mm in the short direction. And the width | variety of the transversal direction of the 1st current collection electrode 6b is smaller than the width | variety of the transversal direction of the 1st output extraction electrode 6a. Moreover, the 1st current collection electrode 6b is provided with two or more at intervals of about 1.5-3 mm. The thickness of the first electrode 6 is about 10 to 40 μm. The first electrode 6 as described above can be formed, for example, by applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.

  The 2nd electrode 7 is an electrode provided in the 2nd surface 10b side of the semiconductor substrate 1, and as shown in FIG. 2, it has the 2nd output extraction electrode 7a and the 2nd current collection electrode 7b. The thickness of the 2nd output extraction electrode 7a is about 10-30 micrometers, and the width | variety of a transversal direction is about 1.3-7 mm. The second output extraction electrode 7a can be formed by the same material and manufacturing method as the first electrode 6 described above, or may be formed by applying a silver paste in a desired shape and then baking it. The second collector electrode 7b has a thickness of about 15 to 50 μm, and is formed on substantially the entire surface of the second surface 10b of the semiconductor substrate excluding the region where the second output extraction electrode 7a is formed. The second current collecting electrode 7b can be formed, for example, by applying an aluminum paste in a desired shape and baking it.

<Method for producing solar cell element>
The basic manufacturing method of the solar cell element 10 of this embodiment shall perform at least the following processes sequentially.

First, a substrate preparation step for preparing a semiconductor substrate 1 having a p-type first semiconductor layer 2 is performed. Next, an application step is performed in which a conductive paste having a metal powder mainly containing silver, an organic vehicle, and a glass frit mainly containing bismuth oxide (Bi ₂ O ₃ ) is applied to the semiconductor substrate 1. . And the baking process which forms the 1st electrode 6 by baking the semiconductor substrate 1 with which the electrically conductive paste was apply | coated is performed. And in this baking process, while making the maximum temperature of heating into 700 degreeC or more, the heating time in the temperature range of 500 degreeC or more shall be 10 seconds or less.

  Next, a specific example of a method for manufacturing the solar cell element 10 will be described.

  First, the substrate preparation process of the semiconductor substrate 1 constituting the first semiconductor layer 2 will be described. When the semiconductor substrate 1 is a single crystal silicon substrate, it is formed by, for example, a pulling method, and when the semiconductor substrate 1 is a polycrystalline silicon substrate, it is formed by, for example, a casting method. Hereinafter, an example using a p-type polycrystalline silicon substrate will be described.

  First, a polycrystalline silicon ingot is produced by, for example, a casting method. Next, the ingot is sliced to a thickness of 250 μm or less, for example. Thereafter, in order to clean the mechanical damage layer and the contamination layer on the cut surface of the semiconductor substrate 1, the surface may be subjected to a very small amount of etching with NaOH, KOH, hydrofluoric acid, or hydrofluoric acid. Note that, after this etching step, a minute uneven structure may be formed on the surface of the semiconductor substrate 1 by using a wet etching method or a dry etching method.

Next, the n-type second semiconductor layer 3 is formed in the surface layer on the first surface 10a side of the semiconductor substrate. Such a second semiconductor layer 3 has a coating thermal diffusion method in which P ₂ O ₅ in a paste state is applied to the surface of a semiconductor substrate and thermally diffused, and POCl ₃ (phosphorus oxychloride) in a gas state is used as a diffusion source. The gas phase thermal diffusion method and the ion implantation method for directly diffusing phosphorus ions are used. The second semiconductor layer 3 is formed to have a depth of about 0.2 to 2 μm and a sheet resistance of about 40 to 200Ω / □.

  Next, when the second semiconductor layer 3 is formed on the second surface 10b side, only the second surface 10b side is removed by etching to expose the p-type conductivity type region on the second surface 10b side. Let For example, the second semiconductor layer 3 is removed by immersing only the second surface 10b side of the semiconductor substrate in a hydrofluoric acid solution. Thereafter, the phosphor glass adhering to the surface of the semiconductor substrate 1 when the second semiconductor layer 3 is formed is removed by etching. In this way, the phosphorous glass remains on the first surface 10a side and the second semiconductor layer 3 formed on the second surface 10b side is removed, whereby the second semiconductor layer 3 on the first surface 10a side is made of phosphorous glass. Can be removed or damaged. Also, a similar structure is formed by a process in which a diffusion mask is formed in advance on the second surface 10b side, the second semiconductor layer 3 is formed by a vapor phase thermal diffusion method or the like, and then the diffusion mask is removed. It is possible.

  As described above, the semiconductor substrate 1 including the first semiconductor layer 2 having the p-type semiconductor layer and the second semiconductor layer 3 having the n-type semiconductor layer can be prepared.

Next, the antireflection layer 5 is formed on the first surface 10 a side of the semiconductor substrate 1, that is, on the second semiconductor layer 3. The antireflection layer 5 is made of, for example, PECVD (plasma enhanced chemical vapor).
deposition) method, vapor deposition method, sputtering method or the like. For example, when the antireflection layer 5 made of a silicon nitride film is formed by PECVD, the reaction chamber is set to about 500 ° C. and a mixed gas of silane (SiH ₄ ) and ammonia (NH ₃ ) is nitrogen (N ₂ ). The antireflective layer 5 is formed by diluting with plasma and depositing the plasma by glow discharge decomposition.

Next, on the second surface 10b side of the semiconductor substrate 1, the third semiconductor layer 4 in which one conductivity type semiconductor impurity is diffused at a high concentration is formed. As the manufacturing method, for example, the following two methods can be employed. The first method is a method of forming at a temperature of about 800 to 1100 ° C. using a thermal diffusion method using BBr 3 (boron tribromide) as a diffusion source. The second method is a method in which an aluminum paste made of aluminum powder, an organic vehicle, or the like is applied by a printing method, and then heat treated (baked) at a temperature of about 600 to 850 ° C. to diffuse aluminum into the semiconductor substrate 1. . Further, if this second method is used, not only a desired diffusion region can be formed only on the printing surface, but also the second surface can be formed in the same step as the step of forming the second semiconductor layer 3 on the first surface 10a side. It is not necessary to remove the n-type second semiconductor layer 3 formed on the 10b side. Therefore, it is sufficient to perform pn separation using only a peripheral portion on the first surface 10a side or the second surface 10b side, and the manufacturing process can be simplified.

  Next, the first electrode 6 (first output extraction electrode 6a, first collector electrode 6b) and the second electrode 7 (second output extraction electrode 7a, second collector electrode 7b) are formed as follows. To do.

The first electrode 6, a metal powder consisting mainly of silver, and glass frit mainly composed of bismuth oxide (Bi 2 _{O 3),} you are manufactured using a conductive paste containing an organic vehicle, a.

  The metal powder is contained at a ratio of about 70 to 95% by mass with respect to the entire conductive paste, and the average particle size of the metal powder can be about 0.1 to 5 μm. Here, the average particle diameter may be a cumulative 50% particle diameter from the small diameter side when the particle diameter is measured by the microtrack particle size distribution measuring method. Moreover, the particle shape of the metal powder is not particularly limited, and may be, for example, spherical or flake shaped. In addition, the metal powder which has silver as a main component means that silver contains more than 50 mass% with respect to the whole metal powder. Examples of metals other than silver contained in the metal powder include copper and nickel.

  As the glass frit, a lead-free glass frit mainly composed of bismuth oxide is used. Here, bismuth oxide as a main component means that bismuth oxide is contained in an amount of more than 50% by mass with respect to the entire components of the glass frit. The glass frit may contain boron oxide or silicon oxide as a component other than bismuth oxide for vitrification. Further, the glass frit can appropriately contain zinc oxide, aluminum oxide, antimony oxide, calcium oxide, zirconium oxide, selenium oxide, barium oxide, magnesium oxide, manganese oxide, lithium oxide, copper oxide and the like as required. . The average particle size of the glass frit may be about 0.05 to 1 μm. Here, the average particle diameter of the glass frit can also be measured by the same method as the average particle diameter of the metal powder described above. And content of the glass frit in an electrically conductive paste can be 1-10 mass% with respect to the whole electrically conductive paste, for example.

  The organic vehicle is obtained by dissolving an organic binder in an organic solvent. Examples of the organic solvent include butyl carbitol, butyl carbitol acetate, butyl cellosolve, butyl cellosolve acetate, terpineol, hydrogenated terpineol, hydrogenated terpineol acetate, methyl ethyl ketone, isobornyl acetate, and nopylacetate. Examples of the organic binder include cellulose resins such as methyl cellulose, ethyl cellulose, and nitrocellulose, acrylic resins such as methyl methacrylate, and butyral resins.

  In addition, additives such as anionic and nonionic dispersants and surfactants may be added to the conductive paste. Thereby, the dispersibility of the metal powder and the glass frit in the conductive paste can be improved.

The first electrode 6 is formed by applying a conductive paste having such a composition to the first surface 10a of the semiconductor substrate 1 and then baking it in an oxygen-containing atmosphere. At this time, the conductive paste is baked under a high temperature condition in which the maximum heating temperature is 700 ° C. or higher. As a result, the component of the conductive paste applied on the antireflection layer 5 by the fire-through in which the glass frit and the antireflection layer 5 react with each other breaks through the antireflection layer 5, and the first electrode 6 electrically connected to the semiconductor substrate 1 is formed. It is formed. Here, a screen printing method or the like can be used as a method for applying the conductive paste. After application, the solvent may be evaporated and dried at a predetermined temperature.

  At this time, a solar cell element having high conversion efficiency can be formed by setting the heating time in the temperature range of 500 ° C. or higher to 10 seconds or less in the baking step. This is because the reactivity of the glass frit mainly composed of bismuth oxide with the antireflection layer 5 is higher than that of the glass frit mainly composed of lead oxide. From this, it is possible to reduce the glass frit from penetrating the second semiconductor layer 3 and damaging the second semiconductor layer 3 by setting the heat load time at a temperature higher than the softening point of the glass as described above. Inferred.

  Furthermore, by setting the maximum heating temperature in the firing step to 700 ° C. or higher, preferably 750 ° C. or higher, good fire-through is performed.

When the second semiconductor layer 3 is formed by a thermal diffusion method such as a coating thermal diffusion method or a vapor phase thermal diffusion method, the first electrode 6 is formed compared to the temperature (maximum temperature) at which the second semiconductor layer 3 is formed. The maximum heating temperature in the firing step can be reduced. Thereby, the penetration into the second semiconductor layer 3 due to the glass frit can be reduced, and a solar cell element having high conversion efficiency can be formed. For example, the temperature (maximum temperature) for forming the second semiconductor layer 3 can be 800 ° C. or higher, preferably 820 ° C. or higher. For example, in the vapor phase thermal diffusion method, phosphorous glass is formed on the surface of the semiconductor substrate by heat-treating the semiconductor substrate for about 5 to 30 minutes at a temperature of about 600 ° C. to 800 ° C. in an atmosphere having a diffusion gas such as POCl _3. Then, phosphorus is diffused from the phosphor glass to the semiconductor substrate by heat-treating the semiconductor substrate for about 10 to 40 minutes at a high temperature of about 800 to 900 ° C. in an inert gas atmosphere such as argon or nitrogen, and the second semiconductor layer. 3 is formed.

  Moreover, the baking process which forms the 1st electrode 6 has a 1st process heated from 500 degreeC to the highest temperature, and a 2nd process cooled from the highest temperature to 500 degreeC.

  At this time, in the first step, the temperature may be continuously increased from 500 ° C. to the maximum temperature without being kept at a constant temperature. Also in the subsequent second step, the temperature may be continuously decreased from the maximum temperature to 500 ° C. without providing a time for keeping the temperature constant. Thereby, the damage of the 2nd semiconductor layer 3 can be reduced, and the favorable contact property of the 1st electrode 6 and the semiconductor substrate 1 can be obtained.

  Further, the time required to reach 500 ° C. from the maximum temperature can be shorter than the time required to reach the maximum temperature from 500 ° C. That is, the cooling time T2 in the second step can be shorter than the heating time T1 in the first step. By extending the time period during which the temperature rises in this way, the reaction shortage between the glass frit and the antireflection layer 5 can be reduced, and by shortening the time period during which the temperature falls, the heat load time is shortened and the second time period. The penetration to the semiconductor layer 3 can be reduced. As a result, a solar cell element with high conversion efficiency can be formed.

  Here, the heating time in the first step is a total heating time from 500 ° C. to the maximum temperature. That is, it includes the time during which the temperature is maintained at a constant temperature from 500 ° C. without increasing the temperature. The cooling time in the second step can be defined similarly.

  The heating time T1 in the first step and the cooling time T2 in the second step can be appropriately selected according to the thickness of the second semiconductor layer 3, the thickness of the antireflection layer 5, and the like. For example, the heating time T1 in the first step can be 3.5 seconds or more and 7 seconds or less, and the cooling time T2 in the second step can be 2.5 seconds or more and 5 seconds or less.

  Further, in the first step of heating from 500 ° C. to the maximum temperature, the temperature increase rate in the second half can be made smaller than the temperature increase rate in the first half. In other words, the first step may include a pre-step for heating at the first temperature rise rate Δt1 and a post-step for heating at the second temperature rise rate Δt2 smaller than the first temperature rise rate Δt1. Good. Specifically, for example, the temperature increase rate at a temperature 50 ° C. lower than the maximum temperature may be set lower than the temperature increase rate in the vicinity of 500 ° C. to 600 ° C.

  Thereby, the time slot | zone near the maximum temperature in a 1st process can be lengthened, and the reaction deficiency with a glass frit and the antireflection layer 5 can be reduced. As a result, the sinterability of the metal powder in the firing step can be improved and the line resistance of the first electrode 6 can be reduced. Moreover, the time zone around 500 ° C. to 600 ° C. in the first step can be shortened, and the heat load time in the firing step can be shortened. As a result, damage to the second semiconductor layer 3 due to penetration of the glass frit into the second semiconductor layer 3 can be reduced, and a solar cell element with high conversion efficiency can be formed.

  For each temperature increase rate, for example, the temperature increase rate Δt1 in the previous process is set to 100 ° C./second or more and 230 ° C./second or less, and the temperature increase rate Δt2 in the subsequent process is set to 80 ° C./second or more and 30 ° C./second or less Can do. Further, the difference between the temperature increase rate Δt1 in the previous step and the temperature increase rate Δt2 in the subsequent step can be set to 50 ° C./second or more. As described above, the first step may include a holding step that is held at a constant temperature in addition to the pre-step and the post-step. This holding process may be provided before the previous process, between the previous process and the subsequent process, and after the subsequent process. Moreover, the heat load time in a baking process can be shortened by raising temperature continuously from 500 degreeC to the maximum temperature, without providing a holding process.

  In addition, the time for heating from room temperature to 500 ° C. is not particularly limited, but in order to sufficiently evaporate the solvent in the conductive paste, for example, the heating time in the temperature range of 300 ° C. or higher and lower than 500 ° C. is 15 seconds or longer and 60 seconds. It is good also as follows.

  Next, the second electrode 7 will be described. As described above, the second electrode 7 includes the second output extraction electrode 7a and the second collector electrode 7b.

  First, the 2nd current collection electrode 7b is produced using the aluminum paste containing aluminum powder and an organic vehicle, for example. This aluminum paste is applied to almost the entire second surface 10b except for a part of the portion where the second output extraction electrode 7a is to be formed. As a coating method, a screen printing method or the like can be used. After applying the aluminum paste in this way, the solvent may be evaporated and dried at a predetermined temperature. In this case, the workability is improved because the aluminum paste hardly adheres to other parts during the subsequent work.

  Next, the 2nd output extraction electrode 7a is produced using the silver paste containing the metal powder which consists of silver powder etc., an organic vehicle, and glass frit, for example. This silver paste is applied to the second surface 10b in a predetermined shape. At this time, the silver paste is applied at a position in contact with a part of the aluminum paste, so that the second output extraction electrode 7a and the second current collecting electrode 7b overlap each other. As a coating method, a screen printing method or the like can be used. After the application, the solvent may be evaporated and dried at a predetermined temperature.

  Then, the semiconductor substrate 1 thus coated with the aluminum paste and the silver paste is baked for about several tens of seconds to several tens of minutes in a baking furnace at a maximum temperature of 600 to 850 ° C. 7 is formed on the second surface 10 b side of the semiconductor substrate 1.

In the present embodiment, electrode formation by printing / firing is used as a method for forming the second electrode 7, but thin film formation such as vapor deposition or sputtering, or plating can also be used.

  As described above, the solar cell element 10 having excellent output characteristics can be quickly and easily manufactured with a small number of steps.

  In addition, this invention is not limited to the said embodiment, Many corrections and changes can be added within the scope of the present invention as follows.

  For example, the conductive paste applied to the first surface 10a and the aluminum paste and silver paste applied to the second surface 10b may be fired simultaneously.

Further, a passivation film may be provided on the second surface 10 b side of the semiconductor substrate 1. This passivation film has a role of reducing carrier recombination on the second surface 10 b which is the back surface of the semiconductor substrate 1. As a passivation film, a silicon nitride film such as a silicon nitride (Si ₃ N ₄ ) film, an amorphous Si nitride (a-SiNx) film, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or titanium oxide ( A film such as TiO ₂ ) can be used. Note that the passivation film can be about 100 to 2000 mm in thickness, and may be formed using a PECVD method, a vapor deposition method, a sputtering method, or the like. Therefore, the structure on the second surface 10b side of the semiconductor substrate 1 can be a structure on the second surface 10b side used in a PERC (Passivated Emitter and Rear Cell) structure or a PERL (Passivated Emitter Rear Locally-diffused) structure. .

  Moreover, the 1st electrode 6 may further have the linear auxiliary electrode 6c which cross | intersects with respect to the longitudinal direction of the 1st current collection electrode 6b in the both ends of the 1st current collection electrode 6b. In this case, even if a part of the first collector electrode 6b is broken, the auxiliary electrode 6c can move the carrier to the first output extraction electrode 6a through the other first collector electrode 6b.

  In addition, at the intersection of the first collector electrode 6b and the first output extraction electrode 6a, or the first collector electrode 6b and the auxiliary electrode 6c, the width of the first collector electrode 6b is equal to the first output extraction electrode 6a or It may be widened toward the auxiliary electrode 6c. As described above, since the width of the first current collecting electrode 6b is very narrow, the line is broken at the intersection with the first output extraction electrode 6a or the auxiliary electrode 6c extending perpendicularly to the longitudinal direction of the first current collecting electrode 6b. Although it may occur, the occurrence of line breakage can be reduced by increasing the width of the first current collecting electrode 6b at the intersection.

  A fourth semiconductor layer that has the same conductivity type as the second semiconductor layer 3 and is thicker than the second semiconductor layer 3 may be formed at the position where the first electrode 6 is formed. That is, not the second semiconductor layer 3 but the fourth semiconductor layer may be formed at the position where the first electrode 6 is formed on the first surface 10a. At this time, the fourth semiconductor layer is formed so that the sheet resistance is lower than that of the second semiconductor layer 3. By forming the fourth semiconductor layer located under the first electrode 6 thick, damage to the pn junction region in forming the first electrode 6 can be reduced. As an example of a method of increasing the thickness of the fourth semiconductor layer, for example, after forming the second semiconductor layer 3 by a coating thermal diffusion method or a vapor phase thermal diffusion method, There is a method of irradiating the semiconductor substrate 1 with a laser in accordance with the electrode shape. As a result, phosphorus is re-diffused from the phosphor glass to the second semiconductor layer 3, and a thick fourth semiconductor layer is formed at the position where the first electrode 6 is formed.

Further, aluminum oxide particles may be added to the conductive paste used to form the first electrode 6. Aluminum oxide has a higher wettability with glass components than silver, and easily adsorbs to glass during firing. Therefore, by adding aluminum oxide to the conductive paste, part of the glass component melted during firing stays in the electrode and is formed by bonding with the glass component present at the interface of the semiconductor substrate 1. This contributes to improving the adhesion strength of the first electrode 6. Furthermore, since the amount of glass frit reaching the interface of the semiconductor substrate 1 is reduced, damage to the second semiconductor layer 3 due to penetration of the glass frit into the second semiconductor layer 3 is reduced, and a solar cell element with high conversion efficiency is obtained. Can be formed. The aluminum oxide has a content of 0.5% or more and 5% or less with respect to the total content of metal powder and glass frit (= 1 to 5 with respect to the total content of silver powder and glass frit 100). The conductive paste may be contained. Moreover, the average particle diameter of aluminum oxide can be 0.1 micrometer or more and 5 micrometers or less, and can be measured by the method similar to the average particle diameter of the metal powder mentioned above.

<< Solar cell module >>
A solar cell module including one or more solar cell elements 10 of the present embodiment will be described. Hereinafter, a solar cell module in which a plurality of the solar cell elements 10 are electrically connected will be described as an example.

  A solar cell module is configured by connecting a plurality of solar cell elements 10 in series and in parallel, such as when the electric output of a single solar cell element 10 is small. By combining a plurality of these solar cell modules, a practical electrical output can be taken out.

  As shown in FIG. 4A, the solar cell module 20 includes, for example, a transparent member 22 such as glass, a front side filler 24 made of transparent EVA, a plurality of solar cell elements 20, and the plurality of solar cells. A wiring member 21 for connecting the battery element 10, a back side filler 25 made of EVA, etc., and a back surface protective material 23 made of a material such as polyethylene terephthalate (PET) or polyvinyl fluoride resin (PVF), and having a single layer or a laminated structure. And mainly.

  Adjacent solar cell elements 10 are electrically connected in series with each other by connecting the first electrode 6 of one solar cell element 10 and the second electrode 7 of the other solar cell element 10 by a wiring member 21. It is connected. As the wiring member 21, for example, a member in which the entire surface of a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is covered with a solder material is used.

  In addition, among the plurality of solar cell elements 10 connected in series, one end of the electrode of the first solar cell element 10 and the last solar cell element 10 is respectively connected to a terminal box 27 which is an output extraction part, and an output extraction wiring 26. Connected by. Moreover, although illustration is abbreviate | omitted in Fig.4 (a), as shown in FIG.4 (b), the solar cell module 20 may be provided with the frame 28 which consists of aluminum etc. As shown in FIG.

  Since the solar cell module 20 according to the present embodiment includes the solar cell element 10 having the first electrode 6 formed by the above-described good fire-through, it can exhibit high conversion efficiency.

  Hereinafter, more specific examples will be described. The reference drawings are FIGS.

  First, a polycrystalline silicon substrate (semiconductor substrate) having a thickness of 220 μm, an outer shape of 156 mm × 156 mm, and a specific resistance of 1.5 Ω · cm was prepared, and the damaged layer on the surface of the silicon substrate was etched and washed with NaOH.

Next, the concavo-convex structure 1a was formed on the first surface 10a of the semiconductor substrate by dry etching. Then, the second semiconductor layer 3 was formed on the first surface 10a of the semiconductor substrate by vapor phase thermal diffusion using POCl ₃ as a diffusion source. At this time, the sheet resistance of the second semiconductor layer 3 was 70Ω / □. Thus, the semiconductor substrate 1 including the first semiconductor layer 2 and the second semiconductor layer 3 was prepared.

  The obtained semiconductor substrate 1 was subjected to etching removal of phosphorous glass with a hydrofluoric acid solution, and then a silicon nitride film to be the antireflection layer 5 was formed on the first surface 10a by PECVD.

  Further, an aluminum paste was applied to almost the entire surface of the second surface 10b of the semiconductor substrate 1 and baked to form the third semiconductor layer 4 and the second current collecting electrode 7b. A first paste 6 and a second output extraction electrode 7a were formed by applying and baking a silver paste on the first surface 10a and the second surface 10b.

  At this time, the silver paste used for the first electrode 6 was a mixture of silver powder, bismuth oxide glass frit, and organic vehicle. The silver paste was applied by a screen printing method and baked under the heating conditions shown in Table 1 to form the first electrode 6. The maximum heating temperature in this firing step was 840 ° C.

  The composition of the glass frit was 78% by mass of bismuth oxide, 4% of boron oxide, 3% of silicon oxide, 10% of zinc oxide and 3% of other components in terms of oxide.

  Moreover, the content mass of the silver powder in the silver paste used for the 1st electrode 6 was 80 mass%, and the content mass of the glass frit was 5 mass% with respect to the content mass of this silver powder.

  Finally, pn separation with a laser was performed in the peripheral portion on the second surface 10b side of the semiconductor substrate 1 to form a solar cell element.

The solar cell element output characteristics (short-circuit current Isc, open-circuit voltage Voc, fill factor FF, conversion efficiency) were measured and evaluated for the solar cell elements fabricated under each condition. In addition, the measurement of these characteristics was measured on the conditions of irradiation of AM1.5 and 100 mW / cm < ² > based on JISC8913. The results are shown in Table 1. In Table 1, No. Table 2 shows the temperature profile under the condition of 2.

  From the results in Table 1, the condition No. 1 in which the heating time in the temperature range of 500 ° C. or higher is 12.4 seconds. No. 10 which is 10 seconds or less compared to No. 10. 1 to 9 were solar cell elements having high conversion efficiency due to the improvement in voltage and fill factor.

  This is presumably because the saturation current due to the recombination of carriers in the depletion layer region could be reduced by reducing the penetration to the second semiconductor layer 3 in the firing step, which is the formation step of the first electrode 6.

No. 2 and No. 3 and no. Compared with 4-8, the solar cell element which has high conversion efficiency is obtained by shortening the cooling time T2 in a 2nd process rather than the heating time T1 in a 1st process.

  No. 4 and no. 5 and no. 6 and no. 7 is compared, the solar cell element having high conversion efficiency is obtained by making the second temperature rising rate Δt2 in the subsequent step smaller than the first temperature rising rate Δt1 in the previous step.

  Furthermore, a silver paste to which 3% by mass of aluminum oxide powder was added was prepared under Condition No. It was confirmed that the solar cell element formed by firing at 4 had a fill factor of 7.75 and improved conversion efficiency to 16.3%.

1: Semiconductor substrate 2: 1st semiconductor layer 3: 2nd semiconductor layer 4: 3rd semiconductor layer 5: Antireflection layer 6: 1st electrode 6a: 1st output extraction electrode 6b: 1st current collection electrode 7: 2nd Electrode 7a: Second output extraction electrode 7b: Second collector electrode 10: Solar cell element 10a: First surface 10b: Second surface

Claims (6)

An application step of applying a conductive paste containing glass frit mainly composed of bismuth oxide to one main surface of a semiconductor substrate;
Firing step of firing the semiconductor substrate coated with the conductive paste,
In the firing step, the maximum heating temperature is set to 700 ° C. or higher, and the heating time in a temperature range of 500 ° C. or higher is set to 10 seconds or less. The firing step includes a first step of heating from 500 ° C. to the maximum temperature and a second step of cooling from the maximum temperature to 500 ° C.,
The method for manufacturing a solar cell element according to claim 1, wherein the cooling time in the second step is shorter than the heating time in the first step. The firing step includes a first step of heating from 500 ° C. to the maximum temperature,
The first step includes a pre-step of heating at a first temperature rise rate and a post-step of heating at a second temperature rise rate smaller than the first temperature rise rate after the pre-step. The manufacturing method of the solar cell element of Claim 1 or Claim 2 characterized by these. In addition to using the semiconductor substrate having one conductivity type in the coating step, the method further includes a diffusion step of diffusing reverse conductivity type impurities into the one main surface of the semiconductor substrate by a thermal diffusion method.
The method for manufacturing a solar cell element according to any one of claims 1 to 3, wherein a heating temperature in the diffusion step is higher than a maximum temperature in the firing step.   5. The solar cell element according to claim 1, wherein in the applying step, the conductive paste is applied on an antireflection layer formed on the one main surface of the semiconductor substrate. Manufacturing method.   The method for manufacturing a solar cell element according to any one of claims 1 to 5, wherein the conductive paste further containing aluminum oxide particles is used in the coating step.

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