JP2012128054A - Electro optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify configuration.SOLUTION: A scanning line driving circuit 34 comprises: a shift register 340 for generating a shift signal SR synchronizing with a Y clock signal CLY so as to be exclusively active; m pieces of first circuits Ua1 through Uam; and m pieces of second circuits Ub1 through Ubm. A shift signal SR[i] and a first enabling signal EN1 are supplied to a first circuit Uai, and the first circuit Uai outputs a scanning signal GWR[i] becoming active when the shift signal SR[i] and the first enabling signal EN1 simultaneously become active. The shift signal SR[i] and a second enabling signal EN2 are supplied to a second circuit Uai, and the second circuit Uai outputs a power supply potential VEL[i], first potential, when the shift signal SR[i] and the second enabling signal EN2 simultaneously become active.

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In a light emitting device in which a driving transistor controls a driving current supplied to a light emitting element, an error in characteristics of the driving transistor (difference from a target value or variation among pixels) becomes a problem. In Patent Document 1, the threshold voltage and mobility error of a driving transistor are reduced by changing the voltage between the gate and source of the driving transistor to a threshold voltage of the driving transistor and then changing the voltage to a voltage according to the gradation. Techniques for compensating are disclosed.

  The light emitting device disclosed in Patent Document 1 includes a plurality of scanning lines and a plurality of power supply lines formed in the row direction, and a plurality of signal lines formed in the column direction, and corresponds to the intersection between the scanning lines and the signal lines. Thus, a plurality of pixel circuits are arranged. Each of the plurality of pixel circuits includes a sampling transistor that has a gate connected to the scanning line and captures the data potential of the signal line, a storage capacitor that stores the captured data potential, a drain that connects to the power supply line, and a gate that connects to the storage capacitor And a drive transistor for supplying a current corresponding to the gate potential to the light emitting element.

  The plurality of scanning lines are scanned by the scanner. In this light emitting device, driving is performed by dividing into a threshold correction preparation period, a threshold correction period, and a sampling period / mobility correction period. More specifically, a part of the threshold correction preparation period, a subsequent threshold correction period (hereinafter referred to as the first period), and a sampling period / mobility correction period (hereinafter referred to as the second period) in one horizontal scanning period. In this case, the potential of the scanning line becomes a high level, and the sampling transistor is turned on. Accordingly, the potential of the scanning line becomes active twice in one horizontal scanning period such as the first period and the second period.

JP 2008-32863 A

Incidentally, Patent Document 1 does not disclose details of the scanner. It has not been known how to generate the potential of the scanning line that becomes active twice in one horizontal scanning period. In this case, a shift signal that is exclusively active every horizontal scanning period is generated, and the pulse width of each shift signal is set to an enable signal that is active in the first period and an enable signal that is active in the second period. It is conceivable to limit the use.
However, when two types of enable signals are supplied to the light emitting panel, there is a problem that the number of terminals increases.
Further, the conventional light emitting device requires a power supply scanner that drives the power supply line in addition to the scanner that drives the scanning line, and thus the configuration is complicated.

  In order to solve the above problems, an electro-optical device according to the present invention includes a plurality of scanning lines each extending in the first direction, and a plurality of scanning lines provided corresponding to the plurality of scanning lines. A plurality of power lines, a plurality of data lines each extending in a second direction different from the first direction, and a plurality of data lines arranged corresponding to each intersection of the plurality of scanning lines and the plurality of data lines A pixel circuit; a driving circuit that supplies a scanning signal to each of the plurality of scanning lines; and a control circuit that supplies a first enable signal and a clock signal that is inverted every unit period to the driving circuit, Each of the plurality of pixel circuits is disposed between a light emitting element, a driving transistor that is supplied with power from the power supply line and supplies a driving current corresponding to a gate potential to the light emitting element, and a gate and a source of the driving transistor. Capacitive element and the drive A selection transistor disposed between a gate of the transistor and a data line corresponding to the pixel circuit, and the drive circuit receives a plurality of shift signals that are exclusively active in synchronization with the clock signal. An output shift register is provided in a one-to-one correspondence with the plurality of shift signals, the shift signal and the first enable signal are supplied, and the shift signal and the first enable signal are simultaneously activated. A plurality of first circuits that output the scanning signal that becomes active in the case, the unit period includes an initialization period in which a first potential is supplied to the power supply line, and a second potential is supplied to the power supply line A compensation period, a holding period, and a writing period in which a data signal is supplied to the data line, and the control circuit determines whether the holding period of an arbitrary unit period ends. , And generates the first enable signal so as to be active in the period until the start of the holding period of the next unit period.

  According to the present invention, the first enable signal becomes active during a period from the end of the holding period in an arbitrary unit period to the start of the holding period of the next unit period. In other words, the active period of the first enable signal continues in successive unit periods and straddles the timing at which the logic level of the clock signal is inverted. In the first half of the active period of the first enable signal, a writing period of a certain unit period is specified, and in the second half, an initialization period and a compensation period of the next unit period are specified. As a result, the scanning signal becomes active during the initialization period, the compensation period, and the writing period, and becomes inactive during the holding period. Since various control signals are generated based on a clock signal, they are usually processed for each unit period. In the present invention, by using the first enable signal whose active period extends over two unit periods, A scanning signal can be generated with a simple configuration.

In the electro-optical device described above, the control circuit supplies a second enable signal that is active in the initialization period and inactive in the other period to the drive circuit, and the drive circuit includes the plurality of shift signals. And the shift signal and the second enable signal are supplied, and when the shift signal and the second enable signal are simultaneously activated, the first potential is supplied to the feeder line. And a plurality of second circuits that output the second potential to the power supply line in other periods.
According to this invention, the shift register can be shared by the configuration for supplying the first potential or the second potential to the power supply line and the configuration for supplying the scanning signal to the scanning line. As a result, the configuration can be simplified and power consumption can be reduced as compared with the case where shift registers are used individually.

In the electro-optical device described above, the first circuit shifts a signal level of a first logic circuit that calculates a logical product of the shift signal and the first enable signal, and an output signal of the first logic circuit. A first level shifter for outputting the scanning signal, wherein the second circuit calculates a logical inversion of the shift signal and the second enable signal, and an output of the second logic circuit And a second level shifter that shifts the signal level of the signal and outputs a power supply potential that becomes the first potential or the second potential.
According to the present invention, since the first level shifter is provided in the subsequent stage of the first logic circuit and the second level shifter in the subsequent stage of the second logic circuit is provided, the level can be converted in the final stage. Therefore, power consumption can be reduced.

In the electro-optical device described above, the driving circuit supplies a reference potential at which the driving transistor is turned on to the plurality of data lines in the initialization period, and displays the reference potential on the plurality of data lines in the writing period. It is preferable to include a data line driver circuit that supplies a data potential corresponding to the power gradation.
According to the present invention, since the drive transistor is turned on in the initialization period, when the second potential is supplied to the power supply line in the subsequent compensation period, the source potential of the drive transistor gradually approaches the threshold voltage. To change. Therefore, it becomes possible to compensate the threshold voltage of the drive transistor.

  An electronic apparatus according to the present invention includes the above-described electro-optical device. A typical example of such an electronic device is a device that uses an electro-optical device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone.

It is a block diagram of the light-emitting device concerning an embodiment. It is a circuit diagram which shows the structure of a pixel circuit. It is a block diagram which shows the structure of a scanning line drive circuit. It is a timing chart which shows operation | movement of a light-emitting device. It is a figure which shows operation | movement of the pixel circuit in an initialization period. It is a figure which shows operation | movement of the pixel circuit in a compensation period. It is a figure which shows operation | movement of the pixel circuit in a holding | maintenance period. It is a figure which shows operation | movement of the pixel circuit in the writing period. It is a figure which shows operation | movement of the pixel circuit in the light emission period. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention.

<A: Embodiment>
The electro-optical device is a device that includes an electro-optical element whose optical characteristics are changed by electric energy. In the embodiments described below, a light-emitting element whose luminance changes in accordance with a drive current will be described as an example of an electro-optical element, and a light-emitting device will be described as an example of an electro-optical device.
<A-1: Configuration and Operation of Light Emitting Device>
FIG. 1 is a block diagram of a light emitting device 1 according to an embodiment of the present invention.
The light emitting device 1 is mounted on an electronic device as a display device that displays an image. As shown in FIG. 1, the light emitting device 1 includes a light emitting panel 100 and a control circuit 200. The control circuit 200 generates a Y clock signal CLY, a first enable signal EN1, a second enable signal EN2, a Y transfer start pulse SPY, an X clock signal CLX, an X transfer start pulse SPX, and a data signal D, and performs electro-optics. It supplies to the light emission panel 100 which is a kind of panel.
The light emitting panel 100 is formed with a plurality of input terminals for capturing various signals from the control circuit 200 (not shown). The light emitting panel 100 includes an element unit 10 in which a plurality of pixel circuits U are arranged, and a drive circuit 30 that drives each pixel circuit U. The drive circuit 30 includes a scanning line drive circuit 34 and a data line drive circuit 36. The drive circuit 30 in this example is composed of a thin film transistor formed on a substrate together with the pixel circuit U. However, a part or all of the drive circuit 30 may be distributed over a plurality of integrated circuits and mounted on the light-emitting panel 100, or mounted on a flexible substrate that is electrically connected to the input terminal of the light-emitting panel 100. May be.

  The element unit 10 includes m scanning lines 12 extending in the X direction, m feeder lines 20 extending in the X direction in pairs with the scanning lines 12, and a Y direction intersecting the X direction. N data lines 14 extending to (m and n are natural numbers) are formed. The plurality of pixel circuits U are arranged at intersections of the scanning lines 12 and the data lines 14 and are arranged in a matrix of m rows × n columns.

  The scanning line driving circuit 34 is a circuit for sequentially selecting a plurality of pixel circuits U in units of rows. The scanning line driving circuit 34 sequentially applies the scanning signals GWR [1] to GWR [m] to the active level (m) in each of the m horizontal scanning periods H (H [1] to H [m]) in the vertical scanning period. By setting to high level, each scanning line 12 (a set of n pixel circuits U in each row) is sequentially selected. Further, the scanning line driving circuit 34 generates power supply potentials VEL [1] to VEL [m] and outputs them to the power supply lines 20.

  The data line driving circuit 36 generates data potentials VX [1] to VX [n] corresponding to one row (n) of pixel circuits U selected by the scanning line driving circuit 34 in a writing period PWRT described later. To each data line 14. Data potential output to the data line 14 in the j-th column (j is an integer satisfying 1 ≦ j ≦ n) in the writing period PWRT in which the i-th row (i is an integer satisfying 1 ≦ i ≦ m) is selected. VX [j] is set to a potential corresponding to the designated gradation of the pixel circuit U located in the i-th row and the j-th column.

  FIG. 2 is a circuit diagram of the pixel circuit U. In FIG. 2, a pixel circuit U disposed corresponding to the intersection of the data line 14 in the j-th column and the scanning line 12 in the i-th row is illustrated. The pixel circuit U includes a light emitting element E, a driving transistor TDR, a selection transistor TS, and a capacitive element CST (capacitance value cp2). The drive transistor TDR and the light emitting element E are arranged in series on a path connecting the power supply line 20 and the power supply line 21 to which the lower potential VCT is supplied. The light emitting element E is an organic EL element in which a light emitting layer of an organic EL (Electroluminescence) material is interposed between an anode and a cathode that face each other. As shown in FIG. 2, the light emitting element E is accompanied by a capacitance CE (capacitance value cp1) as a parasitic capacitance.

The drive transistor TDR is an N-channel transistor (for example, a thin film transistor) whose drain is connected to the power supply line 20 and whose source is connected to the anode of the light emitting element E. The capacitive element CST is interposed between the source of the driving transistor TDR (that is, the path between the driving transistor TDR and the light emitting element E) and the gate of the driving transistor TDR.
The selection transistor TS is an N channel type transistor disposed between the data line 14 and the gate of the driving transistor TDR. The gate of the selection transistor TS is connected to the scanning line 12.

  Next, the scanning line driving circuit 34 will be described with reference to FIG. The scanning line driving circuit 34 transfers the Y transfer start pulse SPY with the Y clock signal CLY to generate shift signals SR [1] to SR [m], and the shift signals SR [1] to SR [ m], m first circuits Ua1 to Uam and m second circuits Ub1 to Ubm are provided. The Y clock signal CLY is inverted every horizontal scanning period. The shift signals SR [1] to SR [m] are exclusively active every horizontal scanning period.

  The first circuit Uai in the i-th row includes an AND circuit 341 and a first level shifter LS1. The AND circuit 341 uses the first enable signal EN1 to limit the pulse width of the shift signal SR [i]. The first level shifter LS1 shifts the level of the output signal of the AND circuit 341 to generate the scanning signal GWR [i].

As shown in FIG. 4, the pixel circuit U is driven by being divided into an initialization period PIN, a compensation period PCP immediately after the initialization period, a holding period Pk immediately after the compensation period PCP, a writing period PWRT, and a light emission period PEL. Is done. Detailed operations in each period will be described later.
The first enable signal EN1 is active in a period (for example, Tx in FIG. 4) from the end of the holding period Pk in an arbitrary horizontal scanning period 1H (unit period) to the start of the holding period Pk in the next horizontal scanning period 1H. It becomes. That is, the active period of the first enable signal EN1 continues in the continuous horizontal scanning period 1H and straddles the timing at which the logic level of the Y clock signal CLY is inverted. In such a first half period Ta of the active period of the first enable signal EN1, the writing period PWRT of a certain horizontal scanning period 1H is specified, and in the second half period Tb, the initialization period PIN and the compensation period of the next horizontal scanning period 1H. A PCP is specified. As a result, the scanning signal GWR [i] becomes active during the initialization period PIN, the compensation period PC, and the writing period PWRT, and becomes inactive during the holding period Pk.
Since various control signals are generated based on the Y clock signal CLY, they are usually processed in units of one horizontal scanning period 1H. In this embodiment, however, the active period extends over two horizontal scanning periods. By using the 1 enable signal EN1, the scanning signal GWR [i] can be generated with a simple configuration.

The second circuit Ubi in the i-th row shown in FIG. 3 includes a NAND circuit 342 and a second level shifter LS2. The NAND circuit 342 uses the second enable signal EN2 to limit the pulse width of the shift signal SR [i]. The second level shifter LS1 shifts the level of the output signal of the NAND circuit 342 to generate the power supply potential VEL [i].
As shown in FIG. 4, since the second enable signal EN2 becomes active in the initialization period PIN in an arbitrary horizontal scanning period 1H, the NAND circuit inverts the logical product of the second enable signal EN2 and the shift signal SR [i]. By performing the calculation at 342, the power supply potential VEL [i] that becomes a low potential in the initialization period PIN and becomes a high potential in other periods can be generated.
In the present embodiment, the common shift register 340 is used to generate the power supply potentials VEL [1] to VEL [m] and the scanning signals GWR [1] to GWR [m]. This simplifies the configuration, reduces power consumption, and further reduces the size of the device.

  Next, a specific operation (driving method) of the pixel circuit U will be described. Hereinafter, the operation of the pixel circuit U in the i-th row and the j-th column will be described by dividing it into an initialization period PIN, a compensation period PCP, a holding period Pk, a writing period PWRT, and a light emitting period PEL. The operation of the pixel circuit U is the same.

(A) Initialization period PIN
As shown in FIG. 4, the scanning line driving circuit 34 sets the scanning signal GWR [i] to a high level in the initialization period PIN. Therefore, as shown in FIG. 5, the selection transistor TS is turned on. At this time, the reference potential Vo is supplied via the data line 14. As a result, the source potential VS of the drive transistor TDR is reset to a potential sufficiently lower than the reference potential Vo. Specifically, the source potential VS is set so that the gate-source voltage VGS of the driving transistor TDR is larger than the threshold voltage VTH. Accordingly, the drive transistor TDR is turned on, and the source potential VS of the drive transistor TDR is set to the first potential VEL_L. That is, the voltage VGS between the gate and the source of the driving transistor TDR (the voltage between both ends of the capacitive element CST) is initialized to the difference voltage (| VEL_L−Vo |) between the first potential VEL_L and the reference potential Vo.

  Further, the first potential VEL_L has a potential difference (that is, a voltage between both ends of the capacitor CE) between the first potential VEL_L and the lower potential VCT supplied to the power line 21 sufficiently to the light emission threshold voltage VTH_OLED of the light emitting element E. The value is set to be lower. Therefore, in the initialization period PIN, the drive transistor TDR is turned on, and the light emitting element E is turned off (non-light emitting state).

(B) Compensation period PCP
As shown in FIG. 4, when the compensation period PCP starts, the scanning line driving circuit 34 sets the power supply potential VEL [i] output to the power supply line 20 in the i-th row to the second potential VEL_H. As a result, as shown in FIG. 6, the current from the i-th feeder line 20 flows through the drive transistor TDR, and the source potential VS of the drive transistor TDR starts to rise. At this time, since the gate potential VG of the drive transistor TDR is maintained at the reference potential Vo, the gate-source voltage VGS of the drive transistor TDR gradually decreases and gradually approaches the threshold voltage VTH. That is, in the compensation period PCP, a compensation operation is performed in which the voltage VGS between the gate and source of the drive transistor TDR gradually approaches the threshold voltage VTH.

  At the end of the compensation period PCP, the gate-source voltage of the drive transistor TDR is substantially equal to the threshold voltage VTH of the drive transistor TDR. Is also set to a potential Vo-VTH which is lower by the threshold voltage VTH. In the present embodiment, this potential Vo−VTH is set to a value such that the voltage across the capacitor CE is sufficiently lower than the light emission threshold voltage VTH_OLED of the light emitting element E. Therefore, in the compensation period PCP, the driving transistor TDR and the light emitting element E are in the off state (non-light emitting state).

(C) Retention period Pk
As shown in FIG. 4, when the holding period Pk starts, the scanning line driving circuit 34 sets the scanning signal GWR [i] to a high level. Therefore, as shown in FIG. 7, the selection transistor TS is turned off. As a result, the gate of the driving transistor TDR is in an electrically floating state. The voltage between both ends of the capacitive element CST (the voltage VGS between the gate and the source of the driving transistor TDR) maintains the voltage at the end point of the compensation period PCP.

(D) Write period PWRT
As shown in FIG. 4, when the writing period PWRT is started, the scanning line driving circuit 34 sets the scanning signal GWR [i] to a high level. Therefore, as shown in FIG. 8, since the selection transistor TS is turned on, the gate of the driving transistor TDR is conducted to the data line 14. As a result, the data potential VX [j] is supplied to the gate of the drive transistor TDR. At this time, the scanning line driving circuit 34 supplies the power supply potential VEL [i] output to the power supply line 20 in the i-th row so that the current IDS corresponding to the data potential VX [j] flows through the driving transistor TDR. Is set to the third potential VEL_H. Since the current IDS corresponding to the data potential VX [j] flows through the drive transistor TDR, the source potential VS of the drive transistor TDR rises with time, so that the voltage VGS between the gate and source of the drive transistor TDR is over time. Decrease.

Here, the greater the mobility μ of the drive transistor TDR, the greater the amount of current IDS flowing through the drive transistor TDR, and the greater the increase in the source potential VS. On the contrary, the smaller the mobility μ is, the smaller the amount of current IDS flowing through the drive transistor TDR is, and the amount of increase in the source potential VS is smaller than when the mobility μ is large. That is, as the mobility μ increases, the decrease amount (negative feedback amount) of the gate-source voltage VGS of the drive transistor TDR increases. On the other hand, as the mobility μ decreases, the decrease amount of voltage VGS (negative feedback amount) decreases. Become. As a result, variations in mobility μ for each pixel circuit U are compensated. Such a mobility compensation operation is performed over the entire period of the write period PWRT. At the end point of the write period PWRT, the voltage between both ends of the capacitive element CST is the characteristic of the data potential VX [j] and the drive transistor TDR ( It is set to a value reflecting the threshold voltage VTH and mobility μ).
Note that the source potential VS of the driving transistor TDR at the end point of the writing period PWRT is set to a value such that the voltage across the capacitor CE is sufficiently lower than the light emission threshold voltage VTH_OLED of the light emitting element E. Therefore, in the writing period PWRT, the driving transistor TDR is turned on, and the light emitting element E is turned off (non-light emitting state).

(E) Light emission period PEL
As shown in FIG. 4, when the light emission period PEL starts, the scanning line driving circuit 34 sets the scanning signal GWR [i] to a low level. Therefore, as shown in FIG. 8, the selection transistor TS shifts to the off state, and the gate of the drive transistor TDR is in an electrically floating state. At this time, the voltage between both ends of the capacitive element CST (the voltage VGS between the gate and the source of the drive transistor TDR) is maintained at the voltage at the end point of the write period PWRT, so that the current IDS corresponding to the voltage is the drive transistor. The potential VS of the source rises with time through TDR.

  At this time, since the gate of the driving transistor TDR is in an electrically floating state, the gate potential VG of the driving transistor TDR rises in conjunction with the source potential VS. Then, the capacitance CE associated with the light emitting element E is maintained while the voltage VGS between the gate and the source of the driving transistor TDR (the voltage between both ends of the capacitance element CST) is maintained at the voltage set at the end point of the writing period PWRT. Is gradually increased (the potential VS of the source of the driving transistor TDR). When the voltage across the capacitor CE reaches the light emission threshold voltage VTH_OLED of the light emitting element E, the current IDS flows through the light emitting element E as the drive current IDR. The light emitting element E emits light with a luminance corresponding to the amount of drive current IDR.

<B: Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
The conductivity type of each transistor (driving transistor TDR, selection transistor TS) constituting the pixel circuit U is arbitrary. For example, a configuration in which the driving transistor TDR is a P-channel type is also employed. When the P-channel type driving transistor TDR is adopted, the voltage relationship (high and low) is reversed as compared with the case where the N-channel type driving transistor TDR is adopted, but the essential operation is the same as in FIG. Detailed description of the operation is omitted.
(2) Modification 2
In the above-described embodiment, the scanning line 12 and the power supply line 20 are driven by the single scanning line driving circuit 34. However, the scanning line 12 and the power supply line 20 may be driven by separate circuits.

(3) Modification 3
The light emitting element E may be an OLED element, an inorganic light emitting diode, or an LED (Light Emitting Diode). In short, all elements that emit light in response to the supply of electric energy (application of electric field or supply of current) can be used as the light-emitting elements of the present invention.

<C: Application example>
Next, an electronic apparatus using the light emitting device according to the present invention will be described. FIG. 10 is a perspective view illustrating a configuration of a mobile personal computer that employs the light emitting device 1 according to the embodiment described above as a display device. The personal computer 2000 includes a light emitting device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the light-emitting device 1 uses an OLED element as the light-emitting element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 11 shows a configuration of a mobile phone that employs the light-emitting device 1 according to the embodiment described above as a display device. The cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the light emitting device 1. By operating the scroll button 3002, the screen displayed on the light emitting device 1 is scrolled.

  FIG. 12 shows a configuration of a personal digital assistant (PDA) that employs the light emitting device 1 according to the embodiment described above as a display device. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the light emitting device 1. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device 1.

  Electronic devices to which the light emitting device according to the present invention is applied include digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators, in addition to those shown in FIGS. , Word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

DESCRIPTION OF SYMBOLS 1 ... Light-emitting device, 10 ... Element part, 12 ... Scan line, 14 ... Data line, 20 ... Feed line, 30 ... Drive circuit, 34 ... Scan line drive circuit, 36 ... Data line drive Circuit, 100 ... Light-emitting panel, 200 ... Control circuit, 340 ... Shift register, Ua1-Uam ... First circuit, Ub1-Ubm ... Second circuit, EN1 ... First enable signal, EN2 ... First 2 enable signal, CST ... capacitance element, CE ... capacitance, E ... light emitting element, GWR ... scanning signal, TDR ... drive transistor, TS ... selection transistor, VEL ... power supply potential, U ... pixel circuit . Shift signal SR [1] to SR [m]

Claims (5)

A plurality of scan lines each extending in a first direction;
A plurality of feed lines provided in one-to-one correspondence with the plurality of scanning lines;
A plurality of data lines each extending in a second direction different from the first direction;
A plurality of pixel circuits arranged corresponding to each intersection of the plurality of scanning lines and the plurality of data lines;
A driving circuit for supplying a scanning signal to each of the plurality of scanning lines;
A control circuit for supplying a first enable signal and a clock signal that is inverted every unit period to the drive circuit;
Each of the plurality of pixel circuits is
A light emitting element;
A drive transistor that is fed from the feed line and supplies a drive current corresponding to a gate potential to the light emitting element;
A capacitive element disposed between a gate and a source of the driving transistor;
A selection transistor disposed between the gate of the driving transistor and a data line corresponding to the pixel circuit;
The drive circuit is
A shift register that outputs a plurality of shift signals that are exclusively active in synchronization with the clock signal;
The shift signals are provided in a one-to-one correspondence with the plurality of shift signals. The shift signals and the first enable signals are supplied, and the shift signals and the first enable signals are activated when the shift signals and the first enable signals are simultaneously activated. A plurality of first circuits for outputting scanning signals,
The unit period includes an initialization period in which a first potential is supplied to the power supply line, a compensation period in which a second potential is supplied to the power supply line, a holding period, and a writing in which a data signal is supplied to the data line. Including
The control circuit generates the first enable signal so as to be active in a period from the end of the holding period of an arbitrary unit period to the start of the holding period of the next unit period.
An electro-optical device. The control circuit supplies a second enable signal that is active in the initialization period and inactive in other periods to the drive circuit,
The drive circuit is provided in a one-to-one correspondence with the plurality of shift signals, the shift signal and the second enable signal are supplied, and the shift signal and the second enable signal are simultaneously activated. A plurality of second circuits that output the first potential to the power supply line and output the second potential to the power supply line in other periods.
The electro-optical device according to claim 1. The first circuit includes:
A first logic circuit that calculates a logical product of the shift signal and the first enable signal;
A first level shifter for shifting the signal level of the output signal of the first logic circuit and outputting the scanning signal;
The second circuit includes:
A second logic circuit that calculates an inversion of a logical product of the shift signal and the second enable signal;
A second level shifter that shifts a signal level of an output signal of the second logic circuit and outputs a power supply potential that is the first potential or the second potential.
The electro-optical device according to claim 1 or 2.   The driving circuit supplies a reference potential at which the driving transistor is turned on to the plurality of data lines in the initialization period, and data corresponding to gradations to be displayed on the plurality of data lines in the writing period. The electro-optical device according to claim 1, further comprising a data line driving circuit that supplies a potential. An electronic apparatus comprising the electro-optical device according to claim 1.

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