JP2012124779A - Signal amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal amplification circuit that can suppress changes in gain due to manufacturing variations of an OTA for outputting a current proportional to an input voltage and due to changes in ambient temperature.SOLUTION: The signal amplification circuit includes: a first integrator 10 having a first OTA 1 for receiving an input voltage Vin and a first capacitor C1; a first analog switch SW1 connected in parallel with the first capacitor C1; and an integration time adjustment circuit 3 for adjusting an integration time for the input voltage Vin. The integration time adjustment circuit 3 includes: a second integrator 20 having a second OTA 2 for receiving a first reference voltage Vref1 and a second capacitor C2; a second analog switch SW2 connected in parallel with the second capacitor C2; and a comparator CP2 for comparing an output voltage of the second integrator 20 with a second reference voltage Vref2. A first control signal and a second control signal for controlling the first analog switch SW1 and the second analog switch SW2, respectively, are output on the basis of an output of the comparator CP2.

Description

  The present invention relates to a signal amplifier circuit.

  Conventionally, as a signal amplification circuit that amplifies an input voltage that is an input signal, it is charged by an OTA (Operational Transconductance Amplifier) that is a first voltage-current conversion circuit that outputs a current proportional to the input voltage and an output current of the OTA. There is known an amplification circuit including a capacitor and a reset switch connected in parallel to the capacitor (for example, Patent Document 1). In this amplifier circuit, an integrator is composed of the OTA and the capacitor, and the voltage across the capacitor becomes the output voltage. Note that OTA is characterized by high input impedance and a large voltage-current conversion coefficient.

  Patent Document 1 described above discloses a sensor device including the above-described amplifier circuit. In this sensor device, an output voltage of a sensor unit that converts a physical quantity or a chemical quantity into an electric quantity is used as an input voltage of the amplifier circuit. Yes. The sensor device also includes an A / D conversion circuit that converts the analog output voltage of the amplifier circuit into a digital value and outputs the digital value.

JP 2009-271010 A

  By the way, in the amplifier circuit using the above-mentioned OTA, it is common to try to realize high gain characteristics and low noise performance by setting the integration time in the integrator to a fixed time. However, in the above-described amplifier circuit, the output voltage fluctuates due to a gain change due to manufacturing variations in OTA characteristics and changes in ambient temperature. Note that characteristic variations due to manufacturing variations can be suppressed by performing trimming after manufacturing the amplifier circuit, but gain changes due to changes in ambient temperature are suppressed by trimming after manufacturing the amplifier circuit. I can't.

  The present invention has been made in view of the above-mentioned reasons, and its purpose is signal amplification capable of suppressing a variation in gain of OTA that outputs a current proportional to an input voltage and a change in gain due to a change in ambient temperature. It is to provide a circuit.

  The signal amplifier circuit according to the present invention is a signal amplifier circuit that amplifies an input voltage that is an input signal, and is a first voltage-current converter circuit that outputs a current proportional to the input voltage. A first integrator having a first capacitor charged by an output current of one OTA, a first analog switch connected in parallel to the first capacitor, and turning on and off the first analog switch The integration time adjustment circuit adjusts the integration time of the input voltage by the first integrator, and the integration time adjustment circuit receives the first reference voltage that is a first constant voltage and receives the first reference voltage. A second voltage-current conversion circuit that outputs a current proportional to the reference voltage of the second OTA and a second capacitor that is charged by the output current of the second OTA. A divider, a second analog switch connected in parallel to the second capacitor, and a comparator for comparing the output voltage of the second integrator and a second reference voltage, which is a second constant voltage. And a first control signal for controlling the first analog switch and a second control signal for controlling the second analog switch based on an output of the comparator.

  This signal amplifying circuit preferably includes a frequency divider that divides the output of the comparator into the first control signal.

  In this signal amplifying circuit, an input switching unit that can selectively input the input voltage and the first reference voltage to the first OTA, and an output of the comparator provided after the comparator A PLL serving as an input signal, the first OTA also serves as the second OTA, and the first capacitor also serves as the second capacitor, and the output of the PLL is controlled by the first control. Preferably it is a signal.

  In this signal amplifier circuit, the PLL includes a voltage controlled oscillator, a phase detector that compares the phases of the output of the voltage controlled oscillator and the external input signal and generates an output signal proportional to the phase difference, and the phase A low-pass filter provided on the downstream side of the detector, a third analog switch provided between the low-pass filter and the voltage-controlled oscillator, and the low-pass provided between the third analog switch and the ground. A voltage holding circuit for holding the control voltage of the voltage controlled oscillator output from the filter, a temperature sensor for detecting the temperature of the first OTA, and a control unit for controlling the third analog switch. The control unit turns on and off the third analog switch when the amount of change in temperature detected by the temperature sensor exceeds a predetermined value. It is preferable to hold the newer the control voltage to the voltage holding circuit.

  The signal amplifier circuit preferably includes a reference voltage setting unit capable of setting the first reference voltage and the second reference voltage.

  The signal amplification circuit includes a voltage comparison circuit that compares the output voltage of the first integrator with a third reference voltage, and the output voltage of the first integrator is based on the output of the voltage comparison circuit. It is preferable that the first reference voltage and the second reference voltage are changed so as to be the third reference voltage.

  The signal amplification circuit includes a plurality of the first integrators, and the integration time adjustment circuit includes all the first analogs connected in parallel to the first capacitors of the plurality of first integrators. It is preferable that the on / off of the switch can be controlled simultaneously.

  The signal amplifying circuit includes a plurality of the first integrators, and at least one of the first integrators alternatively selects the input voltage and the first reference voltage for the first OTA. An input switching unit enabling input is connected, and the first OTA of the first integrator to which the input switching unit is connected also serves as the second OTA, and the input switching unit is connected The integration time is obtained by providing the first capacitor of the first integrator also as the second capacitor, and providing the comparator on the rear stage side of the first integrator to which the input switching unit is connected. It is preferable to operate as an adjustment circuit and to be able to simultaneously control on / off of the first analog switch of the other first integrator.

  In the signal amplifying circuit of the present invention, it is possible to suppress variations in gain due to variations in manufacturing of OTA that outputs a current proportional to the input voltage and changes in ambient temperature.

1A is a schematic circuit diagram and FIG. 2B is a main circuit diagram of the signal amplifier circuit according to the first embodiment. It is operation | movement explanatory drawing same as the above. FIG. 6 is a schematic circuit diagram of a signal amplifier circuit according to a second embodiment. It is operation | movement explanatory drawing same as the above. Regarding the signal amplifying circuit of the third embodiment, (a) is a schematic circuit diagram, and (b) is a main part configuration diagram. It is operation | movement explanatory drawing same as the above. It is operation | movement explanatory drawing same as the above. 4A is a schematic circuit diagram, and FIG. 4B is a main part configuration diagram regarding a signal amplifier circuit according to a fourth embodiment. 5A is a schematic circuit diagram, and FIG. 5B is a main circuit diagram of a signal amplifier circuit according to a fifth embodiment. It is a principal part circuit diagram same as the above. It is a principal part circuit diagram same as the above. With respect to the signal amplifier circuit of the sixth embodiment, (a) is a schematic circuit diagram, and (b) is a main circuit diagram. It is a circuit diagram of the voltage comparison circuit in the same as the above. It is operation | movement explanatory drawing same as the above. It is a circuit diagram of the other structural example of the voltage comparison circuit same as the above. It is operation | movement explanatory drawing same as the above. It is a circuit diagram of another structural example of the voltage comparison circuit in the same as the above. FIG. 10 is a circuit diagram of a signal amplifier circuit according to a seventh embodiment. FIG. 10 is a circuit diagram of a signal amplifier circuit according to an eighth embodiment.

(Embodiment 1)
Hereinafter, the signal amplifier circuit of this embodiment will be described with reference to FIGS. 1 and 2.

  The signal amplification circuit of this embodiment is a signal amplification circuit that amplifies an input voltage Vin that is an input signal. The signal amplification circuit includes a first integrator 10. The first integrator 10 includes a first OTA1 that is a first voltage-current conversion circuit that outputs a current proportional to the input voltage Vin, and a first capacitor C1 that is charged by the output current of the first OTA1. And have. The signal amplifier circuit also includes a first integrator 10 having a first analog switch SW1 connected in parallel to the first capacitor C1.

  Examples of the input voltage Vin include an output voltage (voltage signal) of a sensor (physical quantity sensor, chemical quantity sensor, etc.) not shown.

  The first OTA 1 is configured by a folded cascode operational amplifier, the input terminal on the + side is connected to the ground, and the input voltage Vin is input to the input terminal on the − side.

  The first analog switch SW1 is preferably composed of an n-channel MOS transistor, whereby the on-resistance can be reduced and high-speed operation can be achieved as compared with the case where it is composed of a p-channel MOS transistor.

  Each of the first capacitor C1 and the first analog switch SW1 has one end connected to the output end of the first OTA1, and the other end connected to the ground. Here, the first analog switch SW1 constitutes a first reset circuit that resets the output voltage Vout1 of the first integrator 10.

  Therefore, the integration time of the first integrator 10 (hereinafter also referred to as the first integration time) is determined by the length of the off period of the first analog switch SW1. In other words, in the first integrator 10, the length of the off period of the first analog switch SW1 is the first integration time.

  Here, the output voltage Vout1 of the first integrator 10 increases (changes linearly) in proportion to the first integration time and the input voltage Vin. Here, in the signal amplifier circuit, the gain (voltage gain) is determined by the ratio between the output voltage Vout1 of the first integrator 10 and the input voltage Vin, and the gain increases in proportion to the first integration time. That is, the gain of the signal amplifier circuit changes linearly with respect to the first integration time, and the gain increases as the first integration time increases.

  Further, the signal amplifier circuit includes an integration time adjusting circuit 3 that adjusts the first integration time of the input voltage Vin by the first integrator 10 by turning on and off the first analog switch SW1.

  The integration time adjustment circuit 3 receives a first reference voltage Vref1, which is a first constant voltage, and outputs a current proportional to the first reference voltage Vref1, which is a second voltage-current conversion circuit. And a second integrator 20 having a second capacitor C2 charged by the output current of the second OTA2.

  The second OTA 2 is configured by a folded cascode operational amplifier, the + side input terminal is connected to the ground, and the first reference voltage Vref1 is input to the − side input terminal.

  The integration time adjustment circuit 3 includes a second analog switch SW2 connected in parallel to the second capacitor C2, an output voltage Vint of the second integrator 20, and a second reference voltage that is a second constant voltage. A comparator CP2 for comparing with Vref2 is provided.

  The second analog switch SW2 is preferably composed of an n-channel MOS transistor, whereby the on-resistance can be reduced and high-speed operation can be achieved as compared with the case where it is composed of a p-channel MOS transistor.

  Each of the second capacitor C2 and the second analog switch SW2 has one end connected to the output end of the second OTA 2 and the other end connected to the ground. Here, the second analog switch SW2 constitutes a second reset circuit that resets the output voltage Vint of the second integrator 20.

  The output Vout2 of the comparator CP2 becomes L level when the output voltage Vint of the second integrator 20 is equal to or lower than the second reference voltage Vref2, and becomes H level when larger than the second reference voltage Vref2.

  The integration time adjustment circuit 3 turns on the first analog switch SW1 and the second analog switch SW2 only when the output Vout2 of the comparator CP2 is in the H level. On the other hand, the integration time adjusting circuit 3 turns off the first analog switch SW1 and the second analog switch SW2 only when the output Vout2 of the comparator CP2 is in the L level. In short, the integration time adjusting circuit 3 outputs a first control signal for controlling the first analog switch SW1 and a second control signal for controlling the second analog switch SW2 based on the output Vout2 of the comparator CP2. As a result, the integration time adjusting circuit 3 causes the voltage across the first capacitor C1 (that is, the output voltage Vout1 of the first integrator 10) and the voltage across the second capacitor C2 (that is, the second integrator 20). Each output voltage Vint) is reset to 0V (ground level).

  The first reference voltage Vref1 and the second reference voltage Vref2 are preferably generated using the same reference voltage generation circuit.

  In the integration time adjusting circuit 3, the integration time of the second integrator 20 (hereinafter also referred to as a second integration time) is determined by the first reference voltage Vref1 and the second reference voltage Vref2. This point will be described with reference to FIG.

  The waveform of the output voltage Vint of the second integrator 20 is a sawtooth waveform as shown in FIG. That is, the output voltage Vint of the second integrator 20 increases with time when the integration in the second integrator 20 is started, and the slope at this time is caused by the first reference voltage Vref1. Determined. When the output voltage Vint of the second integrator 20 exceeds the second reference voltage Vref2, the output Vout2 of the comparator CP2 becomes H level, the second analog switch SW2 is turned on, and the second integrator 20 is turned on. Output voltage Vint is reset to zero. Then, when the output Vout2 of the comparator CP2 becomes L level, the integration in the second integrator 20 is started again, and the output voltage Vint of the second integrator 20 increases with time. In short, the increase of the output voltage Vint due to the integration in the second integrator 20 and the decrease due to the reset of the output voltage Vint of the second integrator 20 are alternately repeated. In the integration time adjusting circuit 3, the period when the output Vout2 of the comparator CP2 is at the L level is the first integration time and the second integration time, and the period when the output Vout2 of the comparator CP2 is at the L level is the first reference voltage. It is determined by Vref1 and the second reference voltage Vref2. Therefore, the first integration time and the second integration time can be changed by appropriately changing the first reference voltage Vref1 and the second reference voltage Vref2. The first integration time and the second integration time change linearly with respect to each of the first reference voltage Vref1 and the second reference voltage Vref2.

  The first OTA 1 and the second OTA 2 have the same configuration and are designed to have the same characteristics (equal electrical characteristics and temperature characteristics), and are preferably manufactured at the same time. Further, both the first OTA1 and the second OTA2 employ a folded cascode operational amplifier, but the present invention is not limited to this. For example, both may adopt a telescopic cathode operational amplifier. Both of them may adopt a current mirror type operational amplifier.

  As described above, the signal amplifying circuit of the present embodiment has the first integrator 10 having the first OTA1 and the first capacitor C1 and the integration time of the input voltage Vin by the first integrator 10. And an integration time adjustment circuit 3 for adjustment. In the signal amplifier circuit according to the present embodiment, the integration time adjusting circuit 3 receives the first reference voltage Vref1 and outputs a current proportional to the first reference voltage Vref1, and the second OTA2 and the second OTA2 The second integrator 20 having the second capacitor C2 charged by the output current of the second capacitor C2, the second analog switch SW2 connected in parallel to the second capacitor C2, and the output voltage Vint of the second integrator 20 And a second reference voltage Vref2, and a first control signal for controlling the first analog switch SW1 and a second analog switch SW2 for controlling the first analog switch SW2 based on the output of the comparator CP2. The control signal is output. Thus, in the signal processing circuit according to the present embodiment, the manufacturing variation of the first OTA 1 that outputs a current proportional to the input voltage Vin and the change in the gain due to the change in the ambient temperature without performing the conventional trimming after the manufacturing. Can be suppressed.

(Embodiment 2)
The basic configuration of the signal amplifying circuit of this embodiment is substantially the same as that of the first embodiment. As shown in FIG. 3, the output Vout2 of the comparator CP2 (see FIG. 1B) of the integration time adjusting circuit 3 is divided. The difference is that a frequency divider 4 is used as the first control signal. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  The frequency divider 4 is a circuit that converts the frequency of the output Vout2 of the comparator CP2 into 1 / N (N is a natural number), and uses, for example, a toggle type flip-flop circuit (T-FF). Can be configured. In short, the frequency divider 4 can be configured by a digital circuit that can be reduced in area and easily reduced in power consumption as compared with the second capacitor C2 that is an analog circuit element.

  Here, when the output voltage Vint of the second integrator 20 has a waveform as shown in FIG. 4A and the output Vout2 of the comparator CP2 has a waveform as shown in FIG. 4B, for example, N = 2 Then, the output Vdiv of the frequency divider 4 serving as the first control signal has a waveform as shown in FIG.

  In the signal amplifier circuit of the present embodiment, since the frequency divider 4 is provided, the integration time is changed without changing the first integration time (in other words, without changing the gain design of the signal amplifier circuit). The capacity of the second capacitor C2 in the adjustment circuit 3 can be reduced. As a result, in the signal processing circuit of the present embodiment, it is possible to reduce the area and power consumption when integrated on one chip.

(Embodiment 3)
The basic configuration of the signal amplifier circuit of the present embodiment is substantially the same as that of the first embodiment. As shown in FIG. 5A, the input voltage Vin and the first reference voltage Vref1 are selected for the first OTA1. The difference is that the input switching unit 5 that enables automatic input is provided. In addition, the signal amplification circuit according to the present embodiment includes a phase locked loop (PLL) 6 that is provided at the subsequent stage of the comparator CP2 and uses the output Vout2 of the comparator CP2 as an external input signal, and the first OTA1 is the second OTA1. The first capacitor C1 also serves as the second capacitor C2 and serves as the first control signal for the first analog switch SW1. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  The input switching unit 5 includes an analog switch SW51 provided between an input terminal (not shown) to which the input voltage Vin is input and the first OTA1, and a first reference to which the first reference voltage Vref1 is input. An analog switch 52 provided between a voltage terminal (not shown) and the first OTA 1 is provided. In short, the input switching unit 5 includes two analog switches 51 and 52. Each analog switch 51, 52 of the input switching unit 5 is preferably composed of an n-channel MOS transistor, so that on-resistance can be reduced and high-speed operation is possible compared to the case where it is composed of a p-channel MOS transistor. It becomes.

  The PLL 6 is a circuit having a function of obtaining phase synchronization between an external input signal and a local reference signal. As shown in FIG. 5B, a voltage controlled oscillator (Voltage Controlled) which is a reference signal source for outputting the reference signal. Oscillator (VCO) 61 is provided. The PLL 6 compares the phase of the output of the VCO 61 with an external input signal and generates an output signal proportional to the phase difference, and removes the high-frequency component of the output signal of the PD 62. A low pass filter (LPF) 63 that outputs only the low frequency component as the control voltage of the VCO 61 is provided. The VCO 61 changes the output frequency in a direction that reduces the phase difference from the external input signal. Therefore, the control voltage output from the LPF 63 corresponds to the frequency of the external input signal input to the PD 62. The LPF 63 of the PLL 6 is also called a loop filter, and the characteristics of the LPF 63 are important elements that determine the synchronization characteristics and response characteristics of the PLL 6. Here, the LPF 63 preferably sets circuit constants based on the stability of the PLL 6 and the convergence time of the output of the LPF 63.

  The PLL 6 includes a third analog switch SW3 provided between the LPF 63 and the VCO 61, and a voltage holding circuit 64 provided between the third analog switch SW3 and the ground for holding a control voltage. Yes. The third analog switch SW3 is preferably composed of an n-channel MOS transistor, which can reduce the on-resistance and enable high-speed operation as compared with the case where the third analog switch SW3 is composed of a p-channel MOS transistor. Further, the voltage holding circuit 64 is constituted by a third capacitor. In short, the third analog switch SW3 and the voltage holding circuit 64 have the same function as the sample hold circuit.

  In addition, the signal amplification circuit according to the present embodiment includes an output switching unit 7 that enables one of a signal output terminal (not shown) and the comparator CP2 to be alternatively connected to the output terminal of the first integrator 10. Yes. The output switching unit 7 is provided between the analog switch 71 provided between the output terminal of the first integrator 10 and the signal output terminal, and between the output terminal of the first integrator 10 and the comparator CP2. The analog switch 72 is provided. Each of the analog switches 71 and 72 of the output switching unit 7 is preferably configured by an n-channel MOS transistor, thereby reducing on-resistance and enabling high-speed operation as compared with the case of configuring by an p-channel MOS transistor. It becomes.

  In addition, the signal amplifier circuit of this embodiment includes a control unit 8 that controls the input switching unit 5, the output switching unit 7, and the third analog switch SW3. The control unit 8 may be configured by a microcomputer equipped with an appropriate program, or may be configured by a combination of a timing control circuit and a plurality of circuits each designed to realize a desired function. Also good.

  As shown in FIG. 6, the control unit 8 operates the first OTA1, the first mode in which the first capacitor C1 is operated as a component of the first integrator 10, the first OTA1 as shown in FIG. The second mode in which the first capacitor C1 is operated as a component of the second integrator 20 (that is, the second mode in which the first OTA1 is operated as the second OTA2 and the first capacitor C1 is operated as the second capacitor C2). Mode), the input switching unit 5, the output switching unit 7 and the third analog switch SW3 are controlled.

  In the first mode, as shown in FIGS. 6A and 6B, the analog switch 51 of the input switching unit 5 is on, the analog switch 71 of the output switching unit 7 is on, and the third analog switch SW3 of the PLL 6 is on. Turn off. Therefore, in the first mode, the input voltage Vin is input to the first OTA1, and the output voltage Vout1 proportional to the input voltage Vin and the first integration time is output from the first integrator 10. The first integration time at this time is determined by the output of the PLL 6. That is, in the first mode, when the first analog switch SW1 is turned on / off based on the output of the PLL 6 and the first analog switch SW1 is turned on, the output voltage Vout1 (first output of the first integrator 10) The voltage across the capacitor C1) is reset to 0V. Therefore, in the first mode, the output of the PLL 6 becomes a first control signal for controlling on / off of the first analog switch SW1.

  In the second mode, as shown in FIGS. 7A and 7B, the analog switch 52 of the input switching unit 5 is turned on, the analog switch 72 of the output switching unit 7 is turned on, and the third analog switch SW3 of the PLL 6 is turned on. Turn on. Therefore, in the second mode, the first reference voltage Vref1 is input to the second OTA2, the output of the second integrator 20 is input to the comparator CP2, and the control voltage is applied from the LPF 63 to the VCO 61 in the PLL6. . In the second mode, the second analog switch SW2 is turned on / off based on the output of the PLL 6, and the voltage across the second capacitor C2 is reset to 0 when the second analog switch SW2 is on. Therefore, in the second mode, the output of the PLL 6 becomes a second control signal for controlling on / off of the second analog switch SW2.

  The control unit 8 controls the input switching unit 5, the output switching unit 7, and the third analog switch SW3 so that the first mode and the second mode are periodically switched.

  In the signal amplifier circuit of the present embodiment described above, the first OTA1 also serves as the second OTA2, and the first capacitor C1 also serves as the second capacitor C2. Therefore, the area can be reduced. It becomes.

  Further, in the signal amplifier circuit of the present embodiment, even if the characteristic of the first OTA1 changes, the first integration time is determined by the output of the PLL 6 based on the control voltage changed by the change in the characteristic of the first OTA1. (That is, since the first integration time is readjusted based on the change in the characteristics of the first OTA 1), it is possible to more reliably suppress fluctuations in gain.

(Embodiment 4)
The basic configuration of the signal amplifying circuit of the present embodiment is substantially the same as that of the third embodiment. As shown in FIG. 8, the signal amplifying circuit includes a temperature sensor 9 that detects the temperature of the first OTA 1. Based on the output of the temperature sensor 9, the input switching unit 5, the output switching unit 7 and the third analog switch SW3 are controlled. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 3, and description is abbreviate | omitted.

  What is necessary is just to comprise the temperature sensor 9 with a thermistor etc., for example. The control unit 8 normally controls the input switching unit 5, the output switching unit 7 and the third analog switch SW3 in the first mode, and the amount of change in the temperature detected by the temperature sensor 8 is a predetermined value (for example, 2 to 10 ° C.). ), The third analog switch SW3 is turned on / off in the second mode to hold the new control voltage in the voltage holding circuit 64, and then the control returns to the first mode.

  Thus, in the signal amplifier circuit of the present embodiment, when the amount of change in the temperature of the first OTA 1 exceeds a predetermined value, the first integration time is determined by the output of the PLL 6 based on the new control voltage (that is, the first The first integration time is readjusted based on the change in the characteristics of the first OTA 1), so that the gain varies due to the temperature variation of the first OTA 1 more reliably than in the third embodiment. Can be suppressed.

(Embodiment 5)
The basic configuration of the signal amplifier circuit of the present embodiment shown in FIG. 9A is substantially the same as that of the first embodiment. As shown in FIG. 9B, the first reference voltage Vref1 and the second reference voltage. The difference is that a reference voltage setting unit (reference voltage setting circuit) 15 capable of setting Vref2 is provided. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

For example, as shown in FIG. 10A, the reference voltage setting unit 15 sets the potential at the connection point between the resistor R1 and the variable resistor VR1 connected in series as the first reference voltage Vref1, and FIG. As shown in FIG. 2, the potential of the connection point between the resistor R2 and the variable resistor VR2 connected in series can be set to the second reference voltage Vref2. The series circuit of the resistor R1 and the variable resistor VR1 and the series circuit of the resistor R2 and the variable resistor VR2 may be connected between both ends of the DC power source _{VDD having} a constant voltage (for example, 5V).

  When the reference voltage setting unit 15 has the configuration shown in FIG. 10, the first reference voltage Vref1 can be set to an arbitrary value by changing the resistance value of the variable resistor VR1. By changing the resistance value of the resistor VR2, the second reference voltage Vref2 can be set to an arbitrary value. In short, in this case, each reference voltage Vref1, Vref2 is made independent by a user or the like manually operating each operation unit (not shown) of each variable resistor VR1, VR2 in the reference voltage setting unit 15. Can be set to any value.

  As shown in FIG. 11, the reference voltage setting unit 15 includes a first D / A converter DAC1 that converts a digital first set value into an analog first reference voltage Vref1, and a digital second set value. A configuration including a second D / A converter DAC2 for converting the set value into the analog second reference voltage Vref2 may be employed. In this case, the first reference voltage Vref1 can be set to an arbitrary value by changing the first set value, and the second reference voltage Vref2 can be set by changing the second set value. An arbitrary value can be set. The first set value and the second set value may be given to the reference voltage setting unit 15 from an external computer (such as a microcomputer) equipped with an appropriate program, for example.

  Since the signal amplifying circuit according to the present embodiment includes the reference voltage setting unit 15, the first reference voltage Vref1 and the second reference voltage Vref2 can be set separately, so that the integration time of the input voltage Vin Can be set to an arbitrary value, and the gain can be set to an arbitrary value.

  By the way, the configuration of the reference voltage setting unit 15 may be a configuration other than that shown in FIGS. Further, the reference voltage setting unit 15 is not limited to the present embodiment, and may be provided in the signal amplifier circuits of other embodiments.

(Embodiment 6)
The basic configuration of the signal amplifier circuit of the present embodiment is substantially the same as that of the first embodiment. As shown in FIG. 12, the voltage comparison for comparing the output voltage Vout1 of the first integrator 10 with the third reference voltage Vref3. The circuit 16 includes a first reference voltage Vref1 and a second reference voltage Vref2 so that the output voltage Vout1 of the first integrator 10 becomes the third reference voltage Vref3 based on the output of the voltage comparison circuit 16. The point to change is different. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  As shown in FIG. 13, the voltage comparison circuit 16 includes a comparator CP3 that compares the output voltage Vout1 of the first integrator 10 with a third reference voltage Vref3, and an output of the comparator CP3 that is provided on the rear side of the comparator CP3. Are integrated, and an analog switch SW16 provided between the comparator CP3 and the third integrator 30 is provided.

  The third integrator 30 includes an operational amplifier OP3, a resistor (input resistance) R3 is connected to the inverting input terminal of the operational amplifier OP3, and a capacitor C3 between the inverting input terminal and the output terminal of the operational amplifier OP1. Is connected. Here, in the third integrator 30, the non-inverting input terminal is grounded so that the potential of the non-inverting input terminal of the operational amplifier OP3 is 0V. In short, the third integrator 30 has a configuration of an inverting integrator using the operational amplifier OP3, the resistor R3, and the capacitor C3, and has a series circuit of the resistor R3 and the capacitor C3.

  The analog switch SW16 of the voltage comparison circuit 16 is turned on / off by the output of the integration time adjustment circuit 3.

  In the signal amplifying circuit of the present embodiment, the output Vcp of the comparator CP3 is integrated by the third integrator 30 while the analog switch SW16 of the voltage comparison circuit 16 is on. Then, the voltage comparison circuit 16 changes the first reference voltage Vref1 and the second reference voltage Vref2 based on the output of the third integrator 30. Specifically, when the analog switch SW16 is on and the output Vcp of the comparator CP3 input to the third integrator 30 is at the L level, the first reference voltage Vref1 is increased by a first fixed amount while the first reference voltage Vref1 is increased. The reference voltage Vref2 of 2 is decreased by a second fixed amount. When the analog switch SW16 is on and the output Vcp of the comparator CP3 input to the third integrator 30 is at the H level, the first reference voltage Vref1 is decreased by a first fixed amount while the second reference is made. The voltage Vref2 is increased by a second fixed amount. That is, the first reference voltage Vref1 and the second reference voltage Vref2 have opposite directions of change, and the first reference voltage Vref1 and the second reference voltage Vref2 are output from the comparator CP3 of the voltage comparison circuit 16. As Vcp is reversed, the direction of change is reversed. The first constant voltage generation circuit (not shown) that outputs the first reference voltage Vref1 is variable in output, and changes the first reference voltage Vref1 as described above based on the output Vcp of the comparator CP3. Anything can be used. The second constant voltage generation circuit (not shown) that outputs the second reference voltage Vref2 is variable in output, and changes the second reference voltage Vref2 as described above based on the output Vcp of the comparator CP3. Anything can be used.

  The operation of the voltage comparison circuit 16 described above is summarized as shown in FIG. 14A shows the output voltage Vout1 of the first integrator 10 and the third reference voltage Vref3 in FIG. 14A, FIG. 14B shows the output Vcp of the comparator CP3 in the voltage comparison circuit 16, and FIG. ) Shows on / off of the analog switch SW16 of the voltage comparison circuit 16, (d) shows the first reference voltage Vref1, and (e) shows the second reference voltage Vref2. Each horizontal axis in FIGS. 14A to 14E represents time.

  Therefore, the signal amplification circuit of the present embodiment includes the voltage comparison circuit 16 that compares the output voltage Vout1 of the first integrator 10 with the third reference voltage Vref3. Since the first reference voltage Vref1 and the second reference voltage Vref2 are changed so that the output voltage Vout1 of the integrator 10 becomes the third reference voltage Vref3, the integration time of the first integrator 10 is adjusted. The gain of the first integrator 10 is adjusted.

  The voltage comparison circuit 16 is not limited to the circuit configuration shown in FIG. 13, and may be a circuit configuration as shown in FIG. The basic configuration of the voltage comparison circuit 16 shown in FIG. 15 is substantially the same as that of FIG. 13, and instead of the comparator CP3, the output voltage Vout1 of the first integrator 10 is compared with the third reference voltage Vref3. The only difference is that an error amplifier EA1 for amplifying the difference error signal is provided.

In the voltage comparison circuit 16 having the configuration shown in FIG. 15, the output Vam of the error amplifier EA1 is integrated by the third integrator 30 while the analog switch SW16 is on. Then, the voltage comparison circuit 16 changes the first reference voltage Vref1 and the second reference voltage Vref2 based on the output of the third integrator 30. Specifically, when the analog switch SW16 is on and the output Vam of the error amplifier EA1 input to the third integrator 30 is a negative value, the first reference voltage Vref1 is set to the absolute value of the output Vam of the error amplifier EA1. While the second reference voltage Vref2 is decreased by a variation corresponding to the absolute value of the output Vam of the error amplifier EA1. When the analog switch SW16 is on and the output Vam of the error amplifier EA1 input to the third integrator 30 is a positive value, the first reference voltage Vref1 corresponds to the absolute value of the output Vam of the error amplifier EA1. While decreasing by the amount of change, the second reference voltage Vref2 is increased by the amount of change corresponding to the absolute value of the output Vam of the error amplifier EA1. That is, the first reference voltage Vref1 and the second reference voltage Vref2 have opposite directions of change, and the first reference voltage Vref1 and the second reference voltage Vref2 are generated by the error amplifier EA1 of the voltage comparison circuit 16. The direction of change is reversed as the polarity of the output Vam is reversed. The first constant voltage generation circuit (not shown) that outputs the first reference voltage Vref1 is variable in output, and the first reference voltage Vref1 is set based on the output Vam of the error amplifier EA1 as described above. Anything can be used. The second constant voltage generation circuit (not shown) that outputs the second reference voltage Vref2 is variable in output, and the second reference voltage Vref2 is set based on the output Vam of the error amplifier EA1 as described above. Anything can be used.
The operation of the voltage comparison circuit 16 is summarized as shown in FIG. 16A shows the output voltage Vout1 of the first integrator 10 and the third reference voltage Vref3 in FIG. 16A, FIG. 16B shows the output Vam of the error amplifier EA1 of the voltage comparison circuit 16, and FIG. (c) shows on / off of the analog switch SW16 of the voltage comparison circuit 16, (d) shows the first reference voltage Vref1, and (e) shows the second reference voltage Vref2. Each horizontal axis of Drawing 16 (a)-(e) is time. In the voltage comparison circuit 16 using the error amplifier EA1 as shown in FIG. 15, the output voltage Vout1 of the first integrator 10 is reduced for a shorter time compared to the voltage comparison circuit 16 using the comparator CP3 as shown in FIG. Thus, it is possible to converge to the third reference voltage Vref3.

  In addition, as shown in FIG. 17, the voltage comparison circuit 16 converts the output voltage Vout1 of the first integrator 10 from analog to digital, and the third reference voltage Vref3 to analog. A second A / D converter 162 for digital conversion, a first digital value output from the first A / D converter 161, and a second output from the second A / D converter 162. An operation comprising a digital circuit that calculates an error from the digital value and determines a third digital value corresponding to the amount of change between the first reference voltage Vref1 and the second reference voltage Vref2 based on the error. Unit 163 and a D / A converter 164 that outputs the third digital value output from arithmetic unit 163 after digital-to-analog conversion. In this case, the output voltage Vout1 of the first integrator 10 can be matched with the third reference voltage Vref3 even if the number of comparisons in the voltage comparison circuit 16 is one.

(Embodiment 7)
The basic configuration of the signal amplifying circuit of the present embodiment is substantially the same as that of the first embodiment, and as shown in FIG. 18, a plurality of first integrators 10 are provided, and the integration time adjusting circuit 3 includes the plurality of first amplifiers. The difference is that ON / OFF of all the first analog switches SW1 connected in parallel to the first capacitors C1 of the respective integrators 10 can be simultaneously controlled. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  In the signal amplifying circuit of the present embodiment, the integration time of each of a plurality (six in the illustrated example) of the first integrators 10 can be adjusted by the single integration time adjusting circuit 3. In the configuration including the integrator 10, the area can be reduced and the power consumption can be reduced.

(Embodiment 8)
The basic configuration of the signal amplifier circuit of the present embodiment is substantially the same as that of the first embodiment. As shown in FIG. 19, six first integrators 10 are provided, and two of the first integrators 10 are included. Similarly to the third embodiment, the input switching unit 5 is provided on the front stage side, and the output switching unit 7 is provided on the rear stage side, and the two first integrators 10 are connected to the first of the integration time adjusting circuit 3. The difference is that the second integrator 20 is also used. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, 3, and description is abbreviate | omitted.

  The two first integrators 10 described above are connected to the input switching unit 5 that allows the input voltage Vin and the first reference voltage Vref1 to be alternatively input to the first OTA1. The first OTA1 of the first integrator 10 to which 5 is connected also serves as the second OTA2, and the first capacitor C1 of the first integrator 10 to which the input switching unit 5 is connected is the second capacitor. C2 (see FIGS. 1 and 5) can also be operated as the integration time adjustment circuit 3 by providing the comparator CP2 on the rear stage side of the first integrator 10 to which the input switching unit 5 is connected. ON / OFF of the first analog switch SW1 of the first integrator 10 can be controlled simultaneously. Note that the number of first integrators 10 is not limited to six, and may be any number. Moreover, the number of the 1st integrators 10 which connect the input switching part 5 is not restricted to two, What is necessary is just at least one. However, it is assumed that the number of first integrators 10 connected to the input switching unit 5 is smaller than the total number of first integrators 10.

  Therefore, in the signal amplifier circuit according to the present embodiment, in the configuration including the plurality of first integrators 10, it is not necessary to provide the integration time adjusting circuit 3 for each first integrator 10, and the integration time adjustment is performed. Since a part of the circuit 3 is shared by the first integrator 10, it is possible to reduce the area and power consumption. In the present embodiment, the PLL 6 (see FIG. 5) described in the third embodiment may be provided.

1 First OTA
2 Second OTA
DESCRIPTION OF SYMBOLS 3 Integration time adjustment circuit 4 Frequency divider 5 Input switching part 6 Phase synchronous loop 7 Output switching part 8 Control part 9 Temperature sensor 10 1st integrator 15 Reference voltage setting part 16 Voltage comparison circuit 20 2nd integrator 61 Voltage Control oscillator 62 Phase detector 63 Low pass filter 64 Voltage holding circuit C1 First capacitor C2 Second capacitor CP2 Comparator SW1 First analog switch SW2 Second analog switch SW3 Third analog switch Vin Input voltage Vref1 First Reference voltage Vref2 Second reference voltage Vref3 Third reference voltage

Claims (8)

  A signal amplification circuit that amplifies an input voltage that is an input signal, and is charged by the first OTA that is a first voltage-current conversion circuit that outputs a current proportional to the input voltage and the output current of the first OTA. A first integrator having a first capacitor, a first analog switch connected in parallel to the first capacitor, and turning on and off the first analog switch. An integration time adjustment circuit for adjusting the integration time of the input voltage, and the integration time adjustment circuit receives a first reference voltage, which is a first constant voltage, and inputs a current proportional to the first reference voltage. A second integrator having a second OTA that is a second voltage-to-current converter to be output and a second capacitor that is charged by the output current of the second OTA; A second analog switch connected in parallel to the sensor, and a comparator for comparing the output voltage of the second integrator and a second reference voltage, which is a second constant voltage, based on the output of the comparator And outputting a first control signal for controlling the first analog switch and a second control signal for controlling the second analog switch.   2. The signal amplifying circuit according to claim 1, further comprising a frequency divider that divides the output of the comparator to obtain the first control signal.   An input switching unit that can selectively input the input voltage and the first reference voltage to the first OTA; a PLL that is provided at a subsequent stage of the comparator and that uses the output of the comparator as an external input signal; The first OTA also serves as the second OTA, the first capacitor serves also as the second capacitor, and the output of the PLL is used as the first control signal. The signal processing circuit according to claim 1.   The PLL includes a voltage-controlled oscillator, a phase detector that compares the phases of the output of the voltage-controlled oscillator and the external input signal and generates an output signal proportional to the phase difference, and a downstream side of the phase detector. A low-pass filter provided; a third analog switch provided between the low-pass filter and the voltage-controlled oscillator; and the third analog switch provided between the third analog switch and the ground and output from the low-pass filter. A voltage holding circuit for holding a control voltage of the voltage controlled oscillator, a temperature sensor for detecting the temperature of the first OTA, and a control unit for controlling the third analog switch, wherein the control unit includes: When the amount of change in the temperature detected by the temperature sensor exceeds a predetermined value, a new control voltage is generated by turning on and off the third analog switch. The signal processing circuit according to claim 3, characterized in that to hold the serial voltage holding circuit.   5. The signal processing circuit according to claim 1, further comprising a reference voltage setting unit capable of setting the first reference voltage and the second reference voltage. 6.   A voltage comparison circuit that compares the output voltage of the first integrator with a third reference voltage, and the output voltage of the first integrator is based on the output of the voltage comparison circuit; The signal processing circuit according to claim 1, wherein the first reference voltage and the second reference voltage are changed so that   A plurality of the first integrators are provided, and the integration time adjustment circuit simultaneously controls on / off of all the first analog switches connected in parallel to the first capacitors of the plurality of first integrators. The signal processing circuit according to claim 1, which is possible.   A plurality of the first integrators, and at least one of the first integrators is capable of selectively inputting the input voltage and the first reference voltage to the first OTA. A first OTA of the first integrator to which the input switching unit is connected also serves as the second OTA, and the first integrator to which the input switching unit is connected. The first capacitor also serves as the second capacitor, and can operate as the integration time adjusting circuit by providing the comparator on the rear stage side of the first integrator to which the input switching unit is connected. 2. The signal processing circuit according to claim 1, wherein ON / OFF of the first analog switch of the other first integrator can be simultaneously controlled.

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