JP2012123258A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable both of an interlaced san and a non-interlaced scan and further to reduce power consumption in the interlaced scan in an image display device.SOLUTION: The image display device includes: a gate driver 91 which outputs a drive signal to pixels from each output line 91a corresponding to each row of the pixels and sequentially switches the pixels into a displayable state for each row, to scan; switching elements 91d and 91e which are provided on the output lines 91 of odd-numbered and even-numbered rows; and a main CPU 12. In an interlaced scan system, the main CPU 12 turns off the switching element 91d and the switching element 91e, while the images of odd-numbered and even-numbered fields are displayed by the pixels of the odd-numbered and even-numbered rows. Therefore, both of the interlaced san and the non-interlaced scan are possible. Moreover, when the interlaced scan is performed, output to a row which is not scanned can be stopped by turning off the switching elements 91d and 91e.

Description

  The present invention relates to a video display device that displays video.

  Generally, video scanning methods include an interlace method and a non-interlace method. In the interlace method, odd-numbered rows (hereinafter referred to as odd-numbered rows) and even-numbered rows (hereinafter referred to as even-numbered rows) of display pixels are alternately scanned. Are alternately displayed, and as a result, one image, that is, one frame image is displayed. In the non-interlace method (progressive method), each row of display pixels is sequentially scanned to display one image.

  Conventionally, in an image display device compatible with an interlace scanning method, a switch for selecting only one of an odd-numbered row and an even-numbered row of pixels has been provided, and the row selected by the switch is switched for each field, and the selection is made A device that supplies a scanning signal from a gate driver to pixels in a specified row is known (for example, see Patent Document 1).

  Further, as another video display device corresponding to the interlace scanning method, the gate driver is divided into a group for driving pixels in odd rows and a group for driving pixels in even rows, and two groups of gate drivers for each field. One that performs interlaced driving by alternately driving is known (for example, see Patent Document 2).

  However, in the video display devices described in Patent Document 1 and Patent Document 2, only interlace scanning can be displayed, and non-interlace scanning is difficult. On the other hand, there is a demand for video display devices that can perform interlaced scanning and non-interlaced scanning. Furthermore, reduction of power consumption during interlace scanning is also desired.

  By the way, there is a liquid crystal display device that arbitrarily attenuates the video signal of the odd field and the even field, and supplies the attenuated signal to the corresponding odd line and the even line of the liquid crystal cell, respectively. It is known (see, for example, Patent Document 3). In this apparatus, since a video signal and a signal approximate thereto are supplied to each liquid crystal cell for each field, it is possible to prevent image quality deterioration such as flicker. However, with this apparatus, it is difficult to solve the above problem.

JP 2009-116101 A JP-A-1-147975 Japanese Patent Laid-Open No. 3-153178

  The present invention has been made to solve the above-described conventional problems, and can perform both interlace scanning and non-interlace scanning, and can reduce power consumption during interlace scanning. An object is to provide a display device.

  In order to achieve the above object, a video display device of the present invention includes a display unit in which a plurality of pixels are arranged in a matrix, a driving unit that drives the plurality of pixels and displays an image on the pixels, Control means for controlling the drive means, wherein the drive means has a plurality of output lines respectively corresponding to the respective rows of the plurality of pixels, and the output lines to the pixels of the respective rows. A row driver that outputs a driving signal and sequentially switches and scans pixels to a displayable state for each row, and is provided on each of the plurality of output lines, and permits output by the output line by an on / off operation. A plurality of switching elements to be stopped, and a data driver for sending image data to a pixel in a row enabled to be displayed by the row driver and causing the pixel to display an image, When the display video scanning method by the display means is an interlace method, the control means is configured to display odd-numbered pixels while the data driver displays the even-field image of the display video on the pixels in the even-numbered rows. While the switching element of the output line corresponding to the row is turned off, the output from the output line is stopped, and the image of the odd field of the display image is displayed on the pixels of the odd row by the data driver. Is characterized in that the switching element of the output line corresponding to the even-numbered row is turned off to stop the output from the output line.

  The video display device further includes a discriminating unit for discriminating whether a scanning method of the display video by the display unit is an interlaced method or a non-interlaced method, and the scanning method is determined by the discriminating unit. Preferably, the control means turns on the switching elements of all output lines and permits the output from the output lines.

  In this video display device, the row driver outputs a drive signal output from the output line to the pixels of each row based on a clock signal, and a drive signal output from the shift register to the pixels of the pixels. A level shifter that converts the level to a level required for driving, and the switching element may be arranged at a stage after the shift register and before the level shifter.

  In this video display device, the switching element may be constituted by a semiconductor switching element.

  According to the present invention, the pixels in each row are sequentially displayed by the row driver, and image data is sent from the data driver to the pixels in the display enabled row, so that non-interlaced scanning is performed. It is also possible to perform interlaced scanning by sending image data from the data driver only to the odd-numbered row and even-numbered row to be scanned.

  Moreover, the row driver outputs a drive signal to the pixels in each row so that the pixels can be displayed for each row. However, when performing interlaced scanning, the row driver outputs an output from the row driver to a row that is not scanned. It can be stopped by turning off the switching elements on the line. When driving the switching element to turn off the switching element, driving power is required, but the row driver output is generally larger than the driving power, reducing power consumption. can do.

1 is a perspective view of a video display device according to an embodiment of the present invention. The electrical block diagram of the said apparatus. The circuit block diagram of the display control circuit of the said apparatus. The circuit block diagram of the gate driver of the said display control circuit. The output control flowchart of the said gate driver.

  An image display apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a video display apparatus according to the present embodiment. The video display device 1 includes a display 2 (display means) in which a plurality of pixels 2a are arranged in a matrix and a speaker 3, and is applied to a television receiver. The display 2 is configured by a liquid crystal display, an organic EL display, or the like. The video display device 1 can perform interlaced scanning and non-interlaced scanning.

  FIG. 2 shows an electrical configuration of the video display device 1. In addition to the display 2 and the speaker 3, the video display device 1 demodulates a tuner 5 that receives a digital television broadcast signal (hereinafter referred to as a broadcast signal) via an antenna 4 and the received broadcast signal. A demodulation circuit 6 and a separation circuit 7 that separates the demodulated broadcast signal into a video signal and an audio signal are provided.

  The video display device 1 also includes a video decoder 8 that decodes the video signal separated by the separation circuit 7 and a display control circuit that controls the display 2 so as to display the video based on the decoded video signal. 9, an audio decoder 10 that decodes the audio signal separated by the separation circuit 7, and an audio output control circuit 11 that controls the speaker 3 so as to output audio based on the decoded audio signal. .

  In addition, the video display device 1 includes a main CPU 12 (hereinafter referred to as CPU 12) that controls each circuit in the device, and a remote controller (hereinafter referred to as remote controller) 13 that instructs the CPU 12 to perform various operations using infrared signals. And an infrared receiving circuit 14 that receives an infrared signal transmitted from the remote controller 13, converts it into an electrical signal, and outputs it to the CPU 12. The CPU 12 selects a channel of a broadcast signal received by the tuner 5 based on an instruction from the remote controller 13.

  The display control circuit 9 (driving unit) includes a gate driver 91 and a source driver 92 that display pixels on the display 2 by driving the pixels 2a (see FIG. 1) in a matrix manner.

  The CPU 12 (control means) controls the display control circuit 9 and the audio output control circuit 11 to perform display control of the display 2 and audio output control of the speaker 3. The CPU 12 (discriminating means) discriminates, based on the decoded video signal, whether the scanning method of the video signal (the scanning method of the display video by the display 2) is an interlace method or a non-interlace method. .

  FIG. 3 shows the configuration of the gate driver 91 and the source driver 92. The gate driver 91 (row driver) has a plurality of output lines 91a corresponding to each row of the pixels 2a, outputs a drive signal from the output lines 91a to the pixels 2a in each row, and outputs the pixels 2a for each row. Then, scanning is performed by sequentially switching to a displayable state. In this switching process, regardless of whether the scanning method of the video signal is an interlace method or a non-interlace method, the rows of displayable pixels 2a are switched one by one in order from the top.

  The source driver 92 (data driver) operates in synchronism with this switching, and sends image data to the pixels 2 a in the row that can be displayed by the gate driver 91. This image data is sent independently for each column of the pixels 2a. Each pixel 2a displays an image based on the received image data. The image data indicates, for example, the pixel value of the pixel 2a.

  When the video signal is a non-interlaced scanning method, the source driver 92 sends image data to the pixels 2a in each row that can be displayed. When the video signal is an interlace scanning method, the source driver 92 sends image data only to the pixels 2a in the odd-numbered rows (hereinafter referred to as odd-numbered rows) counting from the top row when displaying an odd-numbered field image. To do. When displaying an image in an even field, the source driver 92 sends image data only to the pixels 2a in the even-numbered row (hereinafter referred to as an even row) counted from the top row. The odd field is a set of scanning lines skipped from the top scanning line among a predetermined number of scanning lines forming the screen, and is a so-called top field. The even-numbered field is a set of scanning lines skipped from the top scanning line starting from the top and ending at the bottom scanning line, and is a so-called bottom field. A screen of one frame is obtained by combining the odd field and the even field.

  FIG. 4 shows a detailed configuration of the gate driver 91. The gate driver 91 is necessary for driving the pixel 2a with a shift register 91b that outputs a drive signal from each output line 91a to each row of pixels 2a (see FIG. 1) and a voltage level of the drive signal output from the shift register 91b. And a level shifter 91c for converting the voltage level. The gate driver 91 further includes switching elements 91d and 91e disposed on the output line 91a after the shift register 91b and before the level shifter 91c. The switching element 91d is provided in each output line 91a corresponding to the odd-numbered row (2n-1) of the pixel 2a, and the switching element 91e is provided in each output line 91a corresponding to the even-numbered row (2n) of the pixel 2a. Yes.

The shift register 91b includes a D flip-flop (hereinafter referred to as D-FF) 91f connected in series by the same number of stages as the number of rows of the pixels 2a, and is driven by the power supply voltage V _DD . Each D-FF 91f corresponds to each output line 91a. Here, for convenience, the output line 91a corresponding to the pixel 2a in the uppermost row is referred to as the uppermost output line 91a. When an input signal, specifically, a pulse signal indicating the output right of the drive signal is input to the D-FF 91f corresponding to the uppermost output line 91a, the D-FF 91f transfers the pulse signal in order from the end. . This transfer is performed in synchronization with a clock signal (CLK in FIG. 4) input to each D-FF 91f. Each D-FF 91f, when receiving the pulse signal, outputs a drive signal from the corresponding output line 91a to the pixels 2a in each row.

The switching elements 91d and 91e are constituted by semiconductor switching elements, for example, P-channel FETs. The switching elements 91d and 91e permit / stop the output from the output line 91a by an on / off operation, that is, a switching operation. The switching operation is independently controlled by the CPU 12. A resistor R1 is connected to the gate of each switching element 91d, 91e, and the CPU 12 applies a voltage to the grounded resistor R2, and thereby the voltage is applied to each switching element 91d, 91e via each resistor R1. Apply to the gate. Each of the switching elements 91d and 91e is turned off when the voltage applied to the gate is High, and the output line 91a is turned off. When the applied voltage is Low, the switching elements 91d and 91e are turned on and the output line 91a is turned on. The input / output relationship between the switching elements 91d and 91e is not limited to the above. The level shifter 91c, the voltage is input _{V hi,} the differential voltage _{V d} of the _{V low,} and outputs a driving voltage G-out of the pixel 2a.

  Next, the output control of the gate driver 91 in accordance with the display image scanning method will be described with reference to FIG. 5 in addition to FIGS. FIG. 5 shows the output control procedure. In the output control, the video decoder 8 generates video data to be displayed on the display 2 by decoding the video signal (S1). Then, the CPU 12 determines from the generated video data whether the display video scanning method is an interlace method. When it is determined that the scanning method is the interlace method (Yes in S2), while the image of the even field of the display image is displayed on the pixels 2a in the even row by the source driver 92 (Yes in S3), the CPU 12 High is input to the gate of the switching element 91d (switching element of the output line corresponding to the odd-numbered pixels 2a) (S4). Accordingly, the switching element 91d is turned off (S5), and the output operation of the output line 91a having the switching element 91d is stopped by the off operation. Therefore, the output from the output line 91a of the row by the level shifter 92 is turned off (S6).

  While the image of the odd field of the display image is displayed on the odd-numbered pixel 2a by the source driver 92 (No in S3), the CPU 12 determines the switching element 91e (the switching element of the output line corresponding to the even-numbered pixel 2a). High is input to the gate (S7). Accordingly, the switching element 91e is turned off (S8), and the output operation of the output line 91a including the switching element 91e is stopped by the off operation. Therefore, the output from the output line 91a of the row by the level shifter 92 is turned off (S9). In this way, during interlace scanning, the CPU 12 turns on / off the switching elements 91d and 91e in the gate driver 91 to stop the output of the gate driver 91 in the even-numbered row when displaying the odd-numbered field. During the display, the output of the gate drivers 91 in odd-numbered rows is stopped.

  When the CPU 12 determines that the display video scanning method is the non-interlace method (No in S2), the CPU 12 turns on the switching elements 91d and 91e of all the output lines 91a and permits the output from those output lines 91a. To do.

  In the present embodiment, the gate driver 91 makes the pixels 2 a displayable for each row, and image data is sent from the source driver 92 to the pixels 2 a in the display enabled row. Therefore, non-interlaced scanning can be performed, and interlaced scanning can also be performed by sending image data from the source driver 92 only to the row to be scanned among odd-numbered rows and even-numbered rows. .

  In addition, when performing interlaced scanning, the output from the gate driver 91 to the non-scanned row can be stopped by turning off the switching elements 91d and 91e. In order to turn off the switching elements 91d and 91e, it is necessary to drive the element by inputting a high signal to the gates of the switching elements 91d and 91e, and driving power is required, but the gate driver output is higher than the driving power. Since it is generally larger, power consumption can be reduced.

  Further, since the output of the shift register 91b is converted to a voltage level necessary for driving the pixel 2a by the level shifter 91c, the output of the shift register 91b may be a voltage level that can transmit a signal. Accordingly, the switching elements 91d and 91e arranged after the shift register 91b and before the level shifter 91c may be low-voltage compatible switching elements, and the cost can be reduced.

  In addition, this invention is not limited to the structure of said embodiment, A various deformation | transformation is possible according to a use purpose. For example, the switching elements 91d and 91e may be N-channel FETs or bipolar transistors.

1 Video display device 2 Display (display means)
2a Pixel 9 Display control circuit (drive means)
91 Gate driver (row driver)
91a Output line 91b Shift register 91c Level shifters 91d, 91e Switching element 92 Source driver (data driver)
12 Main CPU (control means, discrimination means)

Claims (4)

Display means in which a plurality of pixels are arranged in a matrix;
Driving means for driving the plurality of pixels and displaying an image on the pixels;
A video display device comprising: control means for controlling the drive means;
The driving means includes
A row driver having a plurality of output lines corresponding to each row of the plurality of pixels, outputting a drive signal to the pixels from the output lines, and sequentially switching the pixels to a displayable state for each row; ,
A plurality of switching elements respectively provided on the plurality of output lines and permitting / stopping the output by the output lines by an on / off operation;
A data driver that sends image data to pixels in a row that can be displayed by the row driver and causes the pixels to display an image;
In the case where the display image scanning method by the display unit is an interlace method, the control unit is configured to display odd-numbered pixels while the even-numbered row image of the display image is displayed by the data driver. While the switching element of the output line corresponding to the row is turned off, the output from the output line is stopped, and the image of the odd field of the display image is displayed on the pixels of the odd row by the data driver. The video display device is characterized in that the switching element of the output line corresponding to the even-numbered row is turned off to stop the output from the output line. A discriminating means for discriminating whether the scanning method of the display image by the display means is an interlace method or a non-interlace method;
When the determination unit determines that the scanning method is a non-interlace method, the control unit turns on the switching elements of all output lines and permits output from the output lines. The video display device according to claim 1. The row driver outputs a drive signal from each output line to the pixels in each row based on a clock signal, and a drive signal output from the shift register to a level necessary for driving the pixels. A level shifter to convert,
3. The video display device according to claim 1, wherein the switching element is arranged at a stage subsequent to the shift register and before the level shifter. 4.   The video display device according to claim 1, wherein the switching element includes a semiconductor switching element.

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