JP2012119716A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing forward voltage drop, capable of increasing the maximum reverse voltage, and capable of preventing oscillation during recovery.SOLUTION: A first layer 3 has a first conductivity type. A second layer 1 is provided on the first layer 3 and has a second conductivity type. A third layer CLa is provided above the second layer 1. A fourth layer 15 is provided between the second layer 1 and the third layer CLa and has the second conductivity type. A first portion 2 of the third layer CLa has the second conductivity type, has a high peak value of the impurity concentration as compared to the peak value of the impurity concentration of the second layer 1, and a second portion 16 has the first conductivity type. The fourth layer 15 includes a third portion 15n located on the first portion 2 and a fourth portion 15p located on the second portion 16. The peak value of the impurity concentration in the third portion 15n of the fourth layer 15 is high than that in the fourth portion 15p of the fourth layer 15.

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device.

  As a power semiconductor device, for example, there is a high voltage power module that can withstand a voltage of 600 V or more. Some of such power modules have diodes.

For example, according to JP-A 02-066977 (Patent Document 1), diodes, n contact with the p-layer ^- pn junction by a layer is formed, n ^- on the opposite surface and the p-layer of the layer, n ⁺ Regions and p ⁺ regions are provided. An n buffer layer is provided between the n ⁺ region and the p ⁺ region and the n ⁻ layer. According to this publication, the p ⁺ region is described as having an effect of reducing the reverse recovery current of the diode and shortening the reverse recovery time. In addition, since the depletion layer spreading to the n ⁻ layer when the reverse voltage is applied can be stopped by the n buffer layer, the n ⁻ layer can be thinned, and thus the reverse recovery characteristic of the high voltage diode can be improved. Are listed.

Further, for example, according to Japanese Patent Application Laid-Open No. 08-172205 (Patent Document 2), a diode is formed on an n ⁻ semiconductor layer formed on one main surface of an n-type semiconductor substrate and on a surface layer of the n ⁻ semiconductor layer. N ⁺ cathode region, trench extending from the surface of the n ⁺ cathode region through the n ⁻ semiconductor layer to the n-type semiconductor substrate, a gate electrode filled in the trench through a gate oxide film, and the gate An insulating film formed on the electrode, a cathode electrode in contact with the surface of the n ⁺ cathode region sandwiched between the trenches, a p ⁺ anode region formed on a part of the surface layer of the n-type semiconductor substrate, and p ⁺ An anode electrode in contact with the anode region. According to this publication, by applying a negative voltage to the gate electrode with respect to the cathode electrode, it is possible to prevent destruction of the diode and burning of the switching transformer when an overcurrent flows through the diode. ing.

Japanese Patent Laid-Open No. 02-066977 Japanese Patent Laid-Open No. 08-172205

In power diodes, it has been difficult to simultaneously solve the problems of reducing forward voltage drop (V _F ) and suppressing oscillation during recovery (reverse recovery). For example, in the above Japanese Patent 02-066977, JP-stays discloses to improve the recovery properties by providing a p ⁺ region, good balance solve simultaneously the challenges of the by providing how the p ⁺ region It does not show what can be done.

Depending on the application of the power diode, it may be desired to make V _F particularly small. According contrast to the above Japanese Patent 08-172205 discloses a technique, a result of a negative voltage to the cathode electrodes is applied to the gate electrode, there is a problem that V _F is increased.

The present invention has been made in view of the above problems, one object that is to provide a semiconductor device which can reduce the V _F, and to suppress the oscillation during recovery. Another object of the present invention is to provide a semiconductor device capable of particularly reduced V _F.

  A semiconductor device according to one aspect of the present invention includes first and second electrodes and first to fourth layers. The first layer is provided on the first electrode and has the first conductivity type. The second layer is provided on the first layer and has a second conductivity type different from the first conductivity type. The third layer is provided on the second layer. The second electrode is provided on the third layer. The fourth layer is provided between the second layer and the third layer and has the second conductivity type. The third layer has first and second portions. The first portion has the second conductivity type and has a peak value of an impurity concentration that is higher than the peak value of the impurity concentration of the second layer. The second portion has the first conductivity type. The ratio of the area of the second portion to the total area of the first and second portions is 20% or more and 95% or less. The peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of the first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion located on the second portion. The peak value of the impurity concentration of the third portion of the fourth layer is higher than the peak value of the impurity concentration of the fourth portion of the fourth layer.

According to the semiconductor device according to one aspect of the present invention, the V _{F of} the diode is reduced and the oscillation at the time of recovery is suppressed.

According to the semiconductor device according to another aspect of the present invention, the V _{F of} the diode is reduced.

It is sectional drawing which shows schematically the structure of the diode as a semiconductor device in Embodiment 1 of this invention. 2 is a graph schematically showing impurity profiles C _A and C _B along arrows D _A and D _{B in} FIG. 1, respectively. It is a figure which shows the circuit used for each simulation of the diode of FIG. 1, and its comparative example. It is a graph which shows an example of the simulation of the waveform of each recovery characteristic of the diode of FIG. 1, and the diode of a comparative example. An example of the relationship J _A 1 between the voltage V _AK and the current density J _A in the forward direction of the diode of FIG. 1 and an example of the relationship J _A 0 between the voltage V _AK and the current density J _A in the forward direction of the diode of the comparative example. It is a graph to show. It is a diagram illustrating an example of a cross-point in the temperature change of the relationship between the voltage V _AK and current density J _A. FIG. 1 schematically shows an example of the relationship J _R 1 between the voltage V _RA and the current density J _R in the reverse direction of the diode of FIG. 1 and the relationship J _R 0 between the voltage V _RA and the current density J _R in the reverse direction of the diode of the comparative example. It is a graph shown in. 5 is a graph schematically showing an electric field intensity E and a carrier concentration CC at a point P _B in FIG. 4. In the diode 1 is a graph showing an example of a relationship between each of the V _F and surge voltage V _surge at the rated current density, and the ratio of the width W _p of the p layer to the width W _C of the cathode portion. 2 is a graph showing an example of recovery characteristics of a diode when the ratio of the width W _p of the p layer to the width W _C of the cathode portion in FIG. 1 is 0%. 2 is a graph showing an example of recovery characteristics of a diode when the ratio of the width W _p of the p layer to the width W _C of the cathode portion in FIG. 1 is 10%. 2 is a graph showing an example of recovery characteristics of a diode when the ratio of the width W _p of the p layer to the width W _C of the cathode portion in FIG. 1 is 20%. 2 is a graph showing an example of recovery characteristics of a diode when the ratio of the width W _p of the p layer to the width W _C of the cathode portion in FIG. 1 is 50%. Each of the maximum reverse voltage V _RRM , the rated current density V _F , and the surge voltage V _surge in the diode of FIG. 1 and the ratio C ₁ / C ₃ of the peak values C ₁ and C ₃ of the impurity concentration of FIG. It is a graph which shows an example of a relationship. Peak value C ₂ of Figure 2 and an example of a characteristic curve E _REC 1 showing the trade-off characteristics of the V _F and the recovery loss E _REC at the rated current density of the diode 1 in higher than C _1, 2 An example of the characteristic curve E _REC 2 showing the relationship between V _F and the recovery loss E _REC at the rated current density of the diode of FIG. 1 when the peak values C ₁ and C ₂ are equal, and the rated current of the diode of the comparative example is a graph showing the one example of the characteristic curve E _REC 0 showing the relationship between V _F and the recovery loss E _REC in density. And V _F at the rated current density of the diode 1 is a graph showing an example of the relationship between the ratio C ₂ / C ₁ of the peak value of the impurity concentration C ₁ and C ₂ in FIG. As an example of a hole concentration CCh1 and electron concentration CCe1 along arrows D _A (FIG. 1) peak value C ₂ of Fig. 2 is in the on state when higher than C _1, is equal to the peak value C ₁ and C ₂ in FIG. 2 for arrows in the on state D _a is a graph showing the one example of the hole concentration CCh2 and electron density CCe2 along (Figure 1). It is sectional drawing which shows roughly the structure of the diode as a semiconductor device in Embodiment 2 of this invention. FIG. 19 is a cross-sectional view schematically showing a configuration of a modified example of the diode of FIG. 18. It is sectional drawing which shows roughly the structure of the diode as a semiconductor device in Embodiment 3 of this invention. FIG. 21 is a cross-sectional view schematically showing a configuration of a first modification of the diode of FIG. 20. FIG. 21 is a cross-sectional view schematically showing a configuration of a second modification of the diode of FIG. 20. FIG. 21 is a graph showing an example of carrier concentrations CC3 and CC0 in an on state in each of the diode of FIG. 20 and the diode of the comparative example. An example of the relationship J _A 3 between the voltage V _AK and the current density J _A in the forward direction of the diode of FIG. 20 and an example of the relationship J _A 0 between the voltage V _AK and the current density J _A in the forward direction of the diode of the comparative example are shown in FIG. It is a graph to show. And trench depth y in FIG. 20 is a graph showing an example of the relationship between V _F at the rated current density. It is sectional drawing which shows the structure of the diode of a comparative example.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
Referring to FIG. 1, a diode as a semiconductor device in the present embodiment includes an anode electrode 5 (first electrode), a p layer 3 (first layer), and an n ⁻ drift layer 1 (second electrode). Layer), an n layer 15 (fourth layer), a cathode layer CLa (third layer), and a cathode electrode 4 (second electrode). The p layer 3, the n ⁻ drift layer 1, the n layer 15, and the cathode layer CLa are made of, for example, Si doped with a conductivity type impurity.

  The p layer 3 is provided on the anode electrode 5 (immediately below in the figure) and has p type (first conductivity type).

The n ⁻ drift layer 1 is provided on the p layer 3 (immediately below in the drawing) with a thickness of the dimension t3. The n ⁻ drift layer 1 has a conductivity type different from the p-type, that is, an n-type (second conductivity type).

The cathode layer CLa is provided on the n ⁻ drift layer 1 (downward in the figure) via the n layer 15. The cathode layer CLa has a rectangular shape having a width W _c in plan view. The cathode layer CLa includes an n ⁺ region 2 (first portion) having n-type and a p region 16 (second portion) having p-type.

In the present embodiment, each of n ⁺ region 2 and p region 16 has a rectangular shape with a width W _{n and} a rectangular shape with a width W _p in plan view. Cathode layer CLa, n ⁺ region 2 and p region 16 have the same length in plan view. Also between the width W _c, the width W _n and a width W _p, a relationship of _{W c = W n + W p} . Therefore, the ratio of the area of n ⁺ region 2 to the area of p region 16 in plan view is W _n : W _p . The cathode layer CLa is formed so as to satisfy the following expression.

0.2 ≦ W _p / W _c ≦ 0.95
Therefore, the ratio of the area of p region 16 to the total area of n ⁺ region 2 and p region 16 on n layer 15 is 20% or more and 95% or less.

The dimension t1 in the figure corresponds to the thickness of each of the n ⁺ region 2 and the p region 16 and is, for example, 0.2 to 5 μm. The dimension t _sub corresponds to the thickness of the entire semiconductor layer.

N layer 15 is provided between n ⁻ drift layer 1 and cathode layer CLa, and has an n type (second conductivity type). The thickness of the n layer 15 has a dimension obtained by subtracting the dimension t1 from the dimension t2 in the figure, and is, for example, 1 to 50 μm. The n layer 15 includes an n region 15n (third portion) located on the n ⁺ region 2 and an n region 15p (fourth portion) located on the p region 16. Further, the conductivity type impurity contained in the n layer 15 is substantially only an n type conductivity type impurity and does not substantially include a p type conductivity type impurity.

The cathode electrode 4 is provided on the cathode layer CLa.
Still referring to FIG. 2, each of impurity profiles C _A and C _B shows the distribution of impurity concentration at depths D _A and D _B (FIG. 1). The n ⁺ region 2 has a higher impurity concentration peak value C ₄ than the impurity concentration peak value C ₀ of the n ⁻ drift layer 1. The peak value C ₄ of the impurity concentration in the n ⁺ region 2 is higher than the peak value C ₃ of the impurity concentration in the p region 16. The ratio of the impurity concentration peak value C _{1 in} the n region 15 p to the impurity concentration peak value C _{3 in the} p region 16 is 0.001 or more and 0.1 or less. Each of the impurity concentration peak values C ₁ and C ₂ of the n layer 15 is higher than the impurity concentration peak value C ₀ of the n ⁻ drift layer 1 and the impurity concentration peak value of the n ⁺ region 2 of the cathode layer CLa. lower than the C _4.

For example, the surface concentration of n ⁺ region 2 is 1 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ , and the surface concentration of p region 16 is 1 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³ . The peak values C ₁ and C ₂ of the impurity concentration of the n layer 15 are 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³ .

In the present embodiment, the conductivity type impurity contained in n layer 15 is substantially only an n-type conductivity type impurity and does not substantially include a p-type conductivity type impurity. Therefore impurity profile C _B in the interval of depth t1~t2 in FIG 2 shows the concentration of n-type conductivity type impurity. If n region 15p substantially includes p-type conductivity impurities in addition to n-type conductivity impurities, the impurity concentration is the effective impurity concentration, that is, the concentration of p-type and n-type conductivity impurities. This is the difference.

Next, a diode of a comparative example will be described.
Referring to FIG. 26, the diode of the comparative example has a cathode layer CLb composed of n ⁺ region 2 instead of cathode layer CLa of the present embodiment. An n layer 15 is present immediately above the cathode CLb. In this comparative example, the following two problems can be considered.

First, during the recovery operation, the concentration of holes remaining on the n ⁺ region 2 and the n layer 15 side is low, and the depletion layer tends to extend. Since an oscillation phenomenon occurs at the moment when the depletion layer reaches the n layer 15, the safe operating area (SOA) and the recovery tolerance are reduced.

Second, as a countermeasure against the oscillation phenomenon during recovery, it is necessary to delay the extension of the depletion layer from the p-layer 3 / n ⁻ drift layer 1 junction, which is the main junction, to the cathode side. In the comparative example, it is necessary to increase the dimension t3 corresponding to the thickness of the n ⁻ drift layer. As a result, it becomes difficult to improve the trade-off characteristics between the reduction and recovery loss of V _F (E _REC).

In the comparative example, the first problem occurs when the dimension t3 is reduced, and the second problem occurs when the dimension t3 is increased. That is, in this comparative example, the improvement of the trade-off characteristics between the reduction and recovery loss of the V _F, it is difficult to achieve both improvement of the SOA tolerance due suppression of oscillation phenomenon.

According to the present embodiment, on the other hand, while securing the withstand voltage, it is possible to achieve both improvement in reducing the SOA tolerance of V _F. That reduces V _F, improve the maximum reverse voltage, and it is possible to suppress the oscillation during recovery.

  Referring to FIG. 3, in order to verify the above-described effects, a simulation was performed on a circuit including a rated 3300 V class diode as an example of the semiconductor device of the present embodiment. This circuit includes a diode DD, an IGBT (Insulated Gate Bipolar Transistor) transistor TR, coils LM, LAK, LCE, resistors RL, RAK, RCE, RG, power supplies VC, VG, and a current source ION. Have. The coil LM corresponds to the parasitic inductance, the resistor RG corresponds to the gate resistance of the IGBT, and the power source VG corresponds to the gate voltage of the IGBT. The coils LAK and LCE correspond to the wiring impedance for matching the actual measurement result and the simulation result. Resistances RL, RAK, and RCE correspond to wiring-related resistances for matching the actual measurement result and the simulation result. The results of this simulation will be described below.

Referring to FIG. 4, with respect to Examples and Comparative Examples were recovery characteristics waveform, i.e. the simulation of the time variation of the voltage V _AK and current density J _A during recovery performed. In the figure, voltage V _AK 1 and current density J _A 1 correspond to the diode of this embodiment (FIG. 1), and voltage V _AK 0 and current density J _A 0 correspond to the diode of the comparative example (FIG. 26). Is. According to the present embodiment, the oscillation that occurs at the time of recovery is suppressed as compared with the comparative example. As a result, the surge voltage V _surge which is the peak voltage of the voltage V _AK was 5000 V or more in the comparative example, but could be suppressed to about 3000 V in the present example.

As simulation conditions, the coil LM is set to 12 μH, the power source VC is set to 1700 V, the rated current density J _A R is set to 90 _A / cm ² , the forward current J _F is set to J _A R / 10, and the temperature is set to 298 K.

Referring to FIG. 5, a simulation of current density J _A -voltage V _AK characteristics was performed. In the figure, the relationship J _A 1 corresponds to the diode of the example of the present embodiment (FIG. 1), and the relationship J _A 0 corresponds to the diode of the comparative example (FIG. 26). V _F is the voltage V _AK when the current density J _A is the rated current density J _A R = 90 _A / cm ² . It was possible to reduce the V _F as compared with the comparative example according to the present embodiment.

The current density J _A -voltage V _AK characteristic generally varies with temperature. The current density J _A -voltage V _AK characteristics at 25 ° C. and 125 ° C. are as shown in FIG. 6, for example. A point where both characteristic curves intersect is defined as a cross point CP.

With reference to FIG. 7, the reverse characteristic (current density J _R -voltage V _RA ) was simulated. In the figure, the relationship J _R 1 corresponds to the diode of this embodiment (FIG. 1), and the relationship J _R 0 corresponds to the diode of the comparative example (FIG. 26). The maximum reverse voltage V _RRM is the voltage V _RA when the current density J _R = 1 × 10 ⁻² A / cm ² . According to this example, the maximum reverse voltage V _RRM could be increased as compared with the comparative example.

If n layer 15 substantially contains p-type conductivity impurities, maximum reverse voltage V _RRM is lowered. In other words, the maximum reverse voltage V _RRM is increased by the fact that the conductive impurities contained in the n layer 15 are substantially only n-type conductive impurities.

Referring mainly to FIG. 8, the distribution of the electric field strength E and the carrier concentration CC at the point P _B (FIG. 4) in the device depth direction was analyzed using simulation. In the figure, the horizontal axis represents the depth along the arrow D _A (FIG. 1). Further, the hole concentration CCh1, the electron concentration CCe1, and the electric field intensity E1 correspond to the diode of this embodiment (FIG. 1), and the hole concentration CCh0, the electron concentration CCe0, and the electric field intensity E0 correspond to the diode of the comparative example (FIG. 26). ). In the structure of this example (FIG. 1), the hole concentration CCh1 on the cathode side was improved from the hole concentration CCh0 of the comparative example by injecting holes from the p region 16 located on the cathode side during the recovery phenomenon. As a result, as indicated by an arrow RE in the figure, an electric field relaxation phenomenon in which the electric field intensity E on the cathode side relaxed occurred.

Referring mainly to FIGS. 9 to 13, each of V _F (FIG. 5) and surge voltage V _surge (FIG. 4) is correlated with the width ratio W _p / W _c (FIG. 1) (FIG. 9). In order to investigate the above, simulations (for example, FIGS. 10 to 13) with recovery characteristic waveforms (time changes during recovery of each of the current I _A and the voltage V _AK ) under various ratios W _p / W _c are performed. I did it.

As a result, when the width W _p is 20% or more of the width W _c , that is, the ratio of the area of the p region 16 to the total area of the n ⁺ region 2 and the p region 16 (FIG. 1) is 20% or more. By suppressing the oscillation at the time of recovery, the surge voltage V _surge is significantly suppressed to the rated voltage of 3300 V or lower.

Also the width W _p exceeds 95% of the width W _c, may create an obstacle to the operation of the diode by V _F increases rapidly. Conversely, the width W _p is 95% or less of the width W _c , that is, the ratio of the area of the p region 16 to the total area of the n ⁺ region 2 and the p region 16 is 95% or less. V _F is significantly suppressed.

Referring mainly to FIG. 14, each of maximum reverse voltages V _RRM , V _F and surge voltage V _surge and the ratio C ₁ / C _{3 of} impurity concentration peak values C ₁ and C ₃ (FIG. 2) The correlation was examined by simulation. Based on the results of FIG. 9, the width W _p is set to 20% of the width W _c so that oscillation during recovery is suppressed.

As a result of simulation, it was found that the surge voltage V _surge can be remarkably suppressed to a rated voltage of 3300 V or less by setting the ratio C ₁ / C ₃ to 1 × 10 ⁻¹ or less.

Further, it was found that when the ratio C ₁ / C ₃ is 1 × 10 ⁻³ or more, the maximum reverse voltage V _RRM (FIG. 7) is secured up to the rated voltage of 3300 V or more. This is because the ratio C ₁ / C ₃ is set to 1 × 10 ⁻³ or more to suppress the depletion layer from extending from the p-layer 3 / n ⁻ drift layer 1 junction, which is the main junction, to the cathode side. I think.

Referring to FIG. 15, the trade-off characteristic between recovery loss E _REC (mJ / A · pulse) and V _F (V) was examined by simulation. In the figure, a characteristic curve E _REC 1 is obtained when the peak values C ₁ and C ₂ (FIG. 2) of the impurity concentration satisfy C ₂ > C ₁ , and the characteristic curve E _REC 2 satisfies C ₂ = C ₁ . Is the case. On the other hand, the characteristic curve E _REC 0 corresponds to the diode of the comparative example (FIG. 26).

As a result, compared to the structure of the comparative example (FIG. 26) (characteristic curve E _REC 0), the recovery loss in the case of the structure of this example (characteristic curve E _REC 1 and E _REC 2) is shown. trade-off relationship between E _REC and V _F is improved, especially when the peak value C ₁ and C ₂ of the impurity concentration satisfies C _2> C ₁ (characteristic curve E _REC 1), found to be more possible improvement It was. That is, it has been found that the trade-off relationship can be improved while maintaining the dimension t3 (FIGS. 1 and 26) from the viewpoint of the SOA, that is, without relying on the reduction of the dimension t3.

As shown in FIG. 16, V _F decreases as the ratio C ₂ / C ₁ of the peak value of the impurity concentration increases.

Referring to FIG. 17, it is a simulation result of carrier concentration CC in the ON state, that is, when current density J _A is equal to rated current density J _A R (FIG. 5). In the figure, the horizontal axis represents the depth along the arrow D _A (FIG. 1). The hole concentration CCh1 and the electron concentration CCe1 correspond to the case where the impurity concentration peak values C ₁ and C ₂ satisfy C ₂ > C _{1. The} hole concentration CCh 2 and the electron concentration CCe ₂ correspond to the impurity concentration peak value C _1. And C ₂ corresponds to the case where C ₂ = C ₁ is satisfied.

From this result, it was found that when the peak values C ₁ and C ₂ are C ₂ > C ₁ , the carrier concentration in the vicinity of the cathode is increased in the ON state. As a result of the decrease in V _F (FIG. 16) due to the increase in carrier concentration, it is considered that the trade-off relationship between the recovery loss E _REC and V _F (FIG. 15) has been improved.

According to the present embodiment, V _F is reduced, oscillation during recovery is suppressed, and the maximum reverse voltage V _RRM is improved. This point will be described in more detail below.

In the diode structure of the present embodiment (FIG. 1), holes are injected from the p region 16 during the recovery phenomenon, so that the cathode-side hole concentration CCh1 (FIG. 8) is the same as that of the comparative diode structure (FIG. 26). It is higher than the hole concentration CCh0 in the case. As a result, compared with the comparative example, in the present embodiment, the electric field on the cathode side is relaxed at the time of recovery as indicated by an arrow RE (FIG. 8), so the p layer 3 / n ⁻ drift layer 1 junction which is the main junction The depletion layer extends from the cathode side to the cathode side. As a result, the oscillation phenomenon during recovery is suppressed as shown in FIG. 4, and the SOA tolerance of the diode is improved. Thus, since the diode of this embodiment (FIG. 1) can prevent oscillation by causing electric field relaxation (suppressing depletion layer elongation) by hole injection from the p region 16 during the recovery phenomenon, the thickness of the n ⁻ drift layer 1 can be reduced. can be reduced t3, the recovery loss E _REC as shown in Figure 15, is a trade-off characteristics between V _F improved.

In order to promote the hole injection from the cathode side during the recovery operation, in FIG. 1, the ratio of the area of the p region 16 to the area of the cathode layer CLa (the ratio W _p / W of the widths W _p and W _{c in} FIG. 1). _c ) is an important parameter. That is, highly dependent in this parameter, V _F and surge voltage V _surge greatly changes as shown in FIG. According to the present embodiment, when the following expression (1) is satisfied, good operation of the diode is ensured while suppressing oscillation during recovery.

20% ≦ ratio W _p / W _c ≦ 95% (1)
In the equation (1), the upper limit value of 95% is a condition for reducing V _F (FIG. 9) to a practically sufficient level. Further, the lower limit of 20% is to suppress the surge of the waveform of the V _AK waveform (FIGS. 10 to 13), that is, V _surge (FIG. 9) to a value of the breakdown voltage class (3300 V in the above-described simulation) or less. Is the condition. By satisfying Equation (1) in this way, V _F is reduced and oscillation during recovery is suppressed.

As described above, the ratio C ₁ / C ₃ (FIG. 14) of the peak values C ₁ and C ₃ (FIG. 2) of the impurity concentration is reduced as follows, while reducing V _F and suppressing oscillation during recovery. _Satisfying 2) improves the maximum reverse voltage V _RRM .

0.001 ≦ ratio C ₁ / C ₃ ≦ 0.1 (2)
In the above equation (2), the upper limit value of 0.1 is that the amount of holes injected from the p region 16 of the cathode layer CLa is sufficient, so that V _surge is the value of the breakdown voltage class (in the above-described simulation). 3300V) is a condition for suppressing to below. Further, the lower limit value 0.001 represents a decrease in the maximum reverse voltage V _RRM caused by the depletion layer extending from the p-layer 3 / n ⁻ drift layer 1 junction, which is the main junction to the cathode side, reaching the p region 16 during reverse bias. This is a condition to prevent.

Further, when the peak values C ₁ and C ₂ (FIG. 2) of the impurity concentration satisfy the following expression (3), the carrier concentration CC (FIG. 17) on the cathode side when the diode is in the ON state is increased.

C ₂ > C ₁ (3)
As a result of increasing the carrier concentration CC in this way, V _F (FIG. 16) is lowered, so that the trade-off characteristic (FIG. 15) between the recovery loss E _REC and V _F is improved.

  When the above relationships (1) to (3) are satisfied, a diode having particularly excellent characteristics as compared with the diode of the comparative example (FIG. 26) can be obtained.

(Embodiment 2)
Referring to FIG. 18, the diode as the semiconductor device of the present embodiment includes an n-type diffusion layer 17 (fifth layer), a trench structure 26a, a p ⁺ diffusion layer 18, an interlayer insulating film 19, Insulating films 20 and 23, a silicide layer 21 a, and a barrier metal layer 22 are included.

N type diffusion layer 17 is provided between p layer 3 and n ⁻ drift layer 1 and has n type. The trench structure 26 a has a trench that penetrates the p layer 3 and the n-type diffusion layer 17, and has a gate electrode 14 that fills the trench through the gate insulating film 12. The gate electrode 14 is electrically insulated from the anode electrode 5 by the interlayer insulating film 19. The silicide layer 21a is for realizing a low contact resistance with the Si diffusion layer, and is made of, for example, TiSi ₂ , CoSi, or WSi. The barrier metal layer 22 is made of, for example, TiN. The interlayer insulating film 19 is, for example, a silicate glass film to which boron, phosphorus or the like is added.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

Next, the manufacturing method of the diode of this Embodiment is demonstrated.
First, a substrate which is a thick n ⁻ drift layer 1 is prepared. The impurity concentration of n ⁻ drift layer 1 is determined depending on the breakdown voltage class. For example, in the 600 to 6500 V class, it is 1 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻³ .

Next, a p layer 3 and an n-type diffusion layer 17 located immediately below the p layer 3 are formed on the surface of the substrate. The p layer 3 has, for example, a peak concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and a diffusion depth of 1 to 4 μm. The peak concentration of impurities in n type diffusion layer 17 is not less than the concentration of impurities in n ⁻ drift layer 1 and not more than the peak value of impurity concentration in p layer 3. Next, ap ⁺ diffusion layer 18 is formed on the substrate surface. The p ⁺ diffusion layer 18 has, for example, a surface concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ and a diffusion depth of about 0.5 μm. Next, a trench structure 26a and a cathode layer CLa are formed.

The p ⁺ diffusion layer 18 may be formed after the trench structure 26a is formed.
The diode of this embodiment is used so that a potential lower than the potential of the cathode electrode 4 is applied to the gate electrode 14 when a reverse voltage is applied to the diode. For this purpose, for example, the gate electrode 14 is electrically connected to the anode electrode 5. If the potential of the cathode electrode 4 becomes positive when a reverse voltage is applied to the diode, the gate electrode 14 may be grounded.

In this case, according to the simulation results, it was found that it is possible to reduce the current density J _A cross point CP (Figure 6). As a result, the current density at the cross point CP can be made smaller than the current density at which the diode is overloaded. In this case, the temperature coefficient of V _F in overload and became diodes since positive, it is possible to prevent the current concentration on the overload and becomes a diode.

  Further, the amount of holes injected from the p layer 3 when the device is turned on can be controlled by the n-type diffusion layer 17.

Further, the trench structure 26a has a pseudo field plate structure, and the maximum reverse voltage V _RRM can be maintained by promoting the extension of the depletion layer from the junction between the p layer 3 and the n-type diffusion layer 17. Further, since trench structure 26a is formed deeper than the interface between p layer 3 and n type diffusion layer 17, maximum reverse voltage V _RRM can be more reliably maintained.

In addition comparative examples of the diode (Fig. 26), usually, n ^- tradeoff characteristics between recovery loss E _REC and V _F by adjusting the lifetime of carriers in the drift layer 1 is controlled. On the other hand, according to the present embodiment, this trade-off characteristic is controlled by adjusting the concentration of the p layer 3, and the controllable range of this trade-off characteristic is expanded, and the lifetime adjustment step is performed. By eliminating it, the wafer process can be simplified.

A modification of the present embodiment will be described with reference to FIG. The diode of this modification includes an n-type diffusion layer 17, a trench structure 27, a p ⁺ diffusion layer 18, silicide layers 21a and 21b, and a barrier metal layer 22b. The trench structure 27 has a trench penetrating the p layer 3 and the n-type diffusion layer 17, and has a gate electrode 14 filling the trench with the gate insulating film 12 interposed therebetween. The gate electrode 14 is electrically connected to the anode electrode 5 and has the same potential as the anode electrode 5.

  According to this modification, the same potential as that of the anode electrode 5 is applied to the gate electrode 14. Thus, even when the potential of the gate electrode 14 is not controlled from the outside of the diode, a potential lower than the potential of the cathode electrode 4 can be applied to the gate electrode 14 when a reverse voltage is applied to the diode. it can. As a result, the same effect as this embodiment can be obtained.

(Embodiment 3)
Referring to FIG. 20, the diode as the semiconductor device of the present embodiment includes an anode electrode 5 (first electrode), a p layer 3 (first layer), and an n ⁻ drift layer 1 (second electrode). Layer), n layer 15 (fourth layer), cathode layer CLb (third layer), cathode electrode 24 (second electrode), trench structure 26b, interlayer insulating film 19, and insulating film 20 and 23 and a barrier metal layer 22.

The p layer 3 is provided on the anode electrode 5 and has p type (first conductivity type). The n ⁻ drift layer 1 is provided on the p layer 3 and has a conductivity type different from the p type, that is, an n type (second conductivity type).

Cathode layer CLb is provided on n ⁻ drift layer 1 via n layer 15. The cathode layer CLb has an n ⁺ region 2 (first portion). N ⁺ region 2 is n-type and has a higher impurity concentration peak value than that of n ⁻ drift layer 1.

The n layer 15 is provided between the n ⁻ drift layer 1 and the cathode layer CLb. N layer 15 is n-type, has a higher impurity concentration peak value than that of n ⁻ drift layer 1, and has an impurity concentration peak value of n ⁺ region 2. It has a peak value with a lower impurity concentration.

The cathode electrode 24 is provided on the cathode layer CLb.
The trench structure 26 b has a trench that penetrates the n ⁺ region 2 and the n layer 15, and has a gate electrode 14 that fills the trench through the gate insulating film 12. That is, trench structure 26 b is provided in n ⁺ region 2 and n layer 15.

  Each of the gate electrode 14 and the cathode electrode 24 is connected to the positive electrode side and the negative electrode side of the voltage source 30. Thereby, the trench structure 26b is configured such that a positive potential is applied with reference to the potential of the cathode electrode 24.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  It is also possible to use a structure having the cathode layer CLa (FIG. 21) or a structure not having the n layer 15 (FIG. 22) instead of the cathode layer CLb.

  In order to examine the characteristics of the diode of the present embodiment, a simulation similar to that of the first embodiment was performed. The results of this simulation will be described below.

Referring to FIG. 23, the carrier concentration CC in the on state was simulated. As a result, it was found that the carrier concentration CC3 of the diode of the example of the present embodiment (FIG. 20) is higher than the carrier concentration CC0 of the diode of the comparative example (FIG. 26). That is, it was found that the carrier concentration in the vicinity of the cathode was increased in the on state. I think V _F is reduced by increasing the carrier concentration.

Referring to FIG. 24, simulation of current density J _A -voltage V _AK characteristics was performed. In the figure, the current density J _A 3 corresponds to the diode of this embodiment (FIG. 20), and the current density J _A 0 corresponds to the diode of the comparative example (FIG. 26). According to this example, it was found that the current density J _A -voltage V _AK characteristic curve shifts toward the smaller voltage V _{AK as} compared with the comparative example. That it was found that it is possible to reduce the V _F.

Referring to FIG. 25 was performed with the depth y of the trench structure 26b, a simulation of the correlation between V _F. As a result, by the trench depth y and dimension t2 or more, it was able to be more sufficiently reduce the V _F. That is, n ⁺ region 2, by a trench structure 26b is provided so as to penetrate the n layer 15 was found to be more sufficiently reduce the V _F.

According to the present embodiment, by applying a positive bias to the trench structure 26b existing on the cathode side, the accumulation layer is formed on the trench side wall, so that the n + region 2 is enlarged in a pseudo manner. Electron injection from the cathode side can be promoted when the device is turned on. This can reduce the V _F.

Also the n ⁺ region 2, by a trench structure 26b is provided so as to penetrate the n layer 15 can be more sufficiently reduce the V _F. In the modification (FIG. 22), the trench structure 26 b may be provided so as to penetrate the n ⁺ region 2.

  In each of the above embodiments, the first and second conductivity types are p-type and n-type, respectively, but the present invention is not limited to this, and each of the first and second conductivity types. May be n-type and p-type.

  In each of the above embodiments, the diode has been described as the semiconductor device. However, the semiconductor device of the present invention is not limited to a single diode, and may be a power module including a diode. Such a power module includes, for example, an IGBT.

Further, the case where the p layer 3, the n ⁻ drift layer 1, the n layer 15, and the cathode layer CLa are made of Si to which a conductivity type impurity is added has been described. However, instead of Si, a wide area such as SiC or GaN is used. The same effect can be obtained by using a band gap material.

  Further, although a high withstand voltage semiconductor device rated at 3300 V class has been described as an example, the present invention can also be applied to other withstand voltage classes.

  Each embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a power semiconductor device.

CLa, CLb cathode layer (third layer), 1 n ⁻ drift layer (second layer), 2 n ⁺ region (first portion), 3 p layer (first layer), 4, 24 cathode electrode (Second electrode), 5 anode electrode (first electrode), 12 gate insulating film, 14 gate electrode, 15 n layer (fourth layer), 15 nn region (third portion), 15 pn region ( (Fourth portion), 16 p region (second portion), 17 n-type diffusion layer (fifth layer), 26a, 26b, 27 trench structure, 30 voltage source.

Claims (5)

A first electrode;
A first layer provided on the first electrode and having a first conductivity type;
A second layer provided on the first layer and having a second conductivity type different from the first conductivity type;
A third layer provided on the second layer;
A second electrode provided on the third layer;
A fourth layer provided between the second layer and the third layer and having the second conductivity type,
The third layer is
A first portion having the second conductivity type and having a peak value of an impurity concentration higher than that of the impurity concentration of the second layer;
A second portion having the first conductivity type,
The ratio of the area of the second portion to the total area of the first and second portions is 20% or more and 95% or less,
The peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of the first portion of the third layer,
The fourth layer includes a third portion located on the first portion and a fourth portion located on the second portion;
The semiconductor device, wherein a peak value of the impurity concentration of the third portion of the fourth layer is higher than a peak value of the impurity concentration of the fourth portion of the fourth layer.   2. The semiconductor device according to claim 1, wherein a ratio of a peak value of the impurity concentration of the fourth portion to a peak value of the impurity concentration of the second portion is 0.001 or more and 0.1 or less.   3. The semiconductor device according to claim 1, wherein the conductivity type impurity contained in the fourth layer is only the conductivity type impurity of the second conductivity type.   The semiconductor device according to claim 1, wherein a peak value of the impurity concentration of the first portion is higher than a peak value of the impurity concentration of the second portion. A fifth layer provided between the first layer and the second layer and having the second conductivity type;
The semiconductor device according to claim 1, further comprising a trench structure penetrating the first and fifth layers.

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