JP2012118895A - Communication device, data transfer method of communication device, and communication program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To complete DMA transfer early in fixed-period communication.SOLUTION: A block size setting part 222 sets a plurality of block sizes in the decreasing order. A data communication part 210 stores received data as partial data of period data 110 in a buffer 211 until reception of the period data 110 is completed. A transfer control circuit 223 transfers partial data stored in the buffer 211 as first block data to a memory 230 a communication time, needed to receive partial data by a first block size, after the data communication part 210 starts the communication. Further, the transfer control circuit 223 transfers partial data stored in the buffer 211 as new block data a transfer time, needed to transfer the partial data by a last block size, after the last block data begins to be transferred.

Description

  The present invention relates to, for example, a communication device that transfers communication data by DMA (Direct Memory Access), a data transfer method of the communication device, and a communication program.

Conventionally, a CPU (Central Processing Unit) of a transmission device (communication device) accesses a communication buffer, transfers received data from the communication buffer to a memory, and generates response data for the received data.
However, as the processing speed of the CPU has increased, data transfer between the communication buffer and the memory is performed by a mechanism different from the CPU in order to effectively utilize the CPU performance. This mechanism is called “DMA transfer”.

For example, in “fixed cycle communication” in which a plurality of transmission devices transmit in order within a fixed cycle, the transfer device starts DMA transfer when the fixed cycle communication ends.
Then, the CPU of the transmission apparatus generates response data for the received data after the DMA transfer is completed. The generated response data is transmitted at the next transmission timing.

  As a method for completing DMA transfer early, Patent Document 1 discloses the following method.

  The method described in Patent Document 1 performs DMA transfer every time data is received by a certain block size, instead of collectively transferring data received at a certain period when communication at a certain period is completed. It is.

However, in the method described in Patent Document 1, when the block size is large, large received data corresponding to the block size must be DMA-transferred after communication of a certain period is completed. In this case, the time at which the DMA transfer is completed is not so early.
In addition, when the block size is small, the number of times of accessing the communication buffer and memory increases, and the overhead for accessing the communication buffer and memory increases. In this case, the time required for the DMA transfer cannot be shortened, and the DMA transfer cannot be completed quickly.

In the conventional DMA transfer, the CPU is notified after the DMA transfer is completed, and the CPU starts an interrupt handler for processing received data after the DMA transfer is completed.
For this reason, even if the DMA transfer is completed, the received data cannot be processed until the interrupt handler activation process is completed.

JP 2006-079332 A

  An object of the present invention is to enable a DMA transfer to be completed quickly in, for example, fixed-cycle communication.

The communication device of the present invention
A memory for storing data;
A communication buffer for storing communication data;
A data communication unit that communicates communication data via a network and stores the received data in the communication buffer as partial data of the communication data from the start of receiving the communication data until the end of receiving the communication data When,
When the communication time required for receiving the partial data by the first block size out of a plurality of block sizes determined in advance from the time when the data communication unit starts communication is stored in the communication buffer. The transfer time required for transferring the stored partial data to the memory as the first block data and transferring the partial data by the previous block size from the start of the transfer of the previous block data. A data transfer unit that transfers the partial data stored in the communication buffer to the memory as new block data.

  According to the present invention, for example, DMA transfer can be completed early in fixed-cycle communication.

1 is a configuration diagram of a communication system 100 according to Embodiment 1. FIG. 2 is a functional configuration diagram of a transmission apparatus 200 according to Embodiment 1. FIG. FIG. 6 shows an example of periodic data 110 in the first embodiment. FIG. 6 shows an example of periodic data 110 in the first embodiment. 3 is a flowchart illustrating an overview of a communication processing method according to the first embodiment. 9 is a flowchart showing data transfer processing (S130) of the transfer control circuit 223 according to the first embodiment. 5 is a flowchart showing data transfer processing (S130) of the interrupt control circuit 224 according to the first embodiment. FIG. 3 is a schematic diagram illustrating a data transfer method according to the first embodiment. FIG. 3 is a schematic diagram showing a data transfer method (interrupt notification, transfer completion notification) in the first embodiment. Schematic diagram showing a conventional data transfer method. Schematic diagram showing a conventional data transfer method. FIG. 3 is a diagram illustrating an example of hardware resources of the transmission apparatus 200 according to the first embodiment.

Embodiment 1 FIG.
A mode in which the transfer waiting time is determined based on the communication speed and the transfer speed, and received data is transferred from the communication buffer to the memory by DMA (Direct Memory Access) each time the transfer waiting time elapses will be described.

FIG. 1 is a configuration diagram of a communication system 100 according to the first embodiment.
The configuration of communication system 100 in the first embodiment will be described with reference to FIG.

  The communication system 100 includes a bus-type network 101 and a plurality of transmission apparatuses 200 (an example of communication apparatuses) connected to the network 101.

Each transmission apparatus 200 performs fixed-cycle communication (for example, time division communication) via the bus-type network 101.
That is, each transmission device 200 transmits the packet 111 to another transmission device 200 at a predetermined communication cycle. Further, the transmission order of each transmission apparatus 200 is determined, and each transmission apparatus 200 transmits the packet 111 according to the transmission order. The packet 111 transmitted by each transmission device 200 is received by all other transmission devices 200.
For example, one communication cycle is divided into a plurality of unit times, and a unit time is assigned to each transmission apparatus 200. Each transmission device 200 transmits the packet 111 only in the allocated unit time.

  The network 101 of the communication system 100 may be a network other than the bus type (star type, ring type, etc.).

FIG. 2 is a functional configuration diagram of the transmission apparatus 200 according to the first embodiment.
A functional configuration of transmission apparatus 200 according to Embodiment 1 will be described with reference to FIG.

  The transmission device 200 (an example of a communication device) includes a data communication unit 210, a DMA transfer unit 220, a memory 230, and a CPU 240. The data communication unit 210 includes a buffer 211 (an example of a communication buffer).

  A CPU 240 (Central Processing Unit) processes data stored in the memory 230.

The data communication unit 210 communicates periodic data 110 (an example of communication data) via the network 101.
The data communication unit 210 stores the received data in the buffer 211 as partial data of the periodic data 110 from the start of receiving the periodic data 110 until the reception of the periodic data 110 is completed.
The period data 110 is data including a plurality of packets 111 received within the communication period. The period data 110 will be described separately.

  The DMA transfer unit 220 includes a control register 221, a block size setting unit 222, a transfer control circuit 223, and an interrupt control circuit 224.

  The control register 221 stores DMA transfer control information. The DMA transfer control information will be described separately.

The block size setting unit 222 calculates a block size and a transfer waiting time described later based on the control information stored in the control register 221.
Details of the block size setting unit 222 will be described separately.

The transfer control circuit 223 (an example of a data transfer unit) receives partial data by the first block size out of a plurality of block sizes determined in advance since the data communication unit 210 started communication. When the required communication time has elapsed, the partial data stored in the buffer 211 is transferred to the memory 230 as the first block data.
Further, the transfer control circuit 223 stores the data stored in the buffer 211 when the transfer time required to transfer the partial data by the previous block size has elapsed since the start of the transfer of the previous block data. The existing partial data is transferred to the memory 230 as new block data.

When the communication time and the transfer time corresponding to the block size are rephrased as the transfer waiting time, the above description of the transfer control circuit 223 is as follows.
The transfer control circuit 223 transfers the partial data stored in the buffer 211 to the memory 230 as the first block data when a predetermined first transfer waiting time elapses from when the data communication unit 210 starts communication. .
Further, the transfer control circuit 223 transfers the partial data stored in the buffer 211 to the memory 230 as the current block data when the current transfer waiting time has elapsed since the start of the previous block data transfer. . The current transfer waiting time is a time for transferring partial data by a data size (a block size described later) obtained by multiplying the communication speed of the network 101 by the previous transfer waiting time.

The transfer control circuit 223 (an example of a transfer completion notification unit) notifies the CPU 240 of a transfer completion notification when all the partial data has been transferred to the memory 230.
When the interrupt handler activation process is completed and the transfer completion notification is detected, the CPU 240 processes the periodic data 110 constituted by the partial data transferred to the memory 230 by the interrupt handler. The interrupt handler is a function for processing the periodic data 110.

  The interrupt control circuit 224 (an example of an interrupt notification unit) notifies the CPU 240 of an interrupt notification before the transfer control circuit 223 notifies the CPU 240 of a transfer completion notification. The CPU 240 starts the interrupt handler activation process when detecting the interrupt notification notified from the interrupt control circuit 224.

The periodic data 110 is communicated via the network 101 and transferred from the buffer 211 to the memory 230 via the bus 201.
The network 101 is an external communication path (or communication cable, signal line), and the bus 201 is an internal communication path (or signal line).

3 and 4 are diagrams illustrating an example of the periodic data 110 according to the first embodiment.
The period data 110 in the first embodiment will be described with reference to FIGS. 3 and 4.

As illustrated in FIG. 3, the period data 110 is data including a plurality of packets 111 transmitted from each transmission device 200 in one communication period.
However, the periodic data 110 received by each transmission apparatus 200 does not include its own transmission packet. For example, the periodic data 110 received by the transmission apparatus 200C does not include the packet 111C transmitted by the transmission apparatus 200C.

In FIG. 4, the shaded portion indicates a portion corresponding to its own transmission packet.
Periodic data 110 received by each transmission apparatus 200 is divided into a plurality of block data BDs and DMA-transferred.
Further, the size (block size) of the block data BD gradually decreases, and the size of the last block data BD is the smallest. However, the block size includes the size of the portion corresponding to its own transmission packet. That is, the block size of the head block data BD ₁ is the largest when including the size of the transmission packet (shaded part).

FIG. 5 is a flowchart showing an outline of the communication processing method according to the first embodiment.
An outline of the communication processing method in the first embodiment will be described with reference to FIG.

In the control information setting process (S110), the block size setting unit 222 calculates control information such as a block size and a transfer waiting time, and sets the calculated control information in the control register 221.
Details of S110 will be described separately.

In the data communication process (S120), the data communication unit 210 performs fixed cycle communication.
At each periodic communication cycle, the data communication unit 210 of a specific transmission device 200 transmits a synchronization signal, and the data communication units 210 of other transmission devices 200 receive the synchronization signal. And the data communication part 210 of each transmission apparatus 200 starts communication at the time of transmission / reception of a synchronizing signal. Thereby, each transmission apparatus 200 can communicate in synchronization every period.
The data communication unit 210 sequentially stores the received data (partial data of the periodic data 110) in the buffer 211 from the start of receiving the periodic data 110 until the reception of the periodic data 110 is completed.

In the data transfer process (S130), the DMA transfer unit 220 transfers the periodic data 110 stored in the buffer 211 from the buffer 211 to the memory 230 in a plurality of times according to the control information set in S110.
Details of S130 will be described separately.

In the data processing (S140), the CPU 240 performs predetermined processing on the periodic data 110 transferred to the memory 230.
For example, the CPU 240 generates a response packet for the packet 111 included in the periodic data 110 and stores the generated response packet in the memory 230.
Next, the DMA transfer unit 220 transfers the response packet stored in the memory 230 to the buffer 211.
Then, the data communication unit 210 transmits a response packet to the network 101 when its own transmission order is reached.

  The processing from S120 to S140 is repeatedly executed every communication cycle.

  Next, the control information setting process (S110 in FIG. 5) will be described.

The user sets the data size TD of the periodic data 110 (including the received packet and the transmitted packet), the communication speed TN of the network 101, and the transfer speed TB of the bus 201 in the control register 221.
Also, the user sets the overhead OH _B, overhead OH _M and last block Block Size RD _N control register 221 (or first block block size RD ₁ data) of the data in the memory 230 of the buffer 211.
In addition, the user sets an interrupt notification notification time NT _I and a transfer completion notification notification time NT _E in the control register 221.

The overhead of the buffer 211 is a time required for accessing the buffer 211 (for example, a time for reading block data from the buffer 211).
The overhead of the memory 230 is a time required for accessing the memory 230 (for example, a time for writing block data to the memory 230).
Interrupts The alert notification time NT _I, time needed to notify the interrupt notification to the CPU 240 (e.g., sends an interrupt control circuit 224 generates an interrupt notification, the time for CPU 240 detects the interrupt notification ).
A transfer completion notification NT _E, the transfer control circuit 223 generates and transmits a completion notification transfer, CPU 240 is a time) for detecting a completion notification transfer.

The block size setting unit 222 calculates the following relational expression (1-1) using the above values.
The left side of the relational expression (1-1) means a communication time necessary for receiving data by the i-th block size RD _i .
Further, the right side of the relational expression (1-1) means a transfer time necessary for transferring data by the (i-1) th block size RD _i-1 .

The block size setting unit 222 calculates the first to Nth (last) block size by calculating the relational expression (1-1).
However, the block size setting unit 222 satisfies the relational expression (1-2), that is, the block size so that the total block size (left side) matches the data size TD (right side) of the period data 110. Adjust RD _i . For example, when the next block size is added and the total block size exceeds the data size TD of the period data 110, the surplus data size is added to the block size calculated immediately before. Also, for example, the excess data size is subtracted from the previously calculated block size.

Further, the block size setting unit 222 calculates the following equation (2-1) using the _first block size RD ₁ to calculate the first transfer waiting time WT ₁ . The first transfer waiting time WT ₁ is a communication time necessary for receiving the _first block size RD ₁ .
Further, the block size setting unit 222 calculates the following equation (2-2), and calculates the second and subsequent transfer wait times WT. The i (≠ 1) -th transfer waiting time WT _i is a time required for transferring the (i−1) -th block size RD _i−1 . The (i-1) th block size RD _i-1 is equal to a value obtained by multiplying the (i-1) th transfer waiting time WT _i-1 by the communication speed TN.

  The block size setting unit 222 sets the calculated block size RD and transfer waiting time WT in the control register 221.

FIG. 6 is a flowchart showing the data transfer process (S130) of the transfer control circuit 223 in the first embodiment.
Data transfer processing (FIG. 5, S130) (an example of data transfer processing and transfer completion notification processing) of the transfer control circuit 223 in the first embodiment will be described with reference to FIG.

In S210, when the data communication unit 210 receives the synchronization signal, the data communication unit 210 notifies the transfer control circuit 223 of the reception of the synchronization signal (communication start in the period).
The transfer control circuit 223 refers to the control register 221 and starts a transfer waiting timer in which the first (first) transfer waiting time WT ₁ is set.
The transfer wait timer is a function for notifying a timeout when a set time has elapsed since activation.
That is, the transfer waiting timer in which the first transfer waiting time WT ₁ is set receives partial data of the period data 110 by the first block size RD ₁ from when the data communication unit 210 starts communication in the period. Timeout occurs when the communication time (first transfer waiting time WT ₁ ) necessary for the elapse of time elapses.
It progresses to S220 after S210.

In S220, the transfer control circuit 223 waits until the transfer waiting timer times out.
When the transfer waiting timer times out (YES), the process proceeds to S230.

In S230, the transfer control circuit 223 refers to the control register 221, and determines whether or not the transfer waiting time WT _i set in the transfer waiting timer that has timed out is the last (Nth) transfer waiting time WT _N.
When the transfer waiting time WT _i set in the transfer waiting timer is the last transfer waiting time WT _N (YES), the process proceeds to S260.
When the transfer waiting time WT _i set in the transfer waiting timer is not the last transfer waiting time WT _N (NO), the process proceeds to S240.

In S240, the transfer control circuit 223 starts a transfer waiting timer in which the next transfer waiting time WT _i is set.
The transfer waiting timer in which the i-th transfer waiting time WT _i is set is the transfer time required for transferring the partial data of the period data 110 from the buffer 211 to the memory 230 by the i−1th block size RD _i−1. A timeout occurs when (i-th transfer waiting time WT _i ) has elapsed.
It progresses to S250 after S240.

In S250, the transfer control circuit 223 accesses the buffer 211 and the memory 230, and transfers the partial data of the period data 110 stored in the buffer 211 in the memory 230 as the i-th block data _{D i.} Block data _{D i} transferred to the memory 230 is deleted from the buffer 211.
After S250, the process returns to S220.

In S260, the transfer control circuit 223 accesses the buffer 211 and the memory 230, and transfers the partial data of the period data 110 stored in the buffer 211 in the memory 230 as the block data _{D N} of the last (N th). Block data _{D N,} which is transferred to the memory 230 is deleted from the buffer 211.
It progresses to S270 after S260.

In S270, the transfer control circuit 223 notifies the CPU 240 of a transfer completion notification indicating that the transfer of the periodic data 110 has been completed. In the transfer completion notification, information such as a transfer destination address in the memory 230 and a data size TD of the periodic data 110 is set in order to access the periodic data 110 in the memory 230. These pieces of information are managed using the control register 221.
The CPU 240 completes the predetermined interrupt handler activation process when the transfer completion notification is detected or immediately thereafter. The activation of the interrupt handler will be explained separately.
The CPU 240 operates the interrupt handler when the interrupt handler activation process is completed and a transfer completion notification is detected. The interrupt handler accesses the memory 230 and performs predetermined data processing on the periodic data 110 stored in the memory 230 (S140 in FIG. 5).
By S270, the data transfer process (S130) of the transfer control circuit 223 ends.

FIG. 7 is a flowchart showing the data transfer process (S130) of the interrupt control circuit 224 in the first embodiment.
Data transfer processing (FIG. 5, S130) (an example of interrupt notification processing) of the interrupt control circuit 224 in the first embodiment will be described with reference to FIG.

In S310, the interrupt control circuit 224 waits by the transfer control circuit 223 until the transfer of the block data _{D i} is completed.
For example, the transfer control circuit 223 notifies the interrupt control circuit 224 of the completion of the transfer of the block data D _i when the transfer of the block data D _i (FIG. 6, S250, S260) is completed.
If the transfer of the block data _{D i} is completed (YES), the process proceeds to S320.

In S320, the interrupt control circuit 224 refers to the control register 221, and calculates the transferred block size TD _E. If the transfer of the i-th block data _{D i} is completed, the total value of the block size _RD 1 ~ Rd _i until the first i th is already transferred block size TD _E.
It progresses to S330 after S320.

In S330, the interrupt control circuit 224, the transferred block size TD _E is substituted into the following interrupt notification condition (3), to calculate whether satisfied interrupt notification conditional expression (3).
In the interrupt notification conditional expression (3), “data size TD of periodic data 110−transferred block size TD _E ” is equal to the total value of the remaining block sizes RD.
It progresses to S340 after S330.

If the interrupt notification conditional expression (3) is satisfied in S340 (YES), the process proceeds to S350.
If the interrupt notification conditional expression (3) is not satisfied (NO), the process returns to S310.

In S350, the interrupt control circuit 224 notifies the CPU 240 of an interrupt notification for notifying that the interrupt handler is triggered.
The CPU 240 starts an interrupt handler activation process when detecting an interrupt notification.
By S350, the data transfer process (S130) of the interrupt control circuit 224 ends.

FIG. 8 is a schematic diagram showing a data transfer method according to the first embodiment.
A data transfer method according to the first embodiment will be described with reference to FIG.

It is assumed that the periodic data 110 is transferred from the buffer 211 to the memory 230 in six steps.
The time required for accessing the buffer 211 is “OH _B ”, and the time required for accessing the memory 230 is “OH _M ”.
Further, the transmission time zone assigned to the transmission apparatus 200 is indicated by shading. The time zone other than the shaded time is a time zone for receiving partial data of the periodic data 110 from the other transmission apparatus 200.

  A synchronization signal 120 is communicated at the beginning of a cycle.

The data stored in the buffer 211 until the first (first) transfer waiting time WT ₁ elapses after communication of the synchronization signal 120 is the first block data BD ₁ . The first transfer waiting time WT ₁ is a time required for receiving the partial data of the period data 110 by the initial block size RD ₁ .
The transfer control circuit 223 of the DMA transfer unit 220 transfers the first block data BD ₁ from the buffer 211 to the memory 230 when the first transfer waiting time WT ₁ has elapsed.

The data stored in the buffer 211 from the start of the transfer of the first block data BD ₁ until the second (second) transfer waiting time WT ₂ elapses is the second block data BD ₂ . The second transfer waiting time WT ₂ is a time required for transferring the partial data of the periodic data 110 by the initial block size RD ₁ .
The transfer control circuit 223 of the DMA transfer unit 220 transfers the second block data BD ₂ from the buffer 211 to the memory 230 when the _second transfer waiting time WT ₂ has elapsed.

Thereafter, the processing is repeated until the last (sixth) block data BD ₆ is transferred.
That is, the data stored in the buffer 211 from the start of the transfer of the previous block data BD _i-1 until the current transfer waiting time WT _i elapses is the current block data BD _i . The current transfer waiting time WT _i is a time required to transfer the partial data of the period data 110 by the previous block size RD _i−1 .
The transfer control circuit 223 of the DMA transfer unit 220 transfers the current block data BD _i from the buffer 211 to the memory 230 when the current transfer waiting time WT _i has elapsed.

FIG. 9 is a schematic diagram showing the data transfer method (interrupt notification, transfer completion notification) in the first embodiment, and is an enlarged view of the time zone during which the block data BD ₆ is transferred in FIG.
The interrupt notification time and transfer completion notification time will be described with reference to FIG.

The interrupt control circuit 224 of the DMA transfer unit 220 notifies the CPU 240 of an interrupt notification when the transfer of the block data BD ₅ is completed. However, the interrupt notification conditional expression (3) is satisfied when the transfer of the block data BD ₅ is completed.
In other words, the time is the addition notification time TN _E transfer completion notification to the communication time required for reception of the remaining block data BD ₆ RD _{6 /} TB, the interrupt notification reminder time NT _I to interrupt the startup process to take the processing time of the handler It is equal to or shorter than the time of adding BT.

  The CPU 240 that has detected the interrupt notification starts an interrupt handler activation process.

The transfer control circuit 223 of the DMA transfer unit 220 notifies the CPU 240 of a transfer completion notification when the transfer of the last block data BD ₆ is completed.
The interrupt handler activation process is completed when the CPU 240 detects a transfer completion notification or immediately thereafter.

The CPU 240 detecting the transfer completion notification operates the interrupt handler, and the interrupt handler performs predetermined data processing on the periodic data 110 transferred to the memory 230.
For example, the interrupt handler generates a response packet for each packet 111 included in the periodic data 110 and stores the generated response packet in the memory 230. In this case, the DMA transfer unit 220 transfers the response packet stored in the memory 230 to the buffer 211, and the data communication unit 210 transmits the response packet transferred to the buffer 211 in the next transmission period.

10 and 11 are schematic diagrams showing a conventional data transfer method.
As shown in FIG. 10, in the conventional data transfer method, the periodic data is transferred after all the periodic data is received, and the interrupt notification and the transfer completion notification are performed after all the periodic data transfer is completed.
Further, as shown in FIG. 11, in another conventional data transfer method (see Patent Document 1), periodic data is transferred for each single large block size BD, and interrupted after all block data BDs have been transferred. Notification and transfer completion notification were performed.
On the other hand, in the data transfer method according to the first embodiment (see FIGS. 8 and 9), the periodic data is transferred for each gradually decreasing block size BD, and an interrupt notification is made before the transfer of all the block data BD is completed.
For this reason, the data transfer method according to the first embodiment can complete the DMA transfer of periodic data earlier than the conventional data transfer method.

FIG. 12 is a diagram illustrating an example of hardware resources of the transmission apparatus 200 according to the first embodiment.
In FIG. 12, the transmission apparatus 200 includes a CPU 240. The CPU 240 is connected to the ROM 903, the RAM 904 (an example of the memory 230), the communication board 905 (an example of the data communication unit 210), the display device 911, the keyboard 912, the mouse 913, the drive device 914, and the magnetic disk device 920 via the bus 201. And control these hardware devices. The drive device 914 is a device that reads and writes a storage medium such as an FD (Flexible Disk Drive), a CD (Compact Disc), and a DVD (Digital Versatile Disc).

  The communication board 905 is wired or wirelessly connected to a communication network such as a LAN (Local Area Network), the Internet, or a telephone line.

  The magnetic disk device 920 stores an OS 921 (operating system), a program group 922, and a file group 923.

  The program group 922 includes programs that execute functions described as “˜unit” or “˜handler” in the embodiment. The program is read and executed by the CPU 240. In other words, the program causes the computer to function as “˜unit” or “˜handler”, and causes the computer to execute the procedures and methods of “˜unit” and “˜handler”.

  The file group 923 includes various data (input, output, determination result, calculation result, processing result, etc.) used in “˜part” and “˜handler” described in the embodiment.

  In the embodiment, arrows included in the configuration diagrams and flowcharts mainly indicate input and output of data and signals.

  In the embodiment, what is described as “to part” may be “to circuit”, “to apparatus”, and “to device”, and “to step”, “to procedure”, and “to processing”. May be. That is, what is described as “to part” may be implemented by any of firmware, software, hardware, or a combination thereof.

In the first embodiment, for example, the following communication system 100 has been described.
The communication system 100 includes a plurality of transmission devices 200 connected to an external bus (network 101), and performs communication between the transmission devices 200 at a constant cycle.

The transmission apparatus 200 includes a buffer 211, a CPU 240, a memory 230, and a DMA transfer unit 220.
The buffer 211 holds data when data is transmitted and received, the CPU 240 performs calculations, and the memory 230 is used by the CPU 240.
The DMA transfer unit 220 includes a control register 221, a block size setting unit 222, a transfer control circuit 223, and an interrupt control circuit 224. In the following, the corresponding symbols or symbols are shown in parentheses.
The control register 221 includes a transfer source address, a transfer destination address, a transfer data size (TD), a block data size (RD) obtained by dividing the transfer data, an address offset, a cycle, an external bus transfer speed (TN), and an internal bus transfer. It consists of registers storing the speed (TB), the overhead of the buffer 211 (OH _B ), and the delay value (BT) of the interrupt handler of the CPU 240.
The block size setting unit 222 calculates the block data size based on the transfer data size and the transfer speed of the external / internal bus.
The transfer control circuit 223 divides the transfer data (period data 110) into a plurality of blocks (BD) based on the value of the control register 221, and performs DMA transfer in units of blocks.
The interrupt control circuit 224 notifies the CPU 240 of an interrupt.

The block size setting unit 222 receives the transfer data for the block size based on the transfer speed of the external bus, the transfer speed of the internal bus, the overhead of the buffer 211 and the transfer data size before starting communication. A block data size that completes the transfer of the data read immediately before is set in the control register 221.
The transfer control circuit 223 sequentially reads block data size data from the buffer 211 according to the value of the control register 221 and DMA-transfers the data to the memory 230.

The interrupt control circuit 224 determines that the sum of the transfer time ((TD−TD _E ) / TB) of the remaining transfer data size and the interrupt information transfer time (NT _E ) and the interrupt notification time (NT _I ) When it becomes equal to the sum of the delay value (BT) of the interrupt handler, the CPU 240 is notified of an interrupt factor (interrupt notification).

That is, the DMA transfer unit 220 gradually reduces the block size of the transfer data to be read, thereby reducing the size of the block data to be transmitted last while suppressing the division number (number of blocks) of the transfer data.
Further, the DMA transfer unit 220 notifies the CPU 240 in advance of an interrupt notification during execution of the DMA transfer, and notifies interrupt information (transfer completion notification) when the DMA transfer is completed. And CPU240 will operate | move immediately, if the notification of interruption information is received.
Thereby, the DMA transfer unit 220 can complete the DMA transfer earlier than the conventional technique.

  The transmission apparatus 200 in Embodiment 1 may have the following form.

  The user may calculate the block size and the transfer waiting time, and input the calculated block size and the transfer waiting time to the transmission apparatus 200. The block size setting unit 222 sets the input block size and transfer waiting time in the control register 221.

The block size setting unit 222 may update the block size and the transfer waiting time at regular intervals or whenever transfer of one block data is completed.
For example, the transmission apparatus 200 includes a communication speed calculation unit that calculates the communication speed of the network 101 based on the data size that the data communication unit 210 communicates per unit time. The transmission apparatus 200 also includes a transfer rate calculation unit that calculates the transfer rate of the bus 201 based on the data size transferred per unit time by the transfer control circuit 223. Then, the block size setting unit 222 calculates a new block size and a new transfer waiting time by using the communication speed calculated by the communication speed calculation unit and the transfer speed calculated by the transfer rate calculation unit.

  When the data (for example, response packet) generated by the CPU 240 is DMA-transferred from the memory 230 to the buffer 211, the data transfer method described in the first embodiment may be used.

The transfer control circuit 223 may transfer the partial data from the buffer 211 to the memory 230 when the partial data of the period data 110 is stored in the buffer 211 by the block size, not when the transfer waiting time has elapsed. .
That is, when the partial data is stored in the buffer 211 by the first block size among a plurality of block sizes whose order is determined in advance after the data communication unit 210 starts communication, the transfer control circuit 223 receives the buffer 211. The partial data stored in is transferred to the memory 230. Further, the transfer control circuit 223 transfers the partial data stored in the buffer 211 to the memory 230 when the partial data is stored in the buffer 211 by the next block size.
For example, the transfer control circuit 223 periodically accesses the buffer 211, refers to the data size of the partial data stored in the buffer 211, compares the referenced data size with a predetermined block size, and transfers the partial data. It is determined whether or not to do.

  100 communication system, 101 network, 110 period data, 111 packet, 200 transmission device, 201 bus, 210 data communication unit, 211 buffer, 220 DMA transfer unit, 221 control register, 222 block size setting unit, 223 transfer control circuit, 224 Interrupt control circuit, 230 memory, 240 CPU, 903 ROM, 904 RAM, 905 communication board, 911 display device, 912 keyboard, 913 mouse, 914 drive device, 920 magnetic disk device, 921 OS, 922 program group, 923 file group .

Claims (6)

A memory for storing data;
A communication buffer for storing communication data;
A data communication unit that communicates communication data via a network and stores the received data in the communication buffer as partial data of the communication data from the start of receiving the communication data until the end of receiving the communication data When,
When the communication time required for receiving the partial data by the first block size out of a plurality of block sizes determined in advance from the time when the data communication unit starts communication is stored in the communication buffer. The transfer time required for transferring the stored partial data to the memory as the first block data and transferring the partial data by the previous block size from the start of the transfer of the previous block data. And a data transfer unit that transfers the partial data stored in the communication buffer as new block data to the memory when the time elapses. The communication apparatus according to claim 1, wherein the plurality of block sizes satisfy the following relational expression (A).

The communication device further includes:
CPU (Central Processing Unit) for processing data;
A transfer completion notification unit for notifying the CPU of a transfer completion notification when the data transfer unit has transferred all the partial data to the memory;
An interrupt notification unit that notifies the CPU of an interrupt notification before the transfer completion notification unit notifies the CPU of a transfer completion notification;
The CPU starts an interrupt handler process for processing communication data when the interrupt notification is detected,
The CPU processes the communication data constituted by the partial data transferred to the memory by the interrupt handler when the activation processing of the interrupt handler is completed and the transfer completion notification is detected. The communication apparatus according to claim 1 or 2. 4. The communication according to claim 3, wherein the interrupt notification unit notifies the CPU of an interrupt notification when the partial data is transferred to the memory by a transfer size that satisfies the following relational expression (B). apparatus.

A memory for storing data, a communication buffer for storing communication data, a data communication unit for communicating communication data via a network, and a data transfer unit for transferring communication data stored in the communication buffer to the memory In a data transfer method for a communication device comprising:
The data communication unit stores the received data in the communication buffer as partial data of the communication data until the reception of the communication data after the reception of the communication data is completed.
The data transfer unit transfers the partial data stored in the communication buffer to the memory as initial block data when a predetermined initial transfer waiting time has elapsed since the data communication unit started communication. The time for transferring partial data by the data size obtained by multiplying the previous transfer waiting time by the network communication speed is used as the current transfer waiting time. A data transfer method for a communication apparatus, comprising: transferring the partial data stored in the communication buffer to the memory as current block data when a transfer waiting time elapses. Data communication processing for communicating communication data via a network, the data communication processing for storing the received data in the communication buffer as partial data of the communication data from the start of receiving the communication data until the end of receiving the communication data; ,
When a predetermined first transfer waiting time has elapsed since the start of communication in the data communication process, the partial data stored in the communication buffer is transferred to the memory as first block data, and the previous transfer waiting time The time for transferring partial data by the data size obtained by multiplying the communication speed of the network with this transfer waiting time is the current transfer waiting time, and this transfer waiting time has elapsed since the start of the previous block data transfer. In some cases, the communication program causes the computer to execute data transfer processing for transferring the partial data stored in the communication buffer to the memory as current block data.

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