JP2012114684A - Peak hold circuit and bottom hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the detection accuracy of a peak hold circuit and a bottom hold circuit and keep the detection accuracy of the circuits intact during high temperature operation.SOLUTION: The peak hold circuit includes: a first differential amplification circuit 12 having a first differential input circuit 7 having gates connected with an input terminal 1 and an output terminal 2, respectively, and a first current mirror circuit 10; a fifth transistor 13 for generating a charge current I2 proportional to a current I1 flowing through the first current mirror circuit 10; a sixth transistor 14 having a gate connected to an output node 16 of the first differential amplification circuit 12 and a source and a drain connected to a drain of the fifth transistor 13 and a capacitor 17, respectively; and the capacitor 17 charged with the charge current I2. The charge current I2 is reduced as an output voltage VOUT approaches a peak value of an input signal VIN to implement suppressed overshoot and increased detection accuracy of the peak hold circuit.

Description

  The present invention relates to a peak hold circuit that detects and holds a peak value of an input signal, and a bottom hold circuit that detects and holds a bottom value of an input signal.

  For example, in a sensor of a vehicle-mounted device, the sensor signal changes with time, so that it is necessary to correct or control the sensor signal using a peak hold circuit. In order to accurately correct or control the sensor signal, it is necessary to accurately detect the peak value of the sensor signal. For this reason, the peak hold circuit needs to detect the peak value of the sensor signal with high accuracy. In-vehicle equipment must maintain its accuracy even in high-temperature operation.

  For example, Patent Document 1 discloses an example in which a peak value is accurately detected by a peak hold circuit. The peak hold circuit of Patent Document 1 includes a first transistor in which an input signal voltage is applied to a gate, an output voltage is applied to a gate, and a source is connected in common with the first transistor, so that a constant current is supplied from a constant current source. A differential amplifier composed of a second transistor to be distributed, a current equal to the drain current of the second transistor, which is proportional to the current flowing through the load of the first current mirror circuit and the first transistor. And a capacitor charged by the charging current, and the terminal voltage of the capacitor is used as the output voltage.

  In the invention described in Patent Document 1, when the input signal voltage is higher than the peak voltage (output voltage) held in the capacitor, a charging current flows in the capacitor. This charging current is generated by the second current mirror circuit, and its magnitude is the current obtained by subtracting the current flowing through the second transistor from the current flowing through the first transistor of the differential amplifier, that is, the load of the second transistor. Therefore, the difference between the input voltage and the output voltage becomes smaller, that is, the output voltage becomes smaller as it approaches the input signal voltage by charging. When the output voltage becomes equal to the input signal voltage, the currents flowing through the first and second transistors of the differential amplifier become equal, so the charging current becomes zero. As described above, in the invention described in Patent Document 1, since the charging current approaches 0 as the capacitor is charged, the output voltage does not exceed the peak value of the input signal voltage, and the peak value of the peak hold circuit is accurately detected. can do.

  For example, Patent Document 2 discloses an example in which a peak value is accurately detected by a peak hold circuit. The peak hold circuit of Patent Document 2 includes a capacitor, a current source that charges or discharges the capacitor, a switch that connects the current source to the capacitor, a potential of a connection node between the switch and the capacitor, and an input A comparator for opening and closing the switch according to a result of the comparison, a buffer for a connection node between the switch and the capacitor, a buffer for outputting an output signal, and a potential for the output signal And the potential of the input signal, and the current source is braked so that the current flowing through the current source decreases as the potential difference between the potential of the input signal and the potential of the output signal decreases. A semiconductor integrated circuit device comprising a peak or bottom detection circuit including a brake.

  In the invention described in Patent Document 2, the potential of the output signal is compared with the potential of the input signal so that the current flowing through the current source decreases as the potential difference between the potential of the input signal and the potential of the output signal decreases. A brake is provided for braking the current source. For this reason, the charge current to the capacitor can be reduced as the difference between the output signal and the input signal becomes smaller.

  In this way, if the charge current is reduced as the difference between the output signal and the input signal becomes smaller, the charge to the capacitor can be terminated more quickly at a more reliable timing than in the conventional case where the charge current is not controlled. it can. Therefore, a phenomenon that the output signal exceeds the peak level of the input signal is less likely to occur, and the accuracy of the peak hold circuit is greatly improved.

Japanese Patent Laid-Open No. 7-22924 JP 2000-131352 A

  In the invention described in Patent Document 1, in order to detect the peak value, the second current mirror circuit that generates a charging current having a magnitude proportional to the current flowing through the load of the first transistor is charged by the charging current. Connected to the capacitor. During high temperature operation, the leakage current of the second current mirror circuit connected to the capacitor increases. When the leakage current flowing through the second current mirror circuit that increases during high-temperature operation flows in the ground direction, the voltage charged in the capacitor charged by the charging current after detection of the peak value, that is, the output voltage is the second current mirror circuit It gradually decreases with the increase of the leakage current flowing in the ground direction.

  Further, when the leakage current flowing through the second current mirror circuit that increases during high temperature operation flows from the voltage source, the voltage charged in the capacitor charged by the charging current after the peak value is detected, that is, the output voltage flows from the voltage source. However, it gradually increases as the leakage current of the second current mirror circuit increases. Further, when peak value detection is performed at high speed, it is necessary to increase the area of the transistor of the second current mirror circuit and increase the charging current in proportion to the current flowing through the load of the first transistor. However, when the area of the transistor of the second current mirror circuit is increased, the leakage current generated during high temperature operation further increases. Thus, the output voltage increases or decreases due to the leakage current of the second current mirror circuit that increases during high-temperature operation, and the accuracy of detecting the peak value of the peak hold circuit deteriorates.

  In the invention described in Patent Document 2, in order to improve the accuracy of the peak hold circuit, the potential of the connection node between the switch and the capacitor is buffered, the buffer for outputting the output signal, the potential of the output signal, and the potential of the input signal are In comparison, a brake is provided for braking the current source so that the current flowing through the current source becomes smaller as the potential difference between the potential of the input signal and the potential of the output signal becomes smaller. However, the circuit area of the peak hold circuit is expanded by using a buffer and a brake for outputting an output signal.

  Further, in the invention described in Patent Document 2, when an offset voltage is generated in a buffer that outputs an output signal due to process variations, a difference occurs between an output voltage charged in a capacitor and an output voltage obtained by buffering the voltage. The accuracy of detecting the peak value of the circuit is degraded. Further, the output of the brake that compares the input signal and the output signal is affected by the offset voltage generated in the buffer that outputs the output signal, and an error occurs in the amount of current flowing through the current source, and the peak value of the peak hold circuit is detected. Accuracy deteriorates. Furthermore, if an offset voltage occurs due to process variations in the brake that compares the input signal and the output signal, as in the buffer that outputs the output signal, an error occurs in the amount of current flowing through the current source and the peak value of the peak hold circuit is detected. The accuracy of the performance will deteriorate.

  The object of the present invention is to solve the above problems, improve the accuracy of detecting the peak value of the peak hold circuit, suppress the deterioration in accuracy of detecting the peak value that occurs in high temperature operation, and further reduce the circuit area. It is to provide a circuit.

  Another object of the present invention is to solve the above problems, improve the accuracy of detecting the bottom value of the bottom hold circuit, suppress the deterioration of accuracy of detecting the bottom value that occurs in high temperature operation, and further reduce the circuit area. It is to provide a bottom hold circuit.

The peak hold circuit according to the present invention is a peak hold circuit that detects and holds a voltage equal to the peak value of the input signal and then outputs it as an output voltage.
A first transistor to which an input signal is applied to the gate; a second transistor to which an output voltage is applied to the gate and a source is commonly connected to the source of the first transistor and receives a constant current from a constant current source; A first differential input circuit comprising:
A first current mirror circuit for flowing a current equal to a current flowing through the drain of the second transistor into the drain of the first transistor;
A third transistor having a gate connected to the drain of the second transistor and generating a charging current proportional to the current flowing through the drain of the second transistor;
A fourth transistor having a gate connected to the drain of the first transistor, a source connected to the drain of the third transistor, and a drain connected to the capacitor;
A capacitor having one end connected to an output terminal and charged by the charging current;
The terminal voltage of the capacitor is used as an output voltage.

  Therefore, according to the present invention, the output voltage exceeds the peak value or bottom value of the input signal by reducing the charging current or discharging current that charges or discharges the capacitor as the output voltage approaches the peak value of the input voltage. The detection accuracy of the peak hold circuit can be greatly improved.

It is a circuit diagram which shows the peak hold circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the 1st cascode type | mold current mirror circuit 40 provided in the peak hold circuit which concerns on the modification of Embodiment 1 of this invention. FIG. 3 is a voltage and current waveform diagram showing the operation of the peak hold circuit of FIGS. 1 and 2. 3 is a characteristic diagram showing a temperature characteristic of a current I3 flowing in a capacitor 17 when the output voltage VOUT> the input voltage VIN in the peak hold circuit of FIGS. 1 and 2. FIG. It is a circuit diagram which shows the bottom hold circuit based on Embodiment 2 of this invention. FIG. 6 is a voltage and current waveform diagram showing the operation of the bottom hold circuit of FIG. 5. It is a circuit diagram which shows the bottom hold circuit based on Embodiment 3 of this invention. FIG. 6 is a circuit diagram showing a first cascode current mirror circuit 46 provided in a peak hold circuit according to a modification of the first embodiment of the present invention. FIG. 9 is a voltage and current waveform diagram illustrating the operation of the bottom hold circuit of FIGS. 7 and 8.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. The following circuit is an example of the circuit, and is not limited thereto.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a peak hold circuit according to Embodiment 1 of the present invention. The peak hold circuit according to the first embodiment shown in FIG. 1 is a circuit that detects and holds the peak value of the input signal (input voltage) VIN, and then outputs it as the output voltage VOUT, as shown in FIG. The differential amplifier circuit 12, two transistors 13 and 14, a capacitor 17 for charging the output voltage VOUT, and a constant voltage source 18 are provided. Here, the first differential amplifier circuit 12 includes a first differential input circuit 7 and a first current mirror circuit 10.

The first differential input circuit 7 constituting the first differential amplifier circuit 12 is:
(A) a first transistor 5 to which an input signal VIN is applied to a gate;
(B) a second transistor 6 having an output voltage VOUT applied to the gate and a source commonly connected to the source of the first transistor 5;
(C) A constant current source 11 connected to a commonly connected source of the first transistor 5 and the second transistor 6 is provided. One end of the constant current source 11 is connected to the sources of the first and second transistors 5 and 6, while the other end is connected to the ground.

Further, the first current mirror circuit 10 constituting the first differential amplifier circuit 12 includes:
(A) The source is connected to the voltage source 3 of the voltage V _DD , the drain is connected to the drain of the first transistor 5 constituting the first differential input circuit 7, and the gate is connected to the fourth transistor 9. A third transistor 8 commonly connected to the gate and drain;
(B) The source is connected to the voltage source 3, and the commonly connected gate and drain are connected to the drain of the second transistor 6 and the gate of the third transistor 8 constituting the first differential input circuit 7. And a fourth transistor 9 to be connected.

  Further, the fifth transistor 13 has a source connected to the voltage source 3, a gate connected to the drain of the second transistor 6 constituting the first differential input circuit 7, and the second transistor 13. The charging current I2 proportional to the current I1 flowing through the drain of the transistor 6 is generated at the drain. The gate of the sixth transistor 14 is connected to the drain (node 16) of the one transistor 5 constituting the first differential input circuit 7, and the source thereof is connected to the drain of the fifth transistor 13. The drain is connected to the output terminal 2. Note that a drain node 16 of the first transistor 5 constituting the first differential input circuit 7 is an output node of the first differential amplifier circuit 12.

  The capacitor 17 charges the output voltage VOUT, and one end of each is connected to the output terminal 2 and the constant voltage source 18. Here, the constant voltage source 18 is provided to fix one end of the capacitor 18 connected to the constant voltage source 18 to a predetermined potential (for example, a positive potential), and the one end may be connected to the ground 4. It is sufficient if the potential can be fixed.

  FIG. 2 is a circuit diagram showing a first cascode current mirror circuit 40 provided in a peak hold circuit according to a modification of the first embodiment of the present invention. The first current mirror circuit 10 can implement the peak hold circuit shown in FIG. 1 even with the first cascode current mirror circuit 40 shown in FIG.

The first cascode current mirror circuit 40 shown in FIG.
(A) A seventh transistor whose source is connected to the voltage source 3, whose gate is commonly connected to the gate of the eighth transistor 37 and the drain of the tenth transistor 39, and whose drain is connected to the source of the ninth transistor 38. 36,
(B) The source is connected to the voltage source 3, the gate is commonly connected to the drain of the tenth transistor 39 and the gate of the seventh transistor 36, and the drain is connected to the source of the tenth transistor 39. An eighth transistor 37;
(C) The source is connected to the drain of the seventh transistor 36, the gate is connected to the gate of the tenth transistor 39 and the constant voltage source 41, and the drain constitutes the first differential input circuit 7. A ninth transistor 38 connected to the drain of the first transistor 5;
(D) The source is connected to the drain of the eighth transistor 37, the gate is connected to the gate of the ninth transistor 38 and the constant voltage source 41, and the drain is connected to the gate of the eighth transistor 37 and the first transistor. And a tenth transistor 39 connected to the drain of the second transistor 6 constituting the differential input circuit 7, and a current equal to the current I 1 flowing through the drain of the second transistor 6 is It flows to the drain of the first transistor 5.

  FIG. 3 is a voltage and current waveform diagram showing the operation of the peak hold circuit of FIGS. The operation of the circuit will be described with reference to FIG. As shown in FIG. 3, the output voltage VOUT charges the peak value of the input signal VIN until time t1, and detects the peak value of the input signal VIN at time t1. Until the time t1, when the output voltage VOUT is smaller than the voltage of the input signal VIN, the voltage of the output node 16 of the first differential amplifier circuit 12, that is, the voltage applied to the gate of the sixth transistor 14 gradually increases. The sixth transistor 14 is gradually turned off. At this time, since the sixth transistor 14 is gradually turned off until time t1, the drain voltage of the fifth transistor 13 gradually approaches the voltage of the voltage source 3, and the voltage of the voltage source 3 is reached at time t1. It becomes. Therefore, until the time t1, the sixth transistor 14 is gradually turned off, so that the drain voltage of the fifth transistor 13 gradually approaches the voltage source 3, and between the drain and source of the fifth transistor 13 The voltage decreases, and the charging current I2 flowing through the drain of the fifth transistor 13 gradually decreases. At time t1, the charging current I2 becomes zero. Thus, until the time t1, as the output voltage VOUT approaches the peak value of the input signal VIN, the sixth transistor 14 is gradually turned off, and the charging current I2 is reduced to charge the capacitor 17. Overshooting can be prevented, and the accuracy of detecting the peak value of the peak hold circuit is improved.

  FIG. 4 is a characteristic diagram showing the temperature characteristics of the current I3 flowing through the capacitor 17 when the output voltage VOUT> the input voltage VIN in the peak hold circuit of FIGS. In the peak hold circuit of FIG. 1, after detecting the peak value of the input signal VIN (after time t1), the sixth transistor 14 is turned off, and the temperature is increased by disconnecting the capacitor 17 and the fifth transistor 13. As shown in FIG. 4, when the output voltage VOUT is higher than the input signal VIN and the sixth transistor 14 is present, as shown in FIG. Since the current I3 flowing through the capacitor 17 can be reduced as compared with the case where there is no 14, the deterioration of the accuracy of detecting the peak value of the peak hold circuit during high temperature operation can be suppressed.

  Further, the output voltage VOUT is detected by increasing the fifth transistor 13 that generates the charging current I2 proportional to the current I1 flowing through the first current mirror circuit 10 in order to detect the peak value at a high speed. Even if I2 is increased, the use of the sixth transistor 14 does not affect the leakage current of the fifth transistor 13 after detection of the peak value. Therefore, the peak hold circuit according to the present embodiment is not affected by the fifth transistor 13 even when the peak value is detected at high speed during high-temperature operation, and thus suppresses deterioration in accuracy of detecting the peak value. can do.

  Further, in the peak hold circuit according to the present embodiment, the first current mirror circuit 10 is used without using a buffer that outputs an output signal of Patent Document 2 or a brake that applies braking so as to reduce a current flowing through a current source. The accuracy of the peak hold circuit is improved by using the fifth transistor 13 connected to the node 15 and the sixth transistor 14 that gradually approaches the OFF state as the output voltage VOUT approaches the voltage of the input signal VIN. Can do. Therefore, in the peak hold circuit according to the present embodiment, it is possible to eliminate deterioration in accuracy of the peak hold circuit due to the output voltage of the buffer and the brake and the offset voltage of the brake, which are caused by process variations, which is a problem in Patent Document 2, and further reduce the circuit area. Can be reduced.

Embodiment 2. FIG.
FIG. 5 is a circuit diagram showing a bottom hold circuit according to the second embodiment of the present invention. The bottom hold circuit of the second embodiment shown in FIG. 5 is a circuit that detects and holds the bottom value of the input signal (input voltage) VIN and then outputs it as the output voltage VOUT. As shown in FIG. This can be realized with a block configuration substantially similar to the peak hold circuit of FIG. Here, in order to enable bottom value detection, a circuit that reverses the flow direction of the charging current I2 of the peak hold circuit is added. The bottom hold circuit includes a differential amplifier circuit 12, two transistors 19 and 23 having different polarities, a current mirror circuit 22, a capacitor 17 that discharges an output voltage VOUT, and a constant voltage source 18. The

  In FIG. 5, the first differential amplifier circuit 12 is configured in the same manner as the first differential amplifier circuit 12 of FIG. The fifth transistor 19 has its source connected to the voltage source 3 and its gate connected to the drain of the second transistor 6 constituting the same first differential input circuit 7 as in the first embodiment. A current I4 proportional to the current I1 flowing through the drain of the second transistor 6 is generated.

Furthermore, the second current mirror circuit 22
(A) a sixth transistor 20 whose source is connected to the ground 4 and whose drain and gate are connected to the drain of the fifth transistor 19;
(B) a seventh transistor 21 having a source connected to the ground 3, a gate commonly connected to the gate and drain of the sixth transistor 20, and a drain connected to the source of the eighth transistor 23. Then, a discharge current I5 proportional to the current I4 flowing through the fifth transistor 19 is generated at the drain of the seventh transistor 21.

  The eighth transistor 23 has its gate connected to the drain (node 16) of the first transistor 5 constituting the first differential input circuit 7, and its source connected to the drain of the seventh transistor 21. The drain is connected to the output terminal 2. One end of each capacitor 17 is connected to the output terminal 2 and the constant voltage source 18. Note that one end of the capacitor 17 connected to the constant voltage source 18 may be connected to the ground 4 as long as the potential can be fixed.

  FIG. 6 is a voltage and current waveform diagram showing the operation of the bottom hold circuit of FIG. The operation of the circuit will be described with reference to FIG. As shown in FIG. 6, the output voltage VOUT discharges the bottom value of the input signal VIN until time t1, and detects the bottom value of the input signal VIN at time t1. Until the time t1, when the output voltage VOUT is larger than the voltage of the input signal VIN, the voltage applied to the output node 16 of the first differential amplifier circuit 12, that is, the gate of the eighth transistor 23 is gradually lowered. 8 transistor 23 is gradually turned off. At this time, since the eighth transistor 23 is gradually turned off until time t1, the drain voltage of the seventh transistor 21 gradually approaches the ground potential, and becomes the ground potential at time t1. Accordingly, until the time t1, the eighth transistor 23 is gradually turned off, so that the drain voltage of the seventh transistor 21 gradually approaches the ground potential, and the voltage between the source and drain of the seventh transistor 21 is increased. Gradually approaches zero, the discharge current I5 flowing through the drain of the seventh transistor 21 gradually decreases, and the discharge current I5 becomes zero at time t1. In this way, until the time t1, the eighth transistor 23 is gradually turned off as the output voltage VOUT approaches the bottom value of the input signal VIN, and the discharge current I5 is reduced to discharge the capacitor 17. Overshooting can be prevented.

  In the present embodiment, after the bottom value of the input signal VIN is detected, the eighth transistor 23 is turned off, and the output terminal 2 and the seventh transistor 21 are disconnected, so that the temperature increases as the temperature increases. 7 can be prevented from being affected by the leakage current of the transistor 21, and deterioration in accuracy of detecting the bottom value of the bottom hold circuit during high-temperature operation can be suppressed.

Embodiment 3 FIG.
FIG. 7 is a circuit diagram showing a bottom hold circuit according to Embodiment 3 of the present invention. The bottom hold circuit according to the third embodiment shown in FIG. 7 is a circuit that detects and holds the bottom value of the input signal (input voltage) VIN and then outputs it as the output voltage VOUT, as shown in FIG. This can be realized with a block configuration substantially similar to the peak hold circuit of FIG. However, in order to enable bottom value detection, a block whose circuit is changed to have a polarity opposite to that of peak detection is provided. Further, the bottom hold circuit can be realized with a smaller number of components than the bottom hold circuit of FIG. 5, and the circuit area can be reduced. Further, by reversing the polarity of the transistor of the first differential input circuit 7 of the bottom hold circuit of FIG. 5, the influence of the threshold value of the transistor can be alleviated, and input from the bottom hold circuit of the second embodiment of FIG. A bottom value with a low signal VIN can be detected.

The bottom hold circuit according to the third embodiment shown in FIG. 7 includes a differential amplifier circuit 31, two transistors 33 and 34, a capacitor 17 that discharges the output voltage VOUT, and a constant voltage source 18. The In FIG. 7, a first differential amplifier circuit 31 is a circuit in which the polarity of the first differential amplifier circuit 12 in FIG. 1 is reversed, and a first current similar to that of the first differential input circuit 26. The mirror circuit 30 is used. In addition, the first differential input circuit 26 constituting the first differential amplifier circuit 31 includes:
(A) a first transistor 24 to which an input signal VIN is applied to a gate;
(B) a second transistor 25 having an output voltage VOUT applied to the gate and a source commonly connected to the source of the first transistor 24;
(C) A constant current source 27 connected to the commonly connected sources of the first transistor 24 and the second transistor 25 is provided.

The first current mirror circuit 30 constituting the first differential amplifier circuit 31 includes:
(A) The source is connected to the ground 4, the drain is connected to the drain of the first transistor 24 constituting the first differential input circuit 26, and the gate is common to the gate and drain of the fourth transistor 29. A third transistor 28 connected;
(B) The source is connected to the ground 4, and the gate and the drain are connected in common, and the drain of the second transistor 25 and the gate of the third transistor 28 constituting the first differential input circuit 26 are connected. And a fourth transistor 29.

  The fifth transistor 33 has a source connected to the ground 4, a gate connected to the drain of the second transistor 25 constituting the first differential input circuit 26, and the first differential input. A discharge current I7 proportional to the current I6 flowing through the drain of the second transistor 25 constituting the circuit 26 is generated. The sixth transistor 34 has a gate connected to the drain of the first transistor 24 constituting the first differential input circuit 26, and a source connected to the drain of the fifth transistor 33. The drain is connected to the output terminal 2. Note that the node 32 of the gate of the sixth transistor 34 connected to the drain of the first transistor 24 constituting the first differential input circuit 26 is the output of the first differential amplifier circuit 31. It is a node. Further, the capacitor 17 discharges the output voltage VOUT, and one end of each is connected to the output terminal 2 and the constant voltage source 18. Note that one end of the capacitor 17 connected to the constant voltage source 18 may be grounded as long as the potential can be fixed.

  FIG. 8 is a circuit diagram showing a first cascode current mirror circuit 46 provided in a peak hold circuit according to a modification of the first embodiment of the present invention. The first current mirror circuit 30 can be realized by the first cascode current mirror circuit 46 shown in FIG. 8 as well as the bottom hold circuit shown in FIG.

The first cascode current mirror circuit 46 shown in FIG.
(A) A seventh transistor 42 whose source is connected to the ground 4, whose gate is commonly connected to the gate of the eighth transistor 43 and the drain of the tenth transistor 45, and whose drain is connected to the source of the ninth transistor 44. When,
(B) A source connected to the ground 4, a gate connected in common to the drain of the tenth transistor 45 and the gate of the seventh transistor 42, and a drain connected to the source of the tenth transistor 45. 8 transistors 43;
(C) The source is connected to the drain of the seventh transistor 42, the gate is connected to the gate of the tenth transistor 45 and the constant voltage source 47, and the drain constitutes the first differential input circuit 26. A ninth transistor 44 connected to the drain of the first transistor 24;
(D) The source is connected to the drain of the eighth transistor 43, the gate is connected to the gate of the ninth transistor 44 and the constant voltage source 47, and the drain is connected to the gate of the eighth transistor 43 and the first transistor. And a tenth transistor 45 connected to the drain of the second transistor 25 constituting the differential input circuit 26, and a current equal to the current I6 flowing through the drain of the second transistor 25 is It flows to the drain of the first transistor 24.

  FIG. 9 is a voltage and current waveform diagram showing the operation of the bottom hold circuit of FIGS. The operation of the circuit will be described with reference to FIG. As shown in FIG. 9, the output voltage VOUT discharges the bottom value of the input signal VIN until time t1, and detects the bottom value of the input signal VIN at time t1. Until the time t1, when the output voltage VOUT is larger than the voltage of the input signal VIN, the voltage applied to the output node 32 of the first differential amplifier circuit 31, that is, the gate of the sixth transistor 34 gradually decreases, 6 transistor 34 is gradually turned off. At this time, since the sixth transistor 34 is gradually turned off until the time t1, the drain voltage of the fifth transistor 33 gradually approaches the potential of the ground 4 and becomes the potential of the ground 4 at the time t1. . Therefore, until the time t1, the sixth transistor 34 is gradually turned off, so that the drain voltage of the fifth transistor 33 gradually approaches the potential of the ground 4, and the drain-source connection between the fifth transistor 33 and the source is completed. And the discharge current I7 flowing through the drain of the fifth transistor 33 gradually decreases. At time t1, the discharge current I7 becomes zero. In this way, until the time t1, the sixth transistor 34 is gradually turned off as the output voltage VOUT approaches the bottom value of the input signal VIN, and the discharge current I7 is reduced to discharge the capacitor 17. Overshooting can be prevented.

  In the third embodiment, as in the peak hold circuit of FIG. 1, after detecting the bottom value of the input signal VIN, the sixth transistor 34 is turned off, and the output terminal 2 and the fifth transistor 33 are disconnected. Thus, it is possible to eliminate the influence of the leakage current of the fifth transistor 33 that increases as the temperature increases, and it is possible to suppress deterioration in accuracy of detecting the bottom value of the bottom hold circuit during high-temperature operation.

  As described above in detail, according to the present invention, the output voltage is reduced by reducing the charging current or discharging current that charges or discharges the capacitor as the output voltage approaches the peak value or the bottom value of the input voltage. The detection accuracy of the peak hold circuit or the bottom hold circuit can be greatly improved without exceeding the peak value or the bottom value.

  Further, by using the fourth transistor that is gradually turned off in accordance with the drain voltage of the first transistor, a leakage current generated in the third transistor that increases as the temperature increases is charged in the capacitor. Alternatively, after removing the influence on the discharged output voltage (VOUT) and detecting the peak value or bottom value of the input signal (VIN), the leakage current flowing through the capacitor is reduced, so that the peak of the input signal during high temperature operation Degradation of the detection accuracy of the value or the bottom value can be suppressed.

  Further, the second current mirror circuit is used to generate a discharge current proportional to the charging current, and the discharge current discharged to the capacitor as the output voltage approaches the bottom value of the input voltage using the fifth transistor. By making it small, the output voltage does not exceed the bottom value of the input signal, and the accuracy of the bottom hold circuit can be greatly improved.

  DESCRIPTION OF SYMBOLS 1 Input terminal, 2 Output terminal, 3 Voltage source, 4 Ground, 5 1st transistor, 6 2nd transistor, 7 1st differential input circuit, 8 3rd transistor, 9 4th transistor, 10 4th transistor 2 comprises a first current mirror circuit, 11 constant current source, 12 first current mirror circuit 10 and first differential input circuit 7 for flowing a current equal to the drain current I1 of the transistor 6 to the first transistor 5. First differential amplifier circuit, 13 Fifth transistor for generating a charging current I2 proportional to the current I1 flowing through the first current mirror circuit 10, and 14 gate at the output node 16 of the first differential amplifier circuit 12 The sixth transistor to be connected, 15 the node of the first current mirror circuit 10, 16 the output node of the first differential amplifier circuit 12, and 17 the output terminal 2 A capacitor to be connected, 18 constant voltage source, 19 a fifth transistor that generates a current I4 proportional to a current I1 flowing through the first current mirror circuit 10, 20 a sixth transistor, 21 a seventh transistor, 22 a second transistor Current mirror circuit, 23 8th transistor whose gate is connected to the output node 16 of the first differential amplifier circuit 12, 24 1st transistor, 25 2nd transistor, 26 1st differential input circuit, 27 constant current source, 28 third transistor, 29 fourth transistor, 30 first current mirror circuit, 31 first differential amplifier circuit, 32 output node of first differential amplifier circuit 31, 33 first A fifth transistor for generating a discharge current I7 proportional to a current I6 flowing through the current mirror circuit 30 and a gate of the first differential amplifier 34 Sixth transistor connected to output node 32 of width circuit 31, 35 Node of first current mirror circuit 30, 36 Seventh transistor, 37 Eighth transistor, 38 Ninth transistor, 39 Tenth transistor 40 first cascode current mirror circuit, 41 constant voltage source, 42 seventh transistor, 43 eighth transistor, 44 ninth transistor, 45 tenth transistor, 46 first cascode current mirror circuit, 47 Constant voltage source.

Claims (9)

After detecting and holding a voltage equal to the peak value of the input signal, in the peak hold circuit that outputs as the output voltage,
A first transistor to which an input signal is applied to the gate; a second transistor to which an output voltage is applied to the gate and a source is commonly connected to the source of the first transistor and receives a constant current from a constant current source; A first differential input circuit comprising:
A first current mirror circuit for flowing a current equal to a current flowing through the drain of the second transistor into the drain of the first transistor;
A third transistor having a gate connected to the drain of the second transistor and generating a charging current proportional to the current flowing through the drain of the second transistor;
A fourth transistor having a gate connected to the drain of the first transistor, a source connected to the drain of the third transistor, and a drain connected to the capacitor;
A capacitor having one end connected to an output terminal and charged by the charging current;
A peak hold circuit using a terminal voltage of the capacitor as an output voltage.   After detecting the peak value of the input signal, charging is performed in proportion to the current flowing through the drain of the second transistor by using the fourth transistor that is gradually turned off according to the voltage of the drain of the first transistor. 2. The peak hold circuit according to claim 1, further comprising means for suppressing an influence of a leakage current generated in the third transistor that generates a current on the capacitor.   3. The peak hold circuit according to claim 1, wherein the other end of the capacitor is connected to the ground, or connected to a constant voltage source that fixes the other end to a predetermined potential. After detecting and holding a voltage equal to the bottom value of the input signal, in the bottom hold circuit that outputs as the output voltage,
A first transistor to which an input signal is applied to the gate; a second transistor to which an output voltage is applied to the gate and a source is commonly connected to the source of the first transistor and receives a constant current from a constant current source; A first differential input circuit comprising:
A first current mirror circuit for flowing a current equal to a current flowing through the drain of the second transistor into the drain of the first transistor;
A third transistor having a gate connected to the drain of the second transistor and generating a discharge current proportional to the current flowing through the drain of the second transistor;
A fourth transistor having a gate connected to the drain of the first transistor, a source connected to the drain of the third transistor, and a drain connected to the capacitor;
A capacitor having one end connected to the output terminal and discharged by the discharge current;
A bottom hold circuit using the terminal voltage of the capacitor as an output voltage.   After detecting the bottom value of the input signal, a discharge proportional to the current flowing through the drain of the second transistor using the fourth transistor that is gradually turned off according to the voltage of the drain of the first transistor. 5. The bottom hold circuit according to claim 4, further comprising means for suppressing an influence exerted on the capacitor by a leakage current generated in the third transistor that generates a current.   6. The bottom hold circuit according to claim 4, wherein the other end of the capacitor is connected to a ground, or connected to a constant voltage source that fixes the other end to a predetermined potential. After detecting and holding a voltage equal to the bottom value of the input signal, in the bottom hold circuit that outputs as the output voltage,
A first transistor having an input signal applied to the gate, and a second transistor having an output voltage applied to the gate and a source commonly connected to the source of the first transistor and receiving a constant current from a constant current source. A first differential input circuit comprising:
A current mirror circuit for flowing a current equal to a current flowing through the drain of the second transistor into the drain of the first transistor;
A third transistor having a gate connected to the drain of the second transistor and generating a current proportional to the current flowing through the drain of the second transistor;
A second current mirror circuit for generating a discharge current in the drain of the fourth transistor proportional to the current flowing in the drain of the third transistor;
A fifth transistor having a gate connected to the drain of the first transistor, a source connected to the drain of the fourth transistor, and a drain connected to the capacitor;
A capacitor connected at one end to an output terminal and discharged by a discharge current flowing through the drain of the fourth transistor;
A bottom hold circuit using the terminal voltage of the capacitor as an output voltage.   After detecting the bottom value of the input signal, a discharge proportional to the current flowing through the drain of the second transistor using the fourth transistor that is gradually turned off according to the voltage of the drain of the first transistor. 8. The bottom hold circuit according to claim 7, further comprising means for suppressing an influence of a leakage current generated in the third transistor that generates a current on the capacitor.   9. The bottom hold circuit according to claim 7, wherein the other end of the capacitor is connected to a ground, or connected to a constant voltage source that fixes the other end to a predetermined potential.

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