JP2012114367A - Amorphous oxide thin film including tin and thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor that is suited to a display panel and has a good transistor characteristic.SOLUTION: An amorphous oxide thin film contains at least tin (Sn), and in the amorphous oxide thin film, a percentage of SnO is less than 30 mol%, when sum of SnO and SnOis set to 100 mol%.

Description

  The present invention relates to an amorphous oxide thin film, a thin film transistor having the same, and a method for manufacturing the same.

  Field effect transistors are widely used as unit electronic elements, high frequency signal amplifying elements, liquid crystal driving elements and the like of semiconductor memory integrated circuits, and are the most widely used electronic devices at present.

  Among them, with the remarkable development of display devices in recent years, not only liquid crystal display devices (LCD) but also various display devices such as electroluminescence display devices (EL) and field emission displays (FED) are driven by display elements. Thin film transistors (TFTs) are frequently used as switching elements for driving a display device by applying a voltage.

  In addition, silicon-based semiconductors are widely used as the material. Generally, crystalline silicon is used for high-frequency amplifying elements and integrated circuit elements that require high-speed operation, and for liquid crystal driving elements and the like. Amorphous silicon is used because of the demand for large area.

  However, when crystallizing silicon, for example, high temperature of 800 ° C. or higher or heating with an excimer laser is required, and it is difficult to construct a large-area substrate, and a large amount of energy and number of steps are required for manufacturing. There was a problem such as. Furthermore, since crystal silicon is usually limited to the top gate configuration of TFT elements, it has been difficult to reduce costs such as reducing the number of masks.

On the other hand, an amorphous silicon semiconductor (amorphous silicon) that can be formed at a relatively low temperature has a mobility (field effect mobility) as small as about 0.5 cm ² / Vs, and has a lower switching speed than a crystalline one. For this reason, it may not be possible to follow the display of a large screen, high definition, high frequency video. In addition, field effect transistors using amorphous silicon have low stability (reliability) against direct current stress, and are difficult to apply to driving self-luminous display elements such as organic EL that drive direct current. there were.

  Currently, as a switching element for driving a display device, an element using a silicon-based semiconductor film occupies the mainstream, but it has a high switching speed in addition to the stability and workability of a silicon thin film. This is because various performances are good. Such silicon-based thin films are generally manufactured by a chemical vapor deposition (CVD) method.

  Further, a conventional thin film transistor (TFT) has a gate electrode, a gate insulating layer, a semiconductor layer such as hydrogenated amorphous silicon (a-Si: H), a source and a drain electrode on a substrate such as glass. There is a stacked inverted staggered structure, and it is used as a driving element for a flat panel display typified by an active matrix liquid crystal display in the field of large area devices including image sensors. In these applications, even those using amorphous silicon have been required to operate at higher speeds with higher functionality (large screen, high definition, and high frequency).

Under such circumstances, an oxide semiconductor using an oxide has attracted attention as a semiconductor that can be expected to satisfy both transistor performance (mobility and stability) and a large area.
However, among these oxide semiconductors, those using conventional zinc oxide have a low mobility, a low on / off ratio, a large leakage current, an unclear pinch-off, and a normally-on TFT. There were limitations on the manufacturing process and usage environment such as low performance and poor chemical resistance, making wet etching difficult. Furthermore, in order to improve the performance, it is necessary to form a film at a high pressure, and the film formation rate is slow, a high-temperature treatment of 700 ° C. or higher is necessary. To improve the performance, the top gate configuration needs to have a film thickness of 50 nm or more. There were many practical restrictions.

  In order to solve such a problem, a field effect transistor (a thin film transistor, an amorphous oxide semiconductor made of indium oxide, zinc oxide, or an amorphous oxide semiconductor made of indium oxide, zinc oxide, gallium oxide is used. TFT) has been studied. However, if gallium (Ga) is not added, environmental stability such as moisture resistance is insufficient. On the other hand, if Ga is added, TFT characteristics such as mobility and S value may be deteriorated. Furthermore, since Ga is a rare metal, the cost is high and there is a problem in stable supply.

  Then, the possibility of the field effect transistor using the amorphous oxide semiconductor which consists of an indium oxide, a zinc oxide, and a tin oxide as what does not use Ga is also suggested (patent document 1).

A field effect transistor using tin oxide has been studied for a long time, but has not been put into practical use because of high off-current and low mobility. This was thought to be due to the fact that tin oxide tends to produce lower oxide (SnO) as an insulator. From this, it was thought that tin oxide was not suitable as a semiconductor material.
In fact, in a field effect transistor using an amorphous oxide semiconductor composed mainly of indium oxide, zinc oxide, and tin oxide containing tin as a main component, off current and hysteresis are large, and a threshold voltage (Vth) is large and negative. It was. Furthermore, although the mobility can be improved by the heat treatment, the threshold voltage is greatly shifted in the negative direction according to the heat treatment temperature, so that there is a problem that hinders practical use, such as a large variation of transistors and low reliability (Non-patent Document 2). .

  On the other hand, in the study of amorphous oxide semiconductors composed of indium oxide, zinc oxide, and tin oxide that do not contain tin as a main component using co-sputtering, the mobility decreases when zinc is contained at 25 atomic% or more, and the threshold voltage is reduced. On the other hand, when zinc is less than 25 atomic%, the S value increases and the threshold voltage becomes negative, and it was considered difficult to produce a field effect transistor with excellent transistor characteristics (Non-patent Document 3). .

  Under such circumstances, it has been considered difficult to produce a field effect transistor suitable for practical use such as a display panel in an amorphous oxide semiconductor made of indium oxide, zinc oxide, and tin oxide.

International Publication No. 2005/088726 Pamphlet

Transparent conductive film technology (2nd revised edition), published by Ohmsha, p. 160 M.M. S. Grover et al. , J .; Phys. D. 40, 1335 (2007) Kachirayil J. et al. Saji et al. , JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 155 (6), H390-395 (2008)

  An object of the present invention is to provide a field effect transistor having good transistor characteristics and suitable for a display panel.

According to the present invention, the following amorphous oxide thin film and the like are provided.
1. An amorphous oxide thin film containing at least tin (Sn) and having a SnO ratio of less than 30 mol% when the total of SnO and SnO ₂ is 100 mol%.
2. 2. The amorphous oxide thin film according to 1, further comprising a complex oxide containing at least one element selected from indium (In), zinc (Zn), and gallium (Ga).
3. 3. The amorphous oxide thin film according to 2, comprising a composite oxide containing at least tin (Sn) and indium (In).
4). 3. The amorphous oxide thin film according to 2, comprising a composite oxide containing at least tin (Sn), indium (In), and zinc (Zn).
5. The atomic composition ratio represented by Sn / (In + Sn + Zn) is 0.1 atomic% or more and 30 atomic% or less,
A composite oxide having an atomic composition ratio represented by In / (In + Sn + Zn) of 5 atomic% to 75 atomic% and an atomic composition ratio represented by Zn / (In + Sn + Zn) of 20 atomic% to 75 atomic% 5. The amorphous oxide thin film according to 4.
6. A thin film transistor comprising the amorphous oxide thin film according to claim 1 as a semiconductor layer.
7). 7. The method for producing a thin film transistor according to 6, comprising a step of promoting oxidation in the amorphous oxide thin film.
8). Sputtering a target made of a metal oxide in a gas atmosphere containing a rare gas atom and water molecules, wherein the water molecule content is 0.1 to 10% in a partial pressure ratio with respect to the total pressure of the atmospheric gas, 8. The method for producing a thin film transistor according to 7, including a step of forming a thin film on the substrate.
9. Furthermore, the manufacturing method of the thin-film transistor of 8 which sputter | spatters in the atmosphere of the gas which contains 0.1-10% of oxygen molecules by the partial pressure ratio with respect to the total pressure of the said atmospheric gas.

  According to the present invention, a field effect transistor having good transistor characteristics and suitable for a display panel can be provided.

It is a figure which shows the measuring method of the ratio of SnO in an Example and a comparative example. XANES spectra of K absorption edge of Sn in the composite oxide (ITZO) thin film fabricated in Example 1 and is a diagram showing a spectrum for SnO and SnO ₂ for comparison. It is a figure which shows the measurement result of the TFT characteristic of the thin-film transistor produced in the evaluation example 1.

The amorphous oxide thin film of the present invention includes at least tin (Sn), and the ratio of SnO is less than 30 mol% when the total amount of SnO and SnO ₂ is 100 mol%.
The ratio (mol%) of SnO when the total of SnO and SnO ₂ is 100 mol% is referred to as “SnO ratio”.
When the ratio of SnO (lower tin oxide) is less than 30 mol%, a thin film transistor with high mobility can be obtained. The proportion of SnO is preferably less than 25 mol%, particularly preferably less than 20 mol%.

The SnO ratio is obtained by analyzing a profile in the vicinity of the K absorption edge of Sn element obtained by XANES (X-ray Absorption Near Edge Structure, X-ray absorption edge fine structure). Specifically, it can be measured by the method described in the examples.
XANES is an analysis method for analyzing a structure around an element from a specific XAFS spectrum generated by irradiating a substance with X-rays.

  The thin film of the present invention contains tin (Sn), and preferably comprises a complex oxide containing at least one element selected from indium (In), zinc (Zn), and gallium (Ga).

The thin film of the present invention is more preferably composed of a complex oxide containing at least tin (Sn) and indium (In). Examples of the complex oxide include those composed of the following elements.
-Tin (Sn) and Indium (In)
-Tin (Sn), indium (In) and one or more third elements As the third element, Zn, B, Sc, Y, Al, Ga, lanthanoids (La, Ce, Pr, Nd, Sm, Eu Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), Zr, Hf, Ge, Si, Ti, Mn, W, Mo, V, Cu, Ni, Co, Fe, Cr, Nb, etc. Can be mentioned.
The third element may be only one type or two or more types.
As the third element, Zn, Ga, Zr, Hf, Ge, Si, Ti, and Al are particularly preferable because of high mobility when they are thin film transistors.

Among the above, particularly preferred combinations are shown below.
・ Tin (Sn), Indium (In), Zinc (Zn)
・ Tin (Sn), Indium (In), Gallium (Ga)
-Tin (Sn), Indium (In), Zinc (Zn), Gallium (Ga)

When the thin film is made of a complex oxide containing tin (Sn), indium (In), and zinc (Zn), it is preferable that the following atomic composition ratio is satisfied.
Sn / (In + Sn + Zn): 0.1 atomic% or more and 30 atomic% or less,
In / (In + Sn + Zn): 5 atomic% or more and 75 atomic% or less Zn / (In + Sn + Zn): 25 atomic% or more and 70 atomic% or less

When the thin film is made of a composite oxide containing tin (Sn), indium (In), and gallium (Ga), it is preferable that the following atomic composition ratio is satisfied.
Sn / (In + Sn + Ga): 0.1 atomic% to 30 atomic% In / (In + Sn + Ga): 5 atomic% to 75 atomic%,
Ga / (In + Sn + Ga): 5 atomic% or more and 50 atomic% or less

When the thin film is made of a complex oxide containing tin (Sn), indium (In), and a third element X (Zr, Hf, Ge, Si, Ti, Al, etc.) other than Zn and Ga (the third element is 1) When a seed is included), it is preferable to satisfy the following atomic composition ratio.
Sn / (In + Sn + X): 0.1 atomic% to 30 atomic% In / (In + Sn + X): 5 atomic% to 75 atomic% X / (In + Sn + X): 20 atomic% to 70 atomic%

When the thin film is made of a composite oxide containing tin (Sn), indium (In), zinc (Zn) (third element X) and third element Y (when two third elements are included), the following atoms It is preferable to satisfy the composition ratio. The third element Y is preferably Ga.
Sn / (In + Sn + Zn + Y): 0.1 atomic% to 30 atomic% In / (In + Sn + Zn + Y): 5 atomic% to 70 atomic% Zn / (In + Sn + Zn + Y): 10 atomic% to 70 atomic% Y / (In + Sn + Zn + Y): 10 atomic% to 60 atomic%

An amorphous thin film means that a halo pattern is observed by X-ray crystal structure analysis and the crystal structure cannot be specified.
Since the thin film is amorphous, adhesion to an insulating film and a protective layer is improved when used in a transistor, and uniform transistor characteristics can be easily obtained even in a large area.

  The thin film of the present invention can be produced, for example, by the following method for forming a semiconductor layer of a thin film transistor.

The thin film transistor of the present invention has the above amorphous oxide thin film as a semiconductor layer (active layer).
Hereinafter, a structure of the thin film transistor and a method for manufacturing the thin film transistor will be described.

(substrate)
There is no restriction | limiting in particular in a board | substrate, A well-known thing can be used in this technical field. For example, glass substrates such as alkali silicate glass, non-alkali glass and quartz glass, silicon substrates, resin substrates such as acrylic, polycarbonate and polyethylene naphthalate (PEN), polymer film bases such as polyethylene terephthalate (PET) and polyamide Materials can be used.
As for the thickness of a board | substrate or a base material, 0.1-10 mm is common, and 0.3-5 mm is preferable. In the case of a glass substrate, those chemically or thermally reinforced are preferred. When transparency and smoothness are required, a glass substrate and a resin substrate are preferable, and a glass substrate is particularly preferable. When weight reduction is required, a resin substrate or a polymer material is preferable.

(Semiconductor layer)
The semiconductor layer is made of the amorphous oxide thin film of the present invention.
The electron carrier concentration of the semiconductor layer is preferably 10 ¹³ to 10 ¹⁹ / cm ³ , and particularly preferably 10 ¹⁶ to 10 ¹⁸ / cm ³ . When the electron carrier concentration is in the above range, it is easy to become a non-degenerate semiconductor, and when used as a transistor, the balance between mobility and on / off ratio is good, which is preferable.
The band gap is preferably 2.0 to 6.0 eV, and more preferably 2.8 to 5.0 eV. If the band gap is smaller than 2.0 eV, visible light is absorbed and the field effect transistor may malfunction. On the other hand, if it is larger than 6.0 eV, it is difficult to supply carriers and the field effect transistor may not function.

The surface roughness (RMS) of the semiconductor layer is preferably 1 nm or less, more preferably 0.6 nm or less, and particularly preferably 0.3 nm or less. If it is larger than 1 nm, the mobility may decrease.
The film thickness of the semiconductor layer is usually 0.5 to 500 nm, preferably 1 to 150 nm, more preferably 3 to 80 nm, and particularly preferably 10 to 60 nm. If it is thinner than 0.5 nm, it is difficult to form a uniform film industrially. On the other hand, if it is thicker than 500 nm, the film formation time becomes long and cannot be adopted industrially. Moreover, when it exists in the range of 3-80 nm, TFT characteristics, such as a mobility and an on / off ratio, are especially favorable.

  As a method for forming the semiconductor layer, a solution such as a sol-gel method or a CVD method can be used. However, in order to uniformly form a film over a large area, it is preferable to form the semiconductor layer by sputtering using a semiconductor target described later.

  By forming the thin film with a specific composition ratio of the constituent elements of the thin film and forming the semiconductor layer of the thin film transistor described below, the SnO ratio can be less than 30 mol%.

The method for manufacturing a transistor of the present invention includes a treatment that promotes oxidation in the film (increases oxygen uptake) in order to suppress the formation of SnO in the formation of the semiconductor layer.
As this treatment, there is a method in which an atmosphere such as oxygen or water that easily promotes oxidation is included in the atmosphere during film formation, ozone treatment (ozone ashing), high oxygen partial pressure, or an atmosphere containing water vapor after film formation. Heat treatment or the like can be used. In the case of simplifying the process, it is preferable to promote oxidation during film formation.

As a treatment for promoting oxidation at the time of film formation, it is preferable to include water or hydrogen in the atmosphere at the time of film formation, more preferably to include water or hydrogen and oxygen, and particularly to include water and oxygen. preferable.
Through the above process, an oxide (semiconductor layer) in which the oxide (semiconductor layer) is further oxidized and the generation of SnO is reduced can be manufactured. This is apparent from the measurement result of the XANES spectrum at the K absorption edge of Sn in the composite oxide (ITZO) thin film produced in Example 1 shown in FIG. The ITZO film formed by the method of the present invention does not coincide with the peak of SnO during film formation or after annealing, indicating that there is little SnO in the thin film.

Water partial pressure during film formation atmosphere is preferably ^{1 × 10 -3 Pa~1 × 10 -1} Pa, more preferably ^{2 × 10 -3 Pa~1 × 10 -1} Pa, 5 × 10 -3 Pa~2 × 10 ⁻² Pa is particularly preferable. When the water pressure is 1 × 10 ⁻³ Pa or more, the production of a lower oxide of tin can be suppressed. When the pressure is 1 × 10 ⁻¹ Pa or less, it can be expected that the film forming speed is increased.
The water content in the atmosphere during film formation is preferably 0.1 to 10%, preferably 1 to 6%, in terms of the partial pressure ratio with respect to the total pressure of the atmospheric gas.

  The oxygen content of the atmosphere at the time of film formation is preferably 0.1 to 10%, preferably 1 to 8% in terms of the partial pressure ratio with respect to the total pressure of the atmospheric gas.

(Semiconductor layer protective layer)
A protective layer is preferably provided on the semiconductor layer. When the protective layer is present, oxygen in the surface layer of the semiconductor is desorbed in a vacuum or under a low pressure, so that an off current increases and a threshold voltage can be prevented from becoming negative. Further, it is possible to prevent the occurrence of variations in transistor characteristics such as threshold voltage without being influenced by ambient conditions such as humidity even in the atmosphere.

The material for forming the protective layer of the semiconductor layer is not particularly limited. What is generally used can be arbitrarily selected as long as the effects of the present invention are not lost.
For _{example, SiO 2, SiN x, Al} 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3, Y ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO ₃ , AlN, or the like can be used. Among _these, it is preferable to use _{SiO 2, SiN x, Al 2} O 3, Y 2 O 3, Hf 2 O 3, CaHfO 3, more preferably _{SiO 2, SiN x, Y 2} O 3, Hf 2 O ₃ , CaHfO ₃ , and particularly preferably oxides such as SiO ₂ , Y ₂ O ₃ , Hf ₂ O ₃ , and CaHfO ₃ . The number of oxygen in these oxides does not necessarily match the stoichiometric ratio (for example, it may be SiO ₂ or SiO _x ). SiN _x may contain a hydrogen element.
Such a protective film may have a structure in which two or more different insulating films are stacked.

  The protective layer may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to produce industrially. Note that the protective layer is particularly preferably amorphous. When the film is an amorphous film, the smoothness of the interface is good, and an improvement in mobility, suppression of threshold voltage, and suppression of S value can be expected. In addition, gate leakage current can be suppressed.

The protective layer of the semiconductor layer is preferably an amorphous oxide or an amorphous nitride, and particularly preferably an amorphous oxide. Further, if the protective layer is not an oxide, oxygen in the semiconductor moves to the protective layer side, and there is a possibility that the off current becomes high or the threshold voltage becomes negative and normally off.
Further, an organic insulating film such as poly (4-vinylphenol) (PVP) or parylene may be used for the protective layer of the semiconductor layer. Further, the protective layer of the semiconductor layer may have a laminated structure of two or more layers of an inorganic insulating film and an organic insulating film. In particular, it is preferable that the first protective layer that is in great contact with the semiconductor layer is made of an amorphous oxide such as SiO _x and the second protective layer is made of an amorphous nitride such as SiN _x . With such a configuration, it is easy to give good transistor characteristics and moisture resistance.

  For the formation of the protective film, PE (plasma) CVD, TEOS (tetraethoxysilane) CVD, Cat (catalyst) -CVD, sputtering, spin coating, printing method and the like can be used, but industrially PECVD or sputtering is preferable. PECVD is particularly preferred.

(Gate insulation film)
There is no particular limitation on the material for forming the gate insulating film. What is generally used can be arbitrarily selected as long as the effects of the present invention are not lost.
For _{example, SiO 2, SiNx, Al 2} O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3, Y ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO ₃ , AlN, or the like can be used. Among _these, it is preferable to use _{SiO 2, SiN x, Al 2} O 3, Y 2 O 3, Hf 2 O 3, CaHfO 3, more preferably _{SiO 2, SiN x, Y 2} O 3, Hf 2 O ₃ and CaHfO ₃ . The number of oxygen in these oxides does not necessarily match the stoichiometric ratio (for example, it may be SiO ₂ or SiO _x ). SiN _x may contain a hydrogen element.

Such a gate insulating film may have a structure in which two or more different insulating films are stacked. The gate insulating film may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to manufacture industrially.
The gate insulating film may be an organic insulating film such as poly (4-vinylphenol) (PVP) or parylene. Further, the gate insulating film may have a stacked structure of two or more layers of an inorganic insulating film and an organic insulating film.

  For the formation of the gate insulating film, PECVD, TEOSCVD, Cat-CVD, sputtering, spin coating, printing, or the like can be used, but industrially, PECVD or sputtering is preferable, and PECVD is particularly preferable.

(electrode)
There are no particular limitations on the material for forming each of the gate electrode, the source electrode, and the drain electrode, and any material generally used can be selected as long as the effects of the present invention are not lost.
For example, transparent electrodes such as indium tin oxide (ITO), indium zinc oxide, ZnO, SnO ₂ , metal electrodes such as Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, Cu, or these An alloy metal electrode can be used. Moreover, it is preferable to laminate two or more layers to reduce the contact resistance or improve the interface strength. Further, in order to reduce the contact resistance of the source electrode and the drain electrode, the resistance of the interface of the semiconductor layer with the electrode may be adjusted by plasma treatment, ozone treatment or the like.

(Light shielding layer)
The field effect transistor of the present invention preferably has a structure that shields the semiconductor layer. Without a structure that shields the semiconductor layer (for example, a light shielding layer), when light enters the semiconductor layer, carrier electrons may be excited and off current may increase. The light shielding layer is preferably a thin film having absorption at 300 to 800 nm. The light shielding layer may be either the upper part or the lower part of the semiconductor layer, but is preferably on both the upper part and the lower part. Further, the light shielding layer may also be used as a gate insulating film, a black matrix, or the like. When the light shielding layer is on only one side, it is necessary to devise a structure so that light is not irradiated to the semiconductor layer from the side where the light shielding layer is not present.

Each component (layer) of the field effect transistor other than the semiconductor layer can be formed by a technique known in this technical field.
Specifically, each layer is formed by a chemical film formation method such as a spray method, a dip method, or a CVD method, or a physical method such as a sputtering method, a vacuum deposition method, an ion plating method, or a pulse laser deposition method. A film formation method can be used.
Since the carrier density is easily controlled and the film quality can be easily improved, a physical film formation method is preferably used, and a sputtering method is more preferably used because of high productivity.

In sputtering, a method using a sintered complex oxide target, a method using co-sputtering using a plurality of sintered targets, a method using reactive sputtering using an alloy target, and the like can be used. However, the method using a composite oxide sintered target has improved uniformity and reproducibility compared to the method using co-sputtering using a plurality of sintered targets and the method using reactive sputtering using an alloy target. The energy width (E ₀ ) of the localized level can be reduced, and transistor characteristics such as improvement in mobility, reduction in S value, and reduction in threshold voltage can be improved.
Preferably, a composite oxide sintered target is used. Although well-known things, such as RF, DC, or AC sputtering, can be utilized, DC or AC sputtering is preferable from uniformity and mass productivity (equipment cost, film-forming speed).

The substrate temperature during film formation is preferably from room temperature to 250 ° C., more preferably from room temperature to 200 ° C. When the temperature is 250 ° C. or lower, reduction of off-current can be expected when a TFT is manufactured.
The formed film can be patterned by various etching methods.

  The semiconductor layer is preferably formed by DC or AC sputtering. By using DC or AC sputtering, damage during film formation can be reduced as compared with RF sputtering. For this reason, in the field effect transistor, effects such as a reduction in threshold voltage shift, an improvement in mobility, a reduction in threshold voltage, and a reduction in S value can be expected.

Further, heat treatment is preferably performed at 150 to 350 ° C. after the semiconductor layer is formed. In particular, heat treatment is preferably performed at 150 to 350 ° C. after forming the semiconductor layer and the protective layer of the semiconductor layer.
If the temperature is lower than 150 ° C., the thermal stability and heat resistance of the obtained transistor may decrease, mobility may decrease, S value may increase, and threshold voltage may increase. On the other hand, when the temperature is higher than 350 ° C., there is a possibility that a substrate having no heat resistance may not be used, and there is a possibility that equipment costs for heat treatment are required.

  The heat treatment temperature is more preferably 160 to 300 ° C, further preferably 170 to 260 ° C, and particularly preferably 180 to 240 ° C. In particular, if the heat treatment temperature is 180 ° C. or higher and 240 ° C. or lower, it is avoided that the thermal stability and heat resistance are reduced, the mobility is lowered, the S value is increased, or the threshold voltage is increased. In addition, a resin substrate having low heat resistance such as PEN can be used as the transistor substrate, which is preferable.

The heat treatment time is usually preferably 1 second to 24 hours, but is preferably adjusted by the treatment temperature. For example, at 70 to 180 ° C., 10 minutes to 24 hours are more preferable, 20 minutes to 6 hours are more preferable, and 30 minutes to 3 hours are particularly preferable.
In 180-260 degreeC, 6 minutes-4 hours are more preferable, and 15 minutes-2 hours are further more preferable. In 260-300 degreeC, 30 second-4 hours are more preferable, and 1 minute-2 hours are especially preferable.
At 300 to 350 ° C., 1 second to 1 hour is more preferable, and 2 seconds to 30 minutes is particularly preferable.

A sputtering target for forming a semiconductor layer generally uses an oxide powder (for example, a mixture of indium oxide powder, zinc oxide powder, and tin oxide powder) as a starting material. An oxide or the like may be used as a raw material.
The purity of each raw material powder is usually 99.9% (3N) or higher, preferably 99.99% (4N) or higher, more preferably 99.995% or higher, particularly preferably 99.999% (5N) or higher. . If the purity of each raw material powder is less than 99.9% (3N), the semiconductor characteristics may be deteriorated by impurities.

For the raw material powder, indium oxide powder having a specific surface area of 3~16m ² / g, tin oxide powder, wherein zinc powder or mixed oxide powder, mixed powder specific surface area of the entire powder is 3~16m ² / g It is preferable to use the body as a raw material.
In addition, it is preferable to use the powder whose specific surface area of each oxide powder is substantially the same. Thereby, it can pulverize and mix more efficiently. Specifically, the ratio of the specific surface area is preferably 1/4 to 4 times or less, particularly preferably 1/2 to 2 times or less. If the specific surface area is too different, efficient pulverization and mixing cannot be performed, and oxide particles may remain in the sintered body.
However, the specific surface area of zinc oxide is preferably smaller than the specific surface areas of indium oxide and tin oxide. As a result, uneven color of the target can be suppressed.

The mixed powder is mixed and ground using, for example, a wet medium stirring mill. At this time, the specific surface area after pulverization is increased to 1.0 to 3.0 m ² / g from the specific surface area of the raw material mixed powder, or the average median diameter after pulverization is adjusted to be 0.6 to 1 μm. It is preferable to do. By using the raw material powder prepared in this manner, a high-density oxide sintered body can be obtained without requiring a calcination step at all. Moreover, a reduction process is also unnecessary.

In addition, if the increase in the specific surface area of the raw material mixed powder is less than 1.0 m ² / g or the average median diameter of the raw material mixed powder after pulverization exceeds 1 μm, the sintered density may not be sufficiently increased. On the other hand, if the increase in the specific surface area of the raw material mixed powder exceeds 3.0 m ² / g, or if the average median diameter after pulverization is less than 0.6 μm, contamination from the pulverizer during pulverization (impurity contamination amount) ) May increase.
Here, the specific surface area of each powder is a value measured by the BET method. The median diameter of the particle size distribution of each powder is a value measured with a particle size distribution meter. These values can be adjusted by pulverizing the powder by a dry pulverization method, a wet pulverization method or the like.

  The raw material powder is preferably mixed in the same elements and mixing ratio as the thin film of the present invention.

The method for mixing the raw material powder and the method for molding are not particularly limited, and various conventionally known wet methods or dry methods can be used.
Examples of the dry method include a cold press method and a hot press method. In the cold press method, the mixed powder is filled in a mold to produce a molded body and sintered. In the hot press method, the mixed powder is directly sintered in a mold at 700 to 1000 ° C. for 1 to 48 hours, preferably 800 to 950 ° C. for 3 to 24 hours.

  As a dry-type cold press method, the raw material after the pulverization step is dried with a spray dryer or the like and then molded. For the molding, known methods such as pressure molding, cold isostatic pressing, mold molding, and cast molding injection molding can be employed. In order to obtain a sintered body (target) having a high sintered density, it is preferable to mold by a method involving pressurization such as cold isostatic pressure (CIP). In the molding process, molding aids such as polyvinyl alcohol, methylcellulose, polywax, and oleic acid may be used.

  Next, the obtained molded product is sintered to obtain a sintered body. Sintering is preferably performed in an oxygen atmosphere by circulating oxygen or under pressure. Thereby, transpiration of zinc can be suppressed, and a sintered body free from voids (voids) can be obtained. Since the sintered body manufactured in this manner has a high density and generates less nodules and particles during use, an oxide semiconductor film having excellent film characteristics can be manufactured.

  It is preferable that the heating rate at 800 ° C. or higher is 30 ° C./h or lower. If the rate of temperature rise exceeds 30 ° C./h, warping and cracking may occur.

  As the wet method, for example, it is preferable to use a filtration molding method (see JP-A-11-286002). This filtration molding method is a filtration molding die made of a water-insoluble material for obtaining a molded body by draining water from a ceramic raw material slurry under reduced pressure, and a lower molding die having one or more drain holes And a water-permeable filter placed on the molding lower mold, and a molding mold clamped from the upper surface side through a sealing material for sealing the filter, the molding lower mold, Forming mold, sealing material, and filter are assembled so that they can be disassembled respectively. Using a filtering mold that drains the water in the slurry under reduced pressure only from the filter surface side, mixed powder, ion-exchanged water and organic A slurry made of an additive was prepared, and this slurry was poured into a filter-type mold, and the molded body was produced by draining the water in the slurry under reduced pressure only from the filter surface side. After 燥脱 butter, baking.

  In order to make the bulk resistance of the sintered body obtained by a dry method or a wet method uniform over the entire target, a reduction treatment is preferable. A reduction process is a process provided as needed. Examples of the reduction method that can be applied include a method using a reducing gas, vacuum firing, or reduction using an inert gas.

  The oxide sintered body becomes a target by performing processing such as polishing. Specifically, the sintered body is ground by, for example, a surface grinder so that the surface roughness Ra is 5 μm or less. The surface roughness is more preferably Ra ≦ 0.3 μm, and particularly preferably Ra ≦ 0.1 μm.

Further, the sputter surface of the target may be mirror-finished so that the average surface roughness Ra is 1000 angstroms or less. For this mirror finishing (polishing), a known polishing technique such as mechanical polishing, chemical polishing, mechanochemical polishing (a combination of mechanical polishing and chemical polishing) can be used.
For example, polishing to # 2000 or more with a fixed abrasive polisher (polishing liquid: water) or lapping with loose abrasive lapping (abrasive: SiC paste, etc.), and then lapping by changing the abrasive to diamond paste Can be obtained by: Such a polishing method is not particularly limited.

  In addition, air blow, running water washing | cleaning, etc. can be used for the cleaning process of a target. When removing foreign matter by air blow, it is possible to remove the foreign matter more effectively by suctioning with a dust collector from the opposite side of the nozzle. In addition to air blow and running water cleaning, ultrasonic cleaning and the like can also be performed. In ultrasonic cleaning, a method of performing multiple oscillations at a frequency of 25 to 300 KHz is effective. For example, it is preferable to perform ultrasonic cleaning by causing multiple oscillations of 12 types of frequencies at intervals of 25 KHz between frequencies of 25 to 300 KHz.

  After the obtained target is processed, it is bonded to a backing plate, whereby a sputtering target that can be used by being attached to a film forming apparatus is obtained. The backing plate is preferably made of copper. It is preferable to use indium solder for bonding.

The processing step is to further cut the sintered body obtained by sintering as described above into a shape suitable for mounting on a sputtering apparatus, and to attach a mounting jig such as a backing plate, It is a process provided as needed. The thickness of the target is usually 2 to 20 mm, preferably 3 to 12 mm, particularly preferably 4 to 6 mm. Further, a plurality of targets may be attached to one backing plate to make a substantially single target.
The surface is preferably finished with a diamond grindstone of No. 200 to 10,000, and particularly preferably finished with a diamond grindstone of No. 400 to 5,000. If a diamond grindstone smaller than No. 200 or larger than 10,000 is used, the target may be easily broken.

In the field effect transistor, when a voltage Vd of about 5 to 20 V is applied between the source and drain electrodes, the gate voltage Vg is switched between 0 V and 5 to 20 V to thereby change the current Id between the source and drain electrodes. It can be controlled (turned on and off).
As evaluation items of transistor characteristics, for example, field effect mobility μ, threshold voltage (Vth), on / off ratio, S value, and the like can be given.

The field effect mobility can be obtained from the characteristics of the linear region and the saturation region. For example, a method of preparing a graph of √Id−Vg from the result of the transfer characteristics and deriving the field effect mobility from this slope can be mentioned. In this specification, unless otherwise specified, this method is used for evaluation.
There are several methods for obtaining the threshold voltage. For example, the threshold voltage Vth can be derived from the x intercept of the graph of √Id−Vg.

  The on / off ratio can be obtained from the ratio of the largest Id to the smallest Id value in the transfer characteristics.

The S value can be derived from the reciprocal of this slope by creating a Log (Id) -Vd graph from the result of the transfer characteristics.
The unit of the S value is V / decade and is preferably a small value. The S value is preferably 1.0 V / dec or less, more preferably 0.5 V / dec or less, further preferably 0.3 V / dec or less, and particularly preferably 0.1 V / dec or less. If it is 0.8 V / dec or less, the driving voltage becomes small and the power consumption may be reduced. In particular, when used in an organic EL display, it is preferable to set the S value to 0.3 V / dec or less because of direct current drive because power consumption can be greatly reduced. The S value (Swing Factor) is a value indicating the steepness of the drain current that rises sharply from the off state to the on state when the gate voltage is increased from the off state. As defined by the following equation, an increment of the gate voltage when the drain current increases by one digit (10 times) is defined as an S value.
S value = dVg / dlog (Ids)

  The smaller the S value, the sharper the rise ("All about Thin Film Transistor Technology", Ikuhiro Ukai, 2007, Industrial Research Committee). When the S value is large, it is necessary to apply a high gate voltage when switching from on to off, and power consumption may increase.

A field effect transistor of the present invention, mobility is preferably not less than ^{3 cm} 2 / Vs, more preferably at least ^{8 cm} 2 / Vs, more preferably at least 10 cm ² / Vs, particularly preferably at least 16cm ² / Vs. If it is smaller than 3 cm ² / Vs, the switching speed becomes slow, and there is a possibility that it cannot be used for a large-screen high-definition display.

The on / off ratio is preferably 10 ⁷ or more, more preferably 10 ⁸ or more, and particularly preferably 10 ⁹ or more.
The off current is preferably 2 pA or less, more preferably 1 pA or less, and particularly preferably 0.1 pA or less. When the off-current is smaller than 2 pA, it is expected that when used as a display TFT, the contrast becomes good and the uniformity of the screen is improved.

The gate leakage current is preferably 1 pA or less. When it is smaller than 1 pA, a decrease in contrast can be suppressed when used as a TFT of a display.
The threshold voltage is usually -1 to 5V, preferably -0.5 to 3V, more preferably 0 to 2V, and particularly preferably 0 to 1V. If it is larger than -1 V, the voltage applied at the time of OFF is reduced, and the power consumption may be reduced. If it is less than 5V, the drive voltage becomes small and the power consumption may be reduced.

Further, the shift amount of the threshold voltage before and after applying a 10 μA DC voltage at 50 ° C. for 100 hours is preferably 1.0 V or less, and more preferably 0.5 V or less. If the voltage is less than 1 V, the change in image quality over time can be reduced when used as a transistor of an organic EL display.
Further, it is preferable that the hysteresis is small when the gate voltage is raised or lowered on the transfer curve. If the history is small, there is a possibility that the drive voltage can be reduced.

The ratio W / L of the channel width W to the channel length L is usually 0.1 to 100, preferably 0.5 to 20, and particularly preferably 1 to 8. If W / L exceeds 100, the leakage current may increase or the on / off ratio may decrease.
If it is less than 0.1, the field effect mobility may be lowered, or pinch-off may be unclear.
The channel length L is usually 0.1 to 1000 μm, preferably 1 to 100 μm, and more preferably 2 to 10 μm. If the thickness is 0.1 μm or less, it is difficult to produce industrially and the leakage current may be increased. If the thickness is 1000 μm or more, the device becomes too large, which is not preferable.

Example 1
An etch stopper (ES) type field effect transistor having a bottom gate structure was manufactured as follows.
(1) Production of sputtering target As raw materials, powders of indium oxide, zinc oxide and tin oxide have an atomic ratio [In / (In + Sn + Zn)] of 0.365 and an atomic ratio [Sn / (In + Sn + Zn)] of 0.15. Mixing was performed so that the atomic ratio [Zn / ((In + Sn + Zn)] was 0.485. This was supplied to a wet ball mill and mixed and pulverized to obtain a raw material fine powder.

After granulating the obtained raw material fine powder, it was press-molded, put in a firing furnace, fired at 1400 ° C. for 12 hours, and then ground to obtain a sintered body having a thickness of 5 mm and a diameter of 2 inches. The bulk resistance of the sintered body was 2 mΩ, and the theoretical relative density was 0.98.
The theoretical relative density was obtained by calculating the ratio of the density calculated from the specific gravity of each oxide and the amount ratio thereof to the density measured by the Archimedes method.
Further, when the composition of the sintered body was analyzed, the atomic ratio [In / (In + Sn + Zn)] was 0.365, the atomic ratio [Sn / (In + Sn + Zn)] was 0.15, and the atomic ratio [Zn / ((In + Sn + Zn)] was 0.485.
After the sintered body was cleaned, it was bonded to a backing plate to obtain a sputtering target.

(2) Thin Film Production and Evaluation A 150 nm thick oxide thin film was formed on a glass substrate (Corning 1737) using the target manufactured in (1) and evaluated.
Sputtering conditions were as follows: ultimate pressure: 4 × 10 ⁻⁴ Pa or less, atmospheric gas: Ar 94% and oxygen 5%, water 1%, sputtering pressure (total pressure): 0.65 Pa, a DC power source and an input power of 100 W.
The oxide semiconductor film was heat-treated at 300 ° C. for 1 hour in the air.

[Evaluation of crystallinity]
A halo pattern was observed by X-ray crystal structure analysis, and was confirmed to be amorphous.

[Evaluation of lower oxide of tin]
SnO (a lower oxide of tin) was evaluated by the optical system shown in FIG.
XANES measurement was performed on the BL14B2 line of SPring-8 (High Intensity Photoscience Research Center (JASRI)). First, the XANES spectrum of the Sn K absorption edge was measured with respect to powdered SnO and SnO2 by the transmission method. SnO and SnO2 powder samples were diluted with KBr (potassium bromide) and used as pellets. Thereafter, the XANES spectrum was measured by a fluorescence method for the thin film sample produced by the sputtering method.

After background processing, analysis was performed using analysis software REX2000. After subtracting −200 to 400 eV from the rising position of the XANES spectrum as a baseline, normalization was performed at the peak top of the XANES spectrum, and pattern fitting of the XANES spectrum of the sample was performed using two spectra of SnO and SnO ₂ .
In pattern fitting, pattern fitting operation is performed with standard data of SnO and SnO _{2 on} the region of ± 40 eV from the rising position of the XANES spectrum, and the ratio of SnO (mol%) (SnO / (SnO + SnO ₂ ) × 100) from this result. As a result, it was 16%.

(3) Fabrication of transistor Using the target manufactured in (1) as in (2), except that an island shape was formed with a metal mask with a film thickness of 50 nm on an n-type silicon wafer with a thermal oxide film of 100 nm. Then, a thin film was formed, and heat treatment was performed at 300 ° C. for 1 hour in an air atmosphere to obtain an active layer (semiconductor layer).
Using another metal mask, a gold thin film with a thickness of 300 nm is stacked to serve as source / drain electrodes, and heat treatment is performed at 300 ° C. for 1 hour in an air atmosphere to produce a bottom gate top contact type thin film transistor with W / L = 1000/200 μm. did.

(4) Evaluation of transistor Field effect mobility (μ) of a field effect transistor was measured using a semiconductor parameter analyzer (4200SCS, manufactured by Keithley Instruments Co., Ltd.) at room temperature in a light-shielded environment. The results are shown in Table 1.

Examples 2-14, Comparative Examples 1-2
A thin film and a transistor were prepared and evaluated in the same manner as in Example 1 except that the composition of the target and the atmosphere gas during film formation were changed as shown in Table 1. The results are shown in Tables 1 and 2.

Example 3
A thin film with a thickness of 50 nm was formed on the n-type silicon wafer with a thermal oxide film of 100 nm using the target manufactured in Example 1. Sputtering conditions were as follows: ultimate pressure: 4 × 10 ⁻⁴ Pa or less, atmospheric gas: Ar 93% and moisture pressure 7%, sputtering pressure (total pressure): 0.65 Pa, DC power supply and input power 100 W.

After forming the island of the semiconductor layer using photolithography, it was heat-treated in the atmosphere at 300 ° C. for 1 hour. Ti / Au / Ti source / drain electrodes were formed by a lift-off method using sputtering and photolithography. Heat treatment was performed at 300 ° C. for 1 hour in the air to obtain a thin film transistor with W / L = 20/10 μm.
TFT characteristics are field effect mobility μ = 18 cm ² / Vs, S value SS = 0.4 V / dec. The threshold voltage Vth was −1.8V. The results are shown in FIG.

  The thin film of the present invention can be used for a thin film transistor, and the thin film transistor of the present invention can be widely used as a unit electronic element, a high frequency signal amplifying element, a liquid crystal driving element and the like of a semiconductor memory integrated circuit.

Claims (9)

An amorphous oxide thin film containing at least tin (Sn) and having a SnO ratio of less than 30 mol% when the total of SnO and SnO ₂ is 100 mol%.   The amorphous oxide thin film according to claim 1, further comprising a composite oxide containing at least one element selected from indium (In), zinc (Zn), and gallium (Ga).   The amorphous oxide thin film according to claim 2, comprising a composite oxide containing at least tin (Sn) and indium (In).   The amorphous oxide thin film according to claim 2, comprising a composite oxide containing at least tin (Sn), indium (In), and zinc (Zn). The atomic composition ratio represented by Sn / (In + Sn + Zn) is 0.1 atomic% or more and 30 atomic% or less,
A composite oxide having an atomic composition ratio represented by In / (In + Sn + Zn) of 5 atomic% to 75 atomic% and an atomic composition ratio represented by Zn / (In + Sn + Zn) of 20 atomic% to 75 atomic% The amorphous oxide thin film according to claim 4.   A thin film transistor comprising the amorphous oxide thin film according to claim 1 as a semiconductor layer.   The method for producing a thin film transistor according to claim 6, comprising a step of promoting oxidation in the amorphous oxide thin film.   Sputtering a target made of a metal oxide in a gas atmosphere containing a rare gas atom and water molecules, wherein the water molecule content is 0.1 to 10% in a partial pressure ratio with respect to the total pressure of the atmospheric gas, The method for producing a thin film transistor according to claim 7, comprising a step of forming a thin film on the substrate.   Furthermore, the manufacturing method of the thin-film transistor of Claim 8 sputter | spatters in the atmosphere of the gas which contains oxygen molecules 0.1 to 10% by the partial pressure ratio with respect to the total pressure of the said atmospheric gas.