JP2012113518A - Compiler device, code generation method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to access all areas by using register relative access when there are multiple data areas such as a data area for each core and a shared data area shared between cores in an asymmetric multi-core processor.SOLUTION: A compiler device for a multi-core processor performs following steps if there are multiple data areas such as a data area for each core and a shared data area shared between cores: generating a code which saves a register value for register relative access at the beginning of a function in a common program area to a saving destination (such as a data area for each core); and generating a code which overwrites the register value for register relative access with the first address of the shared data area and a code which rewrites (overwrites) the register value for register relative access with the value saved in the saving destination when the function ends (right before the process to branch to an invoker of the function).

Description

  The present invention relates to a compiler apparatus, and more particularly to a compiler apparatus for an asymmetric multi-core processor.

  In recent years, semiconductor integrated circuits have been installed in many products to perform complex control, and a multi-core processor in which a plurality of processor cores are mounted on one semiconductor integrated circuit is adopted in order to improve processing capability. It has become like this.

  A multi-core processor can be expected to improve processing capability by mounting a plurality of processor cores and to reduce power consumption by combining a plurality of processors.

  In that flow, a compiler device that is a development tool for developing a program for controlling a multi-core processor is also an object that can be controlled between each PE (Processor Element: a unit of arithmetic unit (here, core)). The need to generate code (hereinafter referred to as code) has increased.

  In particular, when performing memory access from a program shared between cores, a program that performs absolute address reference is common, but there is an increasing demand for enabling register relative access with high code efficiency.

<Patent Document 1>
Japanese Unexamined Patent Application Publication No. 2006-058991 discloses an example of a conventional compiler apparatus.

  The conventional compiler device has the function of optimizing the data allocation to the data area, checking the number of data accesses at the time of compilation, and rearranging them in the descending order of the number of accesses and placing them in the data area. Outputs code that performs relative access as much as possible.

[Conventional compiler equipment]
As shown in FIG. 1, a conventional compiler apparatus includes a syntax analysis processing unit 1, an intermediate language level optimization unit 2, a code generation processing unit 3, a source program storage unit 4, an intermediate language storage unit 5, An object program storage unit 6 is provided.

  The syntax analysis processing unit 1 inputs a source program described in a high-level language stored in the source program storage unit 4 and performs syntax analysis. The syntax analysis processing unit 1 stores the syntax analysis result in the intermediate language storage unit 5.

  The intermediate language level optimization unit 2 inputs the syntax analysis result by the syntax analysis processing unit 1 stored in the intermediate language storage unit 5, and performs optimization for increasing the efficiency at the time of code generation. The intermediate language level optimization unit 2 stores the optimization result in the intermediate language storage unit 5.

  The code generation processing unit 3 inputs the optimization result by the intermediate language level optimization unit 2 stored in the intermediate language storage unit 5 and generates a code. The code generation processing unit 3 stores the generated code in the object program storage unit 6.

[Code generation processing section]
As shown in FIG. 2, the code generation processing unit 3 includes a node conversion processing unit 7, a register allocation processing unit 8, an address allocation processing unit 9, and a code output processing unit 10.

  The node conversion processing unit 7 inputs the optimization result by the intermediate language level optimization unit 2 stored in the intermediate language storage unit 5 and performs node conversion processing. The node conversion processing unit 7 stores the node conversion result in the node storage unit 11.

  The register allocation processing unit 8 performs data register allocation processing. The register allocation processing unit 8 stores the register allocation result in the node storage unit 11.

  The address allocation processing unit 9 performs an address allocation process for data that has not been allocated by the register. The address allocation processing unit 9 stores the address allocation result in the node storage unit 11.

  The code output processing unit 10 performs code output processing.

[Address assignment processing section]
As shown in FIG. 3, the address allocation processing unit 9 includes a data management information table chain mechanism 13, a data access count registration processing unit 14, a data management information table chain rearrangement processing unit 15, and a data address allocation processing unit. 16.

  The data management information table chain mechanism 13 has a data management information table 12 (12-i, i = 1 to n: n is the number of tables) for each data.

  Each of the data management information tables 12 (12-i, i = 1 to n) holds a pointer to the next data management information table in a rewritable manner, and has a chain sequence by the pointer. The data management information table 12 (12-i, i = 1 to n) holds a pointer indicating the next data management information table in a rewritable manner. Data management information and the number of data accesses are registered in the data management information table 12 (12-i, i = 1 to n).

  The data access count registration processing unit 14 registers the data access count for each data in the data management information table 12 (12-i, i = 1 to n).

  The data management information table chain rearrangement processing unit 15 performs the data management information table after the data access frequency registration processing unit 14 finishes registering the data access frequency to the data management information table 12 (12-i, i = 1 to n). The sequence of 12 (12-i, i = 1 to n) is rearranged in descending order of the number of data accesses.

  The data address allocation processing unit 16 performs data address allocation processing after the data management information table 12 (12-i, i = 1 to n) is rearranged by the data management information table chain rearrangement processing unit 15. .

[Characteristics of conventional compiler equipment]
As described above, in the conventional compiler apparatus, the data management information table 12 (12-i, i = 1 to n) for each data is prepared, and the data management information table 12 (12-i) is registered by the data access count registration unit 14. , I = 1 to n), the number of data accesses for each data is registered, and then the data management information table chain rearrangement processing unit 15 sets the data management information table so that the number of registered data accesses is in descending order. The chain is reordered.

  Then, the data address assignment processing unit 16 assigns the relative distance from the base address in the order of the data management information table for the data having the higher access count so that the data with the higher address count is arranged closer to the base address. Therefore, the number of appearances of prior address calculation and transfer to the register of the relative distance is reduced.

<Patent Document 2>
Further, as a related technique, Patent Document 2 (Japanese Patent Laid-Open No. 2000-029717) discloses an object generation method, a medium storing a processing procedure thereof, and an object generation apparatus. In this related technology, when a high-level language is translated into a machine instruction, the address of the variable is expressed by the entire address, and the value of the base pointer as the base address is held in the register. Compare the efficiency with the relative value expressed as a relative value, and generate an object that adopts a more efficient expression based on the comparison result.

JP 2006-058991 A JP 2000-029717 A

  Conventional compiler devices use register-relative access to all areas when there are multiple data areas such as a data area for each core and a shared data area shared between cores as in an asymmetric multi-core processor. And cannot be accessed.

  The reason for this is that in an asymmetric multi-core processor, the data area for each core and the shared data area are usually arranged in separate areas that are not continuous, so all these areas are within the range accessible by register-relative access. This is because the register relative access to both the data area for each core and the shared data area is impossible.

  The compiler apparatus according to the present invention is a compiler apparatus for an asymmetric multi-core processor, and is a means for performing variable access analysis based on a syntax analysis result of a source program and obtaining analysis information of a variable reference source and a reference count Based on the analysis information, after arranging the variables, a means for creating intermediate code in an intermediate language and whether or not the object code is generated from the intermediate code is a common program. In the case of a common program, a means for adding a register relative access from the common program area to the shared data area is provided.

  The code generation method of the present invention is a code generation method implemented by a compiler device for an asymmetric multi-core processor, and performs access analysis of a variable based on a result of syntax analysis of a source program, and a variable reference source and reference When obtaining the analysis information of the number of times, arranging the variables based on the analysis information, creating intermediate code in the intermediate language, and generating object code from the intermediate code If it is a common program, adding a code for register relative access from the common program area to the shared data area is included.

  The program of the present invention is a program for causing a computer to execute the processing in the above code generation method. Note that the program of the present invention can be stored in a storage device or a storage medium.

  When there are multiple data areas such as a data area for each core and a shared data area shared between cores as in an asymmetric multi-core processor, all areas can be accessed using register relative access. .

It is a block diagram of the conventional compiler apparatus. It is a block diagram of the code generation process part in the conventional compiler apparatus. It is a block diagram of the address allocation process part in said code generation process part. It is a block diagram of the compiler apparatus of this invention. It is a layout diagram of the target program in the address space at the time of execution. It is a flowchart which shows the code | cord | chord generation process which selects an access method similarly to the past. It is a flowchart which shows the code production | generation process which uses register relative access with respect to all the areas. It is a flowchart which shows the execution process of the object program which uses register relative access with respect to all the areas.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in FIG. 4, the compiler apparatus 100 of the present invention includes a reading unit 101, a lexical analysis unit 102, a syntax analysis unit 103, a variable access analysis unit 104, a variable placement unit 105, and an intermediate language creation unit 106. And an optimization unit 107 and a code generation unit 108.

  The reading unit 101 reads a source program. The source program is a source program (source code) stored in the source program storage unit 110.

  The lexical analysis unit 102 performs lexical analysis of the source program and creates a lexical (token). The lexical analysis unit 102 stores the lexical (token) in the intermediate data storage unit 120.

  The syntax analysis unit 103 performs syntax analysis based on the lexical phrase (token) created by the lexical analysis unit 102, and checks whether the sequence of the lexical phrase (token) is correct according to the grammar. The syntax analysis unit 103 stores the syntax analysis result in the intermediate data storage unit 120.

  The variable access analysis unit 104 performs variable access analysis based on the syntax analysis result obtained by the syntax analysis unit 103 to obtain analysis information of the variable reference source and the reference count. The variable access analysis unit 104 stores this analysis information in the intermediate data storage unit 120.

  The variable placement unit 105 performs variable placement based on the analysis information obtained by the variable access analysis unit 104. The variable placement unit 105 stores the variable placement result in the intermediate data storage unit 120.

  After the variables are arranged, the intermediate language creation unit 106 creates an intermediate code in an intermediate language based on the source program. The intermediate language creation unit 106 stores the intermediate code in the intermediate data storage unit 120.

  The optimization unit 107 optimizes the intermediate code based on various types of information stored in the intermediate data storage unit 120, and increases the speed and size of the intermediate code. The optimization unit 107 stores the optimized intermediate code in the intermediate data storage unit 120.

  The code generation unit 108 generates a code based on the optimized intermediate code, and stores the target program in the target program storage unit 130 when the target program is completed. The target program is an object program (object code) described in an executable format.

[Hardware example]
As an example of the compiler apparatus 100, a computer such as a PC (personal computer), an appliance, a workstation, a main frame, or a supercomputer is assumed. The compiler apparatus 100 may be a virtual machine (Virtual Machine (VM)) constructed on a physical machine.

  As an example of the reading unit 101, an interface (I / F: interface) for acquiring information from an external input device, a storage device, or another computer is assumed. As an example of the input device, a KVM (keyboard / video / mouse), a console, a touch panel, a tablet, or a reading device for various information transmission media can be considered.

  The lexical analysis unit 102, the syntax analysis unit 103, the variable access analysis unit 104, the variable placement unit 105, the intermediate language creation unit 106, the optimization unit 107, and the code generation unit 108 are driven based on a program and execute predetermined processing. And a memory that stores the program and various data.

  As an example of the above processor, a CPU (Central Processing Unit), a microprocessor (microprocessor), a microcontroller, or a semiconductor integrated circuit (Integrated Circuit (IC)) having a dedicated function can be considered.

  Examples of the above memory include a semiconductor storage device such as a RAM (Random Access Memory), a ROM (Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory, and an HDD (HoldSold). An auxiliary storage device such as State Drive), a removable disk such as a DVD (Digital Versatile Disk), a storage medium such as an SD memory card (Secure Digital memory card), or the like is conceivable.

  Note that the processor and the memory may be integrated. For example, in recent years, a single chip such as a microcomputer has been developed. Therefore, a case where a one-chip microcomputer mounted on a computer or the like includes a processor and a memory can be considered.

  Examples of the source program storage unit 110, the intermediate data storage unit 120, and the target program storage unit 130 are installed in the above memory, peripheral devices (external HDD, etc.), and external servers (Web server, file server, etc.). Storage device such as DAS (Direct Attached Storage), FC-SAN (Fibre Channel-Storage Area Network), NAS (Network Attached Storage), IP-SAN (IP-Storage Storage Device). It is done.

  However, actually, it is not limited to these examples.

[Address space when executing the target program]
With reference to FIG. 5, an address space in which a program and data are arranged when an object program generated by the compiler apparatus of the present invention is executed in an asymmetric multi-core processor will be described.

  The address space 200 includes a PE1 program area 201, a PE2 program area 202, a common program area 203, a PE1 data area 204, a PE2 data area 205, and a shared data area 206.

  The PE1 program area 201 and the PE2 program area 202 are program areas for each core.

  The common program area 203 is a common program area shared between cores.

  The PE1 data area 204 and the PE2 data area 205 are data areas for each core.

  The shared data area 206 is a shared data area shared between cores.

  The PE1 program area 201, the PE2 program area 202, the common program area 203, the PE1 data area 204, the PE2 data area 205, and the shared data area 206 are arranged at separate addresses.

  In FIG. 5, the notation starting with “0x” is a hexadecimal number.

  The program area 201 for PE1 is from “0x000000” to “0x003FFF”.

  The PE2 program area 202 extends from “0x004000” to “0x007FFF”.

  The common program area 203 extends from “0x008000” to “0x009FFF”.

  The PE1 data area 204 is from the address “0x100000” to the address “0x13FFFF”.

  The PE2 data area 205 extends from “0x200000” to “0x23FFFF”.

  The shared data area 206 is from “0x300000” to “0x33FFFF”.

[Code generation process to select access method]
With reference to FIG. 6, a code generation process for selecting an access method as in the prior art will be described.

(1) Step S101
The reading unit 101 reads a source program.

(2) Step S102
The lexical analysis unit 102 performs lexical analysis of the source program.

(3) Step S103
The syntax analysis unit 103 performs syntax analysis of the source program.

(4) Step S104
The variable access analysis unit 104 performs variable access analysis based on the syntax analysis result, and acquires analysis information of the variable reference source and the reference count.

(5) Step S105
The variable placement unit 105 places variables based on the above analysis information.

(6) Step S106
After the variables are arranged, the intermediate language creating unit 106 creates an intermediate code of the source program in the intermediate language.

(7) Step S107
The optimization unit 107 optimizes the intermediate code.

(8) Step S108
The code generation unit 108 determines whether the program is a common program when generating code based on the optimized intermediate code. The common program is a common area program shared between cores (a program stored in the common program area). The common program can be executed from any core. Here, the common program is stored in the common program area.

(9) Step S109
In the case of a common program, the code generation unit 108 determines the variable access method to be an absolute address reference.

(10) Step S110
If the code generation unit 108 is not a common program, the code generation unit 108 determines that the variable access method is register relative access.

(11) Step S111
The code generation unit 108 generates a code in accordance with the determined variable access method, and ends the process when the target program is completed.

[Code generation process using register relative access for all areas]
With reference to FIG. 7, a code generation process using register relative access to all areas will be described.

(1) Step S201
The reading unit 101 reads a source program.

(2) Step S202
The lexical analysis unit 102 performs lexical analysis of the source program.

(3) Step S203
The syntax analysis unit 103 performs syntax analysis of the source program.

(4) Step S204
The variable access analysis unit 104 performs variable access analysis based on the syntax analysis result, and acquires analysis information of the variable reference source and the reference count.

(5) Step S205
The variable placement unit 105 places variables based on the above analysis information.

(6) Step S206
After the variables are arranged, the intermediate language creating unit 106 creates an intermediate code of the source program in the intermediate language.

(7) Step S207
The optimization unit 107 optimizes the intermediate code.

(8) Step S208
When generating code based on the optimized intermediate code, the code generation unit 108 determines whether or not it is a common program shared between cores. Here, if the program is a common program, the process proceeds to step S209. If the program is not a common program, the process proceeds to step S213.

(9) Step S209
In the case of a common program, the code generation unit 108 generates a symbol that holds the start address of the common data area as data.

(10) Step S210
The code generation unit 108 adds a code for saving the value of the register relative access register to the save destination (data area for each core, etc.) at the start address of the function arranged in the common program area 203.

(11) Step S211
The code generation unit 108 adds a code for overwriting the symbol (the symbol generated in step S209) holding the start address of the shared data area as data to the register relative access register value.

(12) Step S212
The code generation unit 108 adds a code for restoring the register relative access register value from the save destination (writing back to the saved value) immediately before branching to the caller of the function arranged in the common program area. To do.

(13) Step S213
The code generation unit 108 generates a register relative access code when the above-described code addition processing is completed or when the code addition processing is not a common program. The code generation unit 108 generates all intermediate codes as codes, and ends the process when the target program is completed.

[Execution processing of target program using register relative access to all areas]
With reference to FIG. 8, an operation when the asymmetric multi-core processor executes the above-described target program will be described.

(1) Step S301
The asymmetric multi-core processor branches from processing in the PE1 program area 201 or PE2 program area 202 to processing in the common program area 203. Here, the asymmetric multi-core processor executes the main function of PE1 arranged at address “0x000500” of the PE1 program area 201 in the PE1, which is one of the cores, and addresses “0x008500” in the common program area 203. Call the subfunction located at.

(2) Step S302
The asymmetric multi-core processor executes the subfunction to save the register relative access register value “0x100000” to the address “0x10F000” in the PE1 data area 204 as the save destination. As a result, the asymmetric multi-core processor holds the register relative access register value “0x100000” at the address “0x10F000” in the PE1 data area 204.

(3) Step S303
The asymmetric multi-core processor executes the subfunction and rewrites (overwrites) the register relative access register value “0x100000” to the start address “0x300000” of the shared data area 206. In other words, the asymmetric multi-core processor generates a symbol that holds the start address “0x300000” of the shared data area 206 as data, and overwrites this symbol (the start address of the shared data area 206) in the register relative access register value. To do.

(4) Step S304
The asymmetric multi-core processor executes the subfunction, executes the register relative memory access instruction of the instruction at address “0x008600” in the common program area 203, and accesses the data allocated to the address “0x300100” in the shared data area 206 To do.

(5) Step S305
The asymmetric multi-core processor executes the subfunction to write back (overwrite) the value “0x100000” saved in the “0x10F000” address of the PE1 data area 204 as the save destination to the register relative access register value. ). As a result, the asymmetric multi-core processor restores the register relative access register value “0x100000” held at the address “0x10F000” in the PE1 data area 204.

(6) Step S306
The asymmetric multi-core processor executes the subfunction and returns from the address “0x008800” of the common program area 203 to the main function of the address “0x000504” of PE1.

  As mentioned above, when executing a program in the common program area, the address held by the register relative access register can be placed at the start address of the shared data area, so the shared data area can be accessed by register relative access, There is an effect that the shared data area can be accessed by register relative access when executing the program in the program area.

  In addition, by using register relative access, the number of codes can be reduced, and the generated code can be executed more quickly.

<Features of the present invention>
The compiler apparatus of the present invention is a compiler apparatus for an asymmetric multi-core processor, and determines whether or not a common program is used when generating object code from intermediate code. A code for register-relative access to an area is generated.

  Specifically, the compiler apparatus of the present invention is a compiler apparatus for an asymmetric multi-core processor, and is shared when there are a plurality of data areas such as a data area for each core and a shared data area shared between the cores. A means for generating a symbol that holds the start address of the data area as data, and a code for saving the value of the register relative access register to the save destination (data area for each core, etc.) at the start address of the function in the common program area To add a code that overwrites the generated symbol (the start address of the shared data area) to the register relative access register value, and immediately before processing to branch to the function call source of the common program Added code to write back (overwrite) the value saved in the save destination to the relative access register value ; And a that means.

  The code generation method of the present invention is a code generation method for a compiler device for an asymmetric multi-core processor, which includes a step of generating a symbol that holds the start address of a shared data area as data, and a function of a common program area. Adding a code that saves the register-relative access register value to the save address (data area for each core, etc.) at the start address, and the register-relative access register value to the symbol (the head of the shared data area) Code that overwrites the value saved in the save destination in the register relative access register value immediately before the process of adding the code that overwrites the address) and the process that branches to the function call source of the common program And a step of adding.

  This allows register relative access to all areas.

  As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

DESCRIPTION OF SYMBOLS 1 ... Parsing processing part 2 ... Intermediate language level optimization part 3 ... Code generation processing part 4 ... Source program storage part 5 ... Intermediate language storage part 6 ... Object program storage part 7 ... Node conversion processing part 8 ... Register allocation processing part DESCRIPTION OF SYMBOLS 9 ... Address allocation process part 10 ... Code output process part 11 ... Node storage part 12 (12-i, i = 1-n) ... Data management information table 13 ... Data management information table chain mechanism 14 ... Data access frequency registration part 15 Data management information table chain rearrangement processing unit 16 Data address allocation processing unit 100 Compiler device 101 Reading unit 102 Lexical analysis unit 103 Variable access analysis unit 104 Syntactic analysis unit 105 Variable allocation unit 106 Intermediate Word creation unit 107 ... optimization unit 108 ... code generation unit 11 Primitive program storage unit 120 ... Intermediate data storage unit 130 ... Target program storage unit 200 ... Address space 201 ... PE1 program area 202 ... PE2 program area 203 ... Common program area 204 ... PE1 data area 205 ... PE2 data area 206 ... Shared data area

Claims (5)

A compiler device for an asymmetric multi-core processor,
Based on the syntax analysis result of the source program, a means for performing variable access analysis and obtaining analysis information of the variable reference source and the reference count;
Means for creating an intermediate code in an intermediate language after arranging variables based on the analysis information;
A compiler apparatus comprising: means for determining whether or not the object code is a common program when generating the object code from the intermediate code, and in the case of the common program, adding a code for register relative access from the common program area to the shared data area. The compiler apparatus according to claim 1,
Means for generating a symbol that retains the start address of the shared data area as data when there is a plurality of data areas of a data area for each core and a shared data area shared between the cores;
Means for adding a code for saving the value of the register relative access register to the data area for each core at the start address of the function of the common program area;
Means for adding a code for overwriting the symbol to a value of the register relative access register;
A compiler apparatus further comprising means for adding a code for rewriting the value of the register relative access register to the value saved in the data area for each core immediately before the process of branching to the function caller. A code generation method implemented by a compiler device for an asymmetric multi-core processor,
Based on the syntax analysis result of the source program, access analysis of the variable is performed, and analysis information of the variable reference source and the reference count is obtained.
Based on the analysis information, after arranging variables, creating intermediate code in an intermediate language;
A code generation method comprising: determining whether a common program is generated when generating an object code from the intermediate code, and adding a code for register relative access from a common program area to a shared data area if the program is a common program. The code generation method according to claim 3,
When there are a plurality of data areas including a data area for each core and a shared data area shared between the cores, generating a symbol that holds the start address of the shared data area as data;
Adding a code for saving the value of the register relative access register to the data area for each core at the start address of the function of the common program area;
Adding a code to overwrite the symbol to the register relative access register value;
A code generation method further comprising adding a code for rewriting the value of the register relative access register to a value saved in the data area for each core immediately before the process of branching to the function caller.   A program for causing a computer to execute the code generation method according to claim 3 or 4.

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