JP2012113116A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display capable of operating a liquid crystal display panel with a small power consumption.SOLUTION: In a liquid crystal display, an output multiplexer 27 in a source driver outputs a voltage which is equal to a voltage that a D-A converter outputted to each source line, from an output part 45 to the source line when a latch part reads a new data of one row. In addition, an exclusive OR of MSB between an image data in the row and an image data in a row just before the row, each corresponding to the source line, is calculated in advance. Each of a first switch 41 and a second switch 42 disposed at end of the output part 45 connects a corresponding source line to a first capacitor 31 or a second capacitor 32, respectively, when a signal directing the latch part to acquire data, a polarity control signal, and the resultant exclusive OR of a column corresponding to the switch itself satisfy predetermined conditions.

Description

  The present invention relates to an active matrix liquid crystal display device.

  In an active matrix liquid crystal display device, a liquid crystal is generally sandwiched between a common electrode and a plurality of pixel electrodes. Each pixel electrode is provided with an active element such as a TFT (Thin Film Transistor), and it is possible to control whether or not to set the voltage of the source wiring to the pixel electrode using the active element.

  The common electrode is set to a predetermined potential, and each pixel electrode is set to a potential corresponding to each pixel value of the display image. Here, a state in which the potential of the pixel electrode is higher than the potential of the common electrode is referred to as positive polarity. A state in which the potential of the pixel electrode is lower than the potential of the common electrode is referred to as negative polarity.

FIG. 23 is an explanatory diagram showing an example of the potential of the common electrode and the potential for setting the pixel to white or black with each polarity. Here, the case of normally white will be described as an example. The potential of the common electrode referred to as _{V COM. V} pb shown in FIG. _{23, V pw, V COM,} V nw, V nb each represent a _potential, and a _{V nb <V nw <V COM} <V pw <V pb. When the pixel is displayed in black with positive polarity, the potential of the source line connected to the pixel is set to V _pb , and when the pixel is displayed in white with positive polarity, the source line connected to the pixel What is necessary is _just to set an electric potential to _Vpw . In addition, when a pixel is set to be halftone display with positive polarity, the potential of the source line connected to the pixel may be set higher than V _{pw and} lower than V _pb . When the pixel is displayed in black with negative polarity, the potential of the source line connected to the pixel is set to V _nb , and when the pixel is displayed in white with negative polarity, the source connected to the pixel The line potential may be set to V _nw . Further, in the case where a pixel is set to a halftone display with a negative polarity, the potential of the source line connected to the pixel may be set to a potential lower than V _{nw and} higher than V _nb .

  In an active matrix liquid crystal display device, it is preferable to drive so that pixels with the same polarity are less likely to be continuously arranged in order to prevent image deterioration such as occurrence of crosstalk. FIG. 24 is an explanatory diagram showing a general liquid crystal display device. As shown in FIG. 24, pixel electrodes 50 are arranged in a matrix, and each pixel electrode is provided with a TFT 51.

As shown in FIG. 24, the source driver 60 to set the potential of each source line _S 1 to S _n are provided, the output terminal _D 1 to D _n of the source driver 60, the source lines are connected. In the example shown in FIG. 24, each TFT 51 is provided on the left side of the pixel electrode 50 and connected to a source line existing on the left side of the pixel electrode 50. Further, gate lines G ₁ , G ₂ , G ₃ ,... Are provided for each row of pixels, and each gate line is connected to the TFT 51 of each pixel electrode in that row. The gate lines are sequentially selected, and the TFT 51 in the selected row brings the pixel electrode 50 and the source line into a conductive state. As a result, the pixel electrode 50 in the selected row is controlled to be equipotential with the source line existing on the left side of the pixel electrode. Further, the TFT 51 in the non-selected row brings the pixel electrode 50 and the source line into a non-conductive state. The gate lines are sequentially selected, and the source driver 60 sets the potential of each source line to a potential corresponding to the pixel value of each pixel in the selected row, so that an image corresponding to the image data is displayed.

In the general liquid crystal display device shown in FIG. 24, the source driver 60 controls the adjacent columns to have different polarities as follows, for example. The source driver 60 sets the potentials of the source lines S ₁ , S ₃ , S ₅ ,... In the odd-numbered columns to a potential higher than the potential V _COM of the common electrode (not shown) in a certain frame period. The potentials of the source lines S ₂ , S ₄ , S ₆ ,... In the even-numbered columns are set to potentials lower than V _COM . As a result, as shown in FIG. 24, the polarities are alternately different for each column. In FIG. 24, FIG. 25 described later, etc., “+” represents positive polarity and “−” represents negative polarity. The source driver 60 switches the potential of the source line so as to invert the polarity of each column every time the frame period is switched. That is, in the next frame period after the above-described frame period, the source driver 60 sets the potentials of the source lines S ₁ , S ₃ , S ₅ ,... In the odd-numbered columns to be lower than the potential V _{COM of the} common electrode. The potentials of the source lines S ₂ , S ₄ , S ₆ ,... In the even-numbered columns are set higher than V _COM . As a result, as a result, the polarity of each pixel is opposite to the polarity of each pixel shown in FIG. Such a polarity control mode is called “column inversion”.

In addition, as a polarity control method, there is an aspect in which control is performed so that the polarities of pixels adjacent vertically and horizontally are different. Such a control mode is called “dot inversion”. In the case of dot inversion, the source driver 60 sets the potentials of the source lines S ₁ , S ₃ , S ₅ ,... In the odd-numbered columns when selecting the gate lines in the odd-numbered rows in a certain frame period. Are set higher than the potential V _{COM of the} common electrode, and the potentials of the source lines S ₂ , S ₄ , S ₆ ,... In the even-numbered columns are set lower than V _COM . Also, the source driver 60 sets the potentials of the source lines S ₁ , S ₃ , S _{5 ,.} The potentials of the source lines S ₂ , S ₄ , S ₆ ,... In the even-numbered columns are set higher than V _COM . As a result, as shown in FIG. 25, the adjacent pixels are controlled to be alternately positive and negative.

Further, the source driver 60 switches the potential of the source line so as to invert the polarity of each pixel every time the frame period is switched. That is, in the next frame period of the frame period, the source driver 60, during odd-numbered selection gate lines of rows, while an odd-numbered source line of the potential of the column to a potential lower than V _COM, the even The potential of the source line in the second column is set to a potential higher than _VCOM . The source driver 60, during even-numbered selection gate lines of rows, while an odd-numbered source line potential of the column to a potential higher than V _COM, V _COM source line of the potential of the even-numbered column A lower potential is set. As a result, the polarity of each pixel is opposite to the polarity of each pixel shown in FIG.

In the dot inversion, each selected row is switched, by changing the potential of the individual source lines or changing the potential lower than V _COM from the potentials higher than V _COM or a potential higher than V _COM from potentials lower than V _COM Or As a result, power consumption increases.

  There has been proposed a liquid crystal display device that can be controlled so that the polarities of adjacent pixels are different while suppressing power consumption (see Patent Document 1). In the liquid crystal display device described in Patent Document 1, TFTs connected to odd-numbered gate lines are formed on the left side of the source lines, and TFTs connected to even-numbered gate lines are formed on the right side of the source lines. . Then, the polarity of each source line is made constant within one frame period, and the polarity is inverted every frame period, so that power consumption is reduced while realizing dot inversion.

Patent Document 2 describes a liquid crystal display device that suppresses heat generation of a source driver by providing a precharge period at the beginning of each horizontal scanning period. In the invention described in Patent Document 2, three types of potentials are used as potentials (charge share potentials) set in the precharge period. The first charge share potential is a potential equal to the common electrode potential _VCOM . The second charge share potential is a substantially intermediate potential between the positive signal potential corresponding to the lowest gradation and the positive signal potential corresponding to the highest gradation. The third charge share potential is a substantially intermediate potential between the negative signal potential corresponding to the lowest gradation and the negative signal potential corresponding to the highest gradation.

  In the invention described in Patent Document 2, for example, in the first horizontal scanning period, the signal potential (positive polarity) is output after the first charge share potential is supplied to the data signal line. In each of the second to 48th horizontal scanning periods, the signal potential (positive polarity) is output after the second charge share potential is supplied to the data signal line. Further, in the 49th horizontal scanning period, the first charge share potential is supplied to the data signal line, and then the signal potential (negative polarity) is output. Then, in each of the 50th to 96th horizontal scanning periods, the signal potential (negative polarity) is output after the third charge share potential is supplied to the data signal line.

  Japanese Patent Application Laid-Open No. 2004-228688 discloses that in a liquid crystal display device, gradation information of two line data during a period from the time when data is input to the timing controller for each line to the time when data supply to the liquid crystal display panel is started. It is described to judge.

JP 2009-181100 A (paragraphs 0008-0018, FIG. 1-6) JP 2010-15057 A (paragraphs 0018-0033) JP 2009-9088 A (paragraph 0062)

  In the liquid crystal display device described in Patent Document 2, a signal potential is output after supplying a charge share potential to a data signal line in a precharge period. It is conceivable to reduce power consumption by applying this potential supply method to the column inversion described with reference to FIG. However, in the method described in Patent Document 2, since the charge share potential is always supplied at the beginning of each horizontal scanning period, there is a possibility that extra power is consumed. For example, it is assumed that the pixels of the highest gradation are arranged in the positive polarity column shown in FIG. In this case, with respect to the source line of the column, after supplying the second charge share potential, setting to the positive signal potential corresponding to the highest gradation is repeated. Then, the potential of the source line is lowered from the positive signal potential corresponding to the highest gradation to the second charge share potential and is increased again to the positive signal potential corresponding to the highest gradation. Excessive power consumption will occur.

  In the case of dot inversion, the power consumption can be reduced by the driving method described in Patent Document 1, but it is preferable that the power consumption can be further reduced.

  Therefore, an object of the present invention is to provide a liquid crystal display device that can drive a liquid crystal display panel with low power consumption.

  The liquid crystal display device according to the present invention includes a common electrode, pixel electrodes arranged in a matrix, source lines arranged along the column direction of the pixel electrodes, and gate lines arranged along the row direction of the pixel electrodes. An active matrix type liquid crystal display panel (liquid crystal display panels 5 and 5a), a gate driver (for example, gate driver 3) for driving the gate lines line-sequentially, and setting the potential of the source line in accordance with image data A source driver (for example, source drivers 2 and 2a) and a control unit (for example, control unit 1) for controlling the gate driver and the source driver, and the control unit selects a pixel electrode in each row with respect to the source driver; The selection period defining pulse signal (eg, STB) that regulates the potential and the potential set for each source line is the common electrode potential. A polarity control signal (e.g., POL) that defines whether the level is higher or lower, and the level of the polarity control signal is set to a first level (e.g., high level) and a second level (e.g., high level) for each frame period. , Low level), and data holding means (for example, latch units 23 and 23a) for holding one line of image data defining the potential to be set for each source line for each selection period by the source driver; Next-row data holding means (for example, line buffers 22 and 22a) that holds image data for the next row of image data for one row held by the data holding means, and the same number of potential output terminals as the source lines are provided. When outputting a potential corresponding to the image data held by the data holding means from the potential output terminal corresponding to each source line, and outputting the potential from each potential output terminal, When the control signal is at the first level, the odd-numbered potential output terminal from the left outputs a potential higher than the common electrode potential, and the even-numbered potential output terminal from the left outputs a potential lower than the common electrode potential. When the polarity control signal is at the second level, a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left, and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left. Output unit (for example, D-A converters 25 and 25a) and an output unit (for example, output) that outputs a potential equal to the potential output from the potential output terminal of the potential output unit to the source line for each source line. Unit 45) and a first capacitor (for example, first capacitor 31) in which one electrode is set to a specific potential (for example, output converters 27 and 27a). ) And the second capacitor (for example, the second capacitor 32) whose one electrode is set to a specific potential, and the same source line, the value of the most significant bit of the image data and the most significant bit of the next image data And an exclusive OR operation means (for example, each EXOR circuit) for comparing the values of the output value and the potential setting means at the connection end of the output unit and the source line. And a first switch that turns on or off the connection between the electrode of the first capacitor and the electrode that is not set to the specific potential, and the source line and the electrode of the second capacitor that are set to the specific potential A second switch that turns on or off the connection with the non-connected electrode, and the data holding means outputs image data for one row from the next row data holding means when the selection period defining pulse signal rises. The first switch corresponding to the odd-numbered source line from the left has detected the rising edge of the selection period defining pulse signal, the polarity control signal is at the first level, and the source line On the condition that the exclusive OR calculation result corresponding to 1 is all satisfied, the connection between the source line and the electrode of the first capacitor is turned on, and the odd-numbered source line from the left is supported. That the second switch detects the rising edge of the selection period defining pulse signal, the polarity control signal is at the second level, and the calculation result of the exclusive OR corresponding to the source line is 1. On the condition that all are satisfied, the connection between the source line and the electrode of the second capacitor is turned on, and the first switch corresponding to the even-numbered source line from the left is turned on. That H detects the rising edge of the selection period defining pulse signal, the polarity control signal is at the second level, and the exclusive OR calculation result corresponding to the source line is 1. On the condition that the connection between the source line and the electrode of the first capacitor is turned on, the second switch corresponding to the even-numbered source line from the left has detected the rising edge of the selection period defining pulse signal, On condition that the control signal is at the first level and that the calculation result of the exclusive OR corresponding to the source line is all 1, the source line and the electrode of the second capacitor Is turned on and the output section corresponding to the source line is turned off when the source line is connected to the first capacitor or the second capacitor. A potential is set to the source line after the signal is turned off.

  The image data for calculating the exclusive OR is the image data held in the data holding means, and the next image data for calculating the exclusive OR is the image data held in the next row data holding means. There may be.

  The first switch corresponding to the odd-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, the polarity control signal is at the second level, And a new frame period on condition that all the image data corresponding to the source line held by the data holding means before the rising edge of the selection period defining pulse signal is higher than the halftone are satisfied. During the first period, which is the predetermined period at the beginning of the period in which the selection period defining pulse signal rises for the first time after the start of the source line, the source line and the electrode of the first capacitor that are not set to a specific potential The second switch corresponding to the odd-numbered source line from the left is turned on first after the start of a new frame period. The rise of the pulse signal is detected, the polarity control signal is at the first level, and the image data corresponding to the source line held by the data holding means before the rise of the selection period defining pulse signal is detected. On the condition that all the gradations higher than the halftone are satisfied, during the first period, the source line and the electrode of the second capacitor that is not set to a specific potential The connection is turned on, and the first switch corresponding to the even-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, and the polarity control signal is set to the first level. And the image data corresponding to the source line held by the data holding means before the rising edge of the selection period defining pulse signal is halftone. On the condition that all the higher gradations are satisfied, the connection between the source line and the electrode of the first capacitor is turned on during the first period, and it corresponds to the even-numbered source line from the left. The second switch first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, the polarity control signal is at the second level, and before the rising of the selection period defining pulse signal On the condition that the image data corresponding to the source line held by the data holding means is all higher in gradation than the halftone, the source line and the second capacitor are satisfied during the first period. The structure which turns on the connection with the electrode of this may be sufficient.

  The first switch corresponding to the odd-numbered source line from the left has the selection period defining pulse signal rising first after the start of a new frame period, the polarity control signal is at the first level, and On condition that all of the image data corresponding to the source line among the image data for one row taken in by the data holding means by the rising edge of the selection period defining pulse signal is satisfied is a gradation higher than the halftone, During the second period, which is a predetermined period after the first period, the connection between the source line and the electrode of the first capacitor that is not set to the specific potential is turned on, and the odd number from the left In the second switch corresponding to the source line of the first time, the selection period defining pulse signal rises first after the start of a new frame period, and the polarity control signal is And the image data corresponding to the source line among the image data for one row taken in by the data holding means at the rising edge of the selection period defining pulse signal has a gradation higher than the halftone. On the condition that all are satisfied, during the second period, the connection between the source line and the electrode of the second capacitor that is not set to the specific potential is turned on, and the even number from the left The first switch corresponding to the source line is such that the selection period defining pulse signal first rises after the start of a new frame period, the polarity control signal is at the second level, and the selection period defining pulse signal The image data corresponding to the source line is higher than the halftone among the image data for one row captured by the data holding means at the rise of The second switch corresponding to the even-numbered source line from the left is turned on during the second period on the condition that all of the keys are satisfied. However, the data holding means captures the first selection period defining pulse signal after the start of a new frame period, the polarity control signal being at the first level, and the rising of the selection period defining pulse signal. On the condition that the image data corresponding to the source line among the image data for one line is all satisfied to have a gradation higher than the halftone, the source line and the second A configuration in which the connection with the electrode of the capacitor is turned on may be employed.

  The specific potential may be a common electrode potential.

  The liquid crystal display panel may include a source line on a predetermined side of each column of pixel electrodes, and each pixel electrode may be connected to a source line existing on a predetermined side.

  The liquid crystal display panel includes source lines provided on the left side of each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, and pixel electrodes in odd-numbered rows are among the source lines existing on both sides of the pixel electrodes. Even if the pixel electrode in the even-numbered row is connected to the source line on the predetermined side, and the source line on both sides of the pixel electrode is connected to the source line on the opposite side to the predetermined side. Good.

  According to the present invention, a liquid crystal display panel can be driven with low power consumption.

Explanatory drawing which shows the example of the 1st Embodiment of this invention. Explanatory drawing which shows the example of the liquid crystal display panel driven by 1st Embodiment. Explanatory drawing which shows the example of a connection of a pixel electrode, a source line, and a gate line. Explanatory drawing which shows the example of STV and a row switching signal. Explanatory drawing which shows the structural example of a source driver. Explanatory drawing which shows the example of CLK. Explanatory drawing which shows the example of a change of STB. Explanatory drawing which shows the example of switching of POL. Explanatory drawing of the comparison process of the image data by a latch part. Explanatory drawing which shows the structural example of an output multiplexer. Explanatory drawing which shows the relationship between STB and CSD output timing. Explanatory drawing which shows the state in which POL is high level. Explanatory drawing showing a state in which POL is at a low level Explanatory drawing which shows the example of output timing charts, such as STV and STVD. Explanatory drawing which shows the example of the electrical potential change at the time of switching of a frame period. Explanatory drawing which shows a 1st period and a 2nd period. Explanatory drawing which shows the example of the electrical potential change at the time of switching of a frame period. Explanatory drawing which shows the example of a structure which provides D flip-flop doubly and performs the exclusive OR operation of MSB. Explanatory drawing which shows the example of the liquid crystal display panel driven by 2nd Embodiment. Explanatory drawing which shows the structural example of the source driver in 2nd Embodiment. Explanatory drawing of the comparison process of the image data by the latch part in 2nd Embodiment. Explanatory drawing which shows the structural example of the output multiplexer in 2nd Embodiment. Explanatory drawing which shows the example of the electric potential which sets a pixel to white and black by the electric potential of a common electrode, and each polarity. Explanatory drawing which shows a general liquid crystal display device. Explanatory drawing which shows the other example of a liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, for the sake of simplicity of explanation, a case where the source driver reads data for one line serially will be described as an example.

[Embodiment 1]
FIG. 1 is an explanatory diagram showing an example of the first embodiment of the present invention. The liquid crystal display device according to the present invention includes a control unit 1, a source driver 2, a gate driver 3, a liquid crystal display panel 5, and a power supply unit 4. The power supply unit 4 supplies power to the source driver 2 and the gate driver 3.

  FIG. 2 is an explanatory diagram showing an example of the liquid crystal display panel 5 driven in the first embodiment. The liquid crystal display panel 5 sandwiches liquid crystal (not shown) between a plurality of pixel electrodes 50 arranged in a matrix and a common electrode (not shown in FIG. 2), and the liquid crystal is connected to the pixel electrode 50 and the common electrode. An image is displayed by changing to a state corresponding to the potential difference between the two. The liquid crystal display panel 5 includes a pair of substrates (not shown), has a plurality of pixel electrodes 50 arranged in a matrix on one substrate, and has a common electrode on the other substrate. Two substrates are arranged so that the pixel electrode group 50 and the common electrode face each other, and liquid crystal is injected between the substrates.

The liquid crystal display panel 5 includes a source line on the left side of each column of pixel electrodes, for example. In this example, the number of pixel electrode columns is n, and the number of source lines is n. Each source line is represented as _S 1 to S _n. Each individual source line is connected to a source driver 2 (see FIG. 1).

  Each pixel electrode 50 is provided with an active element 51. In the following description, a case where the active element 51 is a TFT (Thin Film Transistor) will be described as an example. However, an active element other than a TFT may be provided in each pixel electrode 50. The source of each TFT 51 is connected to the source line, and the drain of each TFT 51 is connected to the pixel electrode 50.

In addition, the liquid crystal display panel 5 includes gate lines G ₁ , G ₂ , G ₃ ,... For each row of pixel electrodes arranged in a matrix. In FIG. 2, illustration of gate lines in the fourth and subsequent rows is omitted. The gate line is connected to the gate of the TFT 51 provided in each pixel electrode 50 in the corresponding row. For example, gate line G ₁ shown in FIG. 2 is connected to the gate of TFT51 of the first row pixel electrodes.

FIG. 3 is an explanatory diagram illustrating an example of connection between a pixel electrode, a source line, and a gate line. In Figure 3, the pixel electrode 50 is connected to the gate line G _i of the i-th row, also as an example a case connected to the source line S _k of k-th column. Gate 51 _a of the TFT51 is connected to the gate line _{G i.} Further, TFT 51 has a source connected to 51 _c to the source line _{S k,} and a drain connected 51 _b to the pixel electrode 50.

  The gate driver 3 (see FIG. 1) sets the potential of each gate line. The gate driver 3 sequentially selects the gate lines one by one, sets the selected gate lines to the selected potential, and sets the unselected gate lines to the unselected potential. Accordingly, each row is selected one by one.

  The control unit 1 describes a control signal for instructing the gate driver 1 to start one frame period (hereinafter referred to as STV) and a control signal for instructing switching of a selected row (hereinafter referred to as row switching signal). ). FIG. 4 is an explanatory diagram showing examples of STV and row switching signals. The period from the rising edge of the row switching signal to the next rising edge of the row switching signal is the period of the row switching signal, and is a period for setting the potential at the time of selection for one gate line. In addition, the control unit 1 sets STV to a high level at the start of one frame period, and sets STV to a low level in other periods. That is, the control unit 1 notifies the start of the frame period by setting STV to a high level. When the gate driver 3 detects the rising edge of the row switching signal while the STV is at the high level, the gate driver 3 sets the gate line of the first row to the potential at the time of selection and the gate line of the other row is not selected Set to potential. Thereafter, each time the gate driver detects the rising edge of the row switching signal, the gate driver sequentially switches the gate line set to the potential at the time of selection.

Each of the TFTs 51 (see FIGS. 2 and 3) sets the drain and the source in a conductive state when the gate potential is set to the selected potential, and the drain and the source when the gate potential is set to the non-selected potential. Turn off the source. Accordingly, each pixel electrode in the selected row is equipotential with the source line connected via the TFT. In addition, each pixel electrode in a non-selected row is in a non-conductive state with the source line. In the example shown in FIG. 3 is selected gate line G _i is the gate 51 _a is set to the selection period potential, it becomes the conductive state and the drain 51 _b and the source 51 _c, and the source line S _k is the pixel electrode 50 It becomes equipotential. Then, the liquid crystal state between the pixel electrode 50 and the common electrode 55 is defined according to the potential difference between the potential V _COM of the common electrode 55 and the potential of the pixel electrode 50, and the display state in this pixel is determined.

The power supply unit 4 supplies the gate driver 3 with a voltage that becomes a selected potential and a non-selected potential. Further, the power supply unit 4 supplies the source driver 2 with voltages V _{0 to} V ₄ , V _{5 to} V ₈ , and V _COM . V _COM is a potential set to the common electrode 55 (see FIG. 3). V ₀ ~V _{3 is} higher than _{V COM voltage,} V 4 ~V _{7 is} lower than _{V COM} voltage. Here, it is assumed that V ₇ <V ₆ <V ₅ <V ₄ <V _COM <V ₃ <V ₂ <V ₁ <V ₀ . In this example, the case where the power supply unit 4 supplies V _{0 to} V ₃ as voltages for positive polarity display and V _{4 to} V ₇ as voltages for negative polarity display will be described as an example. To do. In this example, in order to simplify the explanation, an example in which four gradation display is performed by V _{0 to} V ₃ at the time of positive polarity driving and four gradation display is performed by V _{4 to} V ₇ at the time of negative polarity driving is taken as an example. explain. However, the voltages supplied from the power supply unit 4 for positive and negative display are not limited to four types, and the number of gradations is not limited to four gradations. Further, in the case of each of the positive polarity and the negative polarity, a case where the power supply unit 4 supplies the same number of types of voltages as the number of gradations to the source driver 2 will be described as an example. A DA converter 25), which will be described later, may divide the supplied voltage and generate each potential corresponding to a larger number of gradations than the type of the supplied voltage.

The source driver 2 (see FIG. 1), under the control of the control unit 1 sets the potential corresponding to image data of each pixel of the selected row to the respective source lines S ₁ to S _n. As a result, the pixel electrode in the selected row has a potential corresponding to the image data.

FIG. 5 is an explanatory diagram showing a configuration example of the source driver 2. The source driver 2 includes a shift register 21, a line buffer 22, a latch unit 23, a level shifter 24, a DA converter 25, a buffer 26, an output multiplexer 27, a mode control unit 28, and a V _COM buffer 29. And a first capacitor 31 and a second capacitor 32. As already described, in this embodiment, the number of source lines of the liquid crystal display panel 5 is n.

  Control signals CLK and STH are input to the shift register 21 from the control unit 1. CLK is a clock signal input from the control unit 1. FIG. 6 shows an example of CLK. The shift register 21 includes n signal output terminals equal to the number of source lines. The shift register 21 outputs a data read instruction signal from one signal output terminal to the signal input terminal of the line buffer 22 every time CLK is input (that is, every rising edge of CLK). In this example, the shift register 21 outputs a data reading instruction signal in order from the left signal output terminal every time CLK is input. However, the direction of the output terminal that sequentially outputs the data reading instruction signal is not limited to the left side, and may be output sequentially from the right signal output terminal. The data reading instruction signal is a signal for instructing the line buffer 22 to take in image data.

  The control signal STH is a signal for instructing the control unit 1 (see FIG. 1) to start capturing data for one line. For example, when instructing the output start of the data reading instruction signal from the leftmost signal output terminal, the control unit 1 sets STH to a high level and sets STH to a low level in other periods. If the shift register 21 detects the rising edge of CLK when STH is at a high level, the shift register 21 outputs a data read instruction signal from the leftmost signal output terminal. Thereafter, the shift register 21 sequentially switches the signal output end each time a rising edge of CLK is detected.

  In this example, the line buffer 22 includes signal input terminals corresponding to the signal output terminals of the shift register 21. Each time a data reading instruction signal is input to the signal input terminal, one line of image data is read out of one line of image data. For example, when a data reading instruction signal is input to the i-th signal input terminal from the left, the image data of the i-th pixel from the left in one line is read. The line buffer 22 holds the read individual image data. These image data are pixel values representing the gradation of individual pixels in one line.

  Further, the control unit 1 inputs a control signal STB to the source driver 2. STB is a control signal that specifies the selection period of each row. FIG. 7 is an explanatory diagram showing an example of STB change. The period from the falling edge to the rising edge of STB is a selection period of one row in the liquid crystal display panel 5. The control unit 1 outputs CLK so that a data read instruction signal is output from each signal output terminal of the shift register 21 within one cycle of STB. Therefore, one line of image data is held in the line buffer 22 before the end of one cycle of STB. The line buffer 22 has n data output terminals, and the latch unit 23 has n data input terminals. The image data for one line is simultaneously read from the line buffer 22 into the latch unit 23 via these data output terminals and data input terminals.

  The timing at which the latch unit 23 reads data from the line buffer 22 is defined by the STB. For example, the latch unit 23 collectively reads image data for one line for each rising edge of the STB. In each cycle of the STB, reading of image data for one line in the line buffer 22 is completed before the rising edge of the STB, and the latch unit 23 at the rising edge of the STB Read image data. At the rising edge of the STB, the latch unit 23, the level shifter 24, the DA converter 25, the buffer 26, and the output multiplexer 27 operate, and the output multiplexer 27 corresponds to the image data in each column on each source line of the liquid crystal display panel 5. Set the potential. A series of operations of the latch unit 23, the level shifter 24, the DA converter 25, the buffer 26, and the output multiplexer 27 will be described.

  The latch unit 23 has n potential output terminals corresponding to n data input terminals. The latch unit 23 outputs a potential corresponding to the gradation represented by the image data read from each data input terminal from a potential output terminal corresponding to the data input terminal. For example, a potential corresponding to the gradation represented by the image data read from the i-th data input terminal from the left is output from the i-th potential output terminal from the left. In this way, the latch unit 23 outputs each potential corresponding to each image data for one line.

  The latch unit 23 also reads the image for one row read at the leading edge of the previous STB at the timing when the line buffer 22 has completed holding the image data for the next row before the STB rises. The data and image data for one row held in the line buffer 22 are compared for each pixel, and a control signal corresponding to the comparison result is output to the output multiplexer. This control signal is referred to as CSD. The image data comparison process and CSD in the latch unit 23 will be described later.

  The level shifter 24 has n potential input terminals and n potential output terminals. The n potential input terminals of the level shifter 24 are connected to the n potential output terminals of the latch unit 23 on a one-to-one basis. The level shifter 24 performs level shift on the potential input from the latch unit 23 to the potential input terminal, and outputs the power after the level shift from the potential output terminal. Each potential input terminal and each potential output terminal of the level shifter 24 also have a one-to-one correspondence. For example, when the level shifter 24 performs level shift on the potential input to the i th potential input terminal from the left, the level shifter 24 outputs the potential after the level shift from the i th potential output terminal from the left.

The DA converter 25 has n potential input terminals and n potential output terminals. The n potential input terminals of the DA converter 25 are connected to the respective potential output terminals of the level shifter 24 on a one-to-one basis. The DA converter 25 converts the potential input from the level shifter 24 to each potential input terminal into an analog voltage and outputs the analog voltage from each potential output terminal. The D-A converter 25 receives the voltages V _{0 to} V ₃ and V _{4 to} V ₇ from the power supply unit 4 (see FIG. 1). Then, the DA converter 25 outputs V _{0 to} V ₃ and V _{4 to} V ₇ input from the power supply unit 4 as potentials after analog conversion. That is, the DA converter 25 outputs the level-shifted potential output from the latch unit 23 in accordance with the value of each image data, and converts the potential into one of the potentials corresponding to the four gradations. However, here, a case where the gradation of the image is four gradations will be described as an example. However, the type of voltage input to the DA converter 25 is not limited to V _{0 to} V ₇ , and the image The gradation is not limited to 4 gradations. Further, the DA converter 25 may divide the input voltage and output potentials corresponding to more types of gradations. These points are the same in other embodiments described later.

Further, the DA converter 25 receives the control signal POL output from the control unit 1 (see FIG. 1). POL is a control signal that defines whether the potential of each source line is higher or lower than the common electrode. D-A converter 25, POL is depending on whether the low level is a high level, the output potential of each potential output terminal or to potentials higher than V _COM, switches or become potentials lower than V _COM. Specifically, D-A converter 25, when POL is at a high level, the output potential of the odd-numbered each potential output terminal from the left and potentials higher than V _COM, the even-numbered each potential output terminals from the left _{Is set} to a potential lower than VCOM. Conversely, when the POL is at a low level, D-A converter 25, the output potential of the odd-numbered each potential output terminal from the left and potentials lower than V _COM, the even-numbered each potential output terminals from the left output the potential is higher than _{V COM} potential.

That is, when POL is at a high level, any potential of V _{0 to} V ₃ is output from the odd-numbered potential output terminal from the left of the DA converter 25, and even-numbered potential output from the left. From the end, any potential among V _{4 to} V ₇ is output. Conversely, when POL is at a low level, the odd-numbered potential output terminal from the left of the DA converter 25 outputs any potential from V _{4 to} V ₇ , and the even-numbered potential from the left. From the output end, any potential from V _{0 to} V ₃ is output.

  Further, in the present embodiment, the control unit 1 switches the POL alternately between a high level and a low level every frame period. FIG. 8 is an explanatory diagram showing an example of POL switching. Although FIG. 8 shows a case where POL is changed from high level to low level when the frame period is switched, the control unit 1 switches POL from low level to high level when the next frame period is switched.

As described above, since POL is switched every frame period, the output potential from each potential output terminal in the DA converter 25 is higher than V _COM or from V _COM within one frame period. It remains at a low potential. As a result, the potential of each source line is also maintained at a potential higher than V _COM or lower than V _COM within one frame period. As a result, by using the liquid crystal display panel 5 (see FIG. 2), “column inversion” is achieved in the present embodiment.

  In the following examples, when “odd number”, “even number”, etc. are simply described, it means “odd number”, “even number”, etc. from the left side.

  The buffer 26 has a potential input terminal corresponding to the potential output terminal of the DA converter 25 on a one-to-one basis, and outputs n potential output terminals that output a potential equal to the potential input to each potential input terminal of the buffer 26. Have For example, the i-th potential output terminal from the left of the buffer 26 outputs a potential equal to the potential input to the i-th potential input terminal from the left of the buffer 26. The buffer 26 is, for example, a voltage follower.

The output multiplexer 27 has a potential input end corresponding to the potential output end of the buffer 26 on a one-to-one basis. The output multiplexer 27 has n potential output terminals corresponding to each potential input terminal on a one-to-one basis. Each potential output terminal of the output multiplexer 27 is connected to the _n source lines S _{1 to} Sn included in the liquid crystal display panel 5 on a one-to- _one basis. The output multiplexer 27 outputs the potential input to the i-th potential input terminal from the left from the i-th potential output terminal from the left.

However, a first capacitor 31 and a second capacitor 32 are connected to the output multiplexer 27. The first capacitor 31 is a capacitor for connecting to a source line is set to potentials higher than V _COM, the second capacitor is a capacitor for connecting to a source line is set to potentials lower than V _COM . The capacity of the first capacitor 31 and the capacity of the second capacitor 32 may be determined to be equal, for example.

  The output multiplexer 27 connects the potential output terminal (in other words, the source line connected to the potential output terminal) and the first capacitor 31 or the second capacitor 32 when a predetermined condition is satisfied. . During this time, the output multiplexer 27 stops outputting the potential input to the potential input end corresponding to the potential output end. Further, when the predetermined condition is not satisfied, the output multiplexer 27 outputs the potential input to the potential input terminal from the corresponding potential output terminal. That is, the potential input to the potential input terminal is set to the source line connected to the corresponding potential output terminal.

  The detailed configuration of the output multiplexer 27 will be described later.

  The mode control unit 28 receives POL and STB from the control unit 1 and inputs the POL and STB to other components. Specifically, the mode control unit 28 inputs the STB input from the control unit 1 to the line buffer 22, the latch unit 23, the DA converter 25, and the output multiplexer 27. Further, the mode control unit 28 inputs the POL input from the control unit 1 to the DA converter 25 and the output multiplexer 27.

The V _COM buffer 29 is supplied with the voltage V _COM from the power supply unit 4 and sets the potential of the common electrode 55 (see FIG. 3) to V _COM .

  The control unit 1 inputs the above STH, CLK, STB, and POL to the source driver 2 and controls the source driver 2 in addition to inputting the STV and the row switching signal to the gate driver 3. Further, the control unit 3 compares the image data with the latch unit 23 at the timing when the line buffer 22 has completed holding the image data for the next row before starting the STB. A control signal to be instructed (hereinafter referred to as a comparison instruction signal) is output. Note that raising a control signal such as STB means that the control signal is set to a high level.

Next, an operation in which the latch unit 23 compares the image data for one row read at the immediately preceding STB rising edge with the image data for one row held in the line buffer 22 for each pixel will be described. Here, the average potential of the minimum value of the potential V ₀ ~V ₃ used for the positive polarity display the maximum value (V ₃ in this _example) (V ₀ in this _embodiment) and V _a. That is, V _a = (V ₃ + V ₀ ) / 2. Further, an average potential of the minimum value (V _{7 in} this example) and the maximum value (V _{4 in} this example) among the potentials V _{4 to} V ₇ used for negative display is V _b . That is, V _b = (V ₇ + V ₄ ) / 2. Hereinafter, V _{a is referred} to as a first intermediate potential, and V _{b is referred} to as a second intermediate potential.

  FIG. 9 is an explanatory diagram of image data comparison processing by the latch unit 23. The latch unit 23 holds image data for one row read at the immediately preceding STB rising edge. Of the image data for one row, the image data of each pixel is referred to as data 1, data 2,..., Data n. Further, after the previous STB rising edge, the line buffer 22 sequentially reads the image data of the next row for each pixel. The control unit 2 can determine that the line buffer 22 has read the image data for one row, based on how many times CLK (see FIG. 6) is raised after STH is set to the high level. When the control unit 2 determines that the line buffer 22 has read the image data for one row, the control unit 2 inputs a comparison instruction signal to the latch unit 23 until the next STB rising edge.

  Of the image data for one row that the line buffer 22 has completed reading, the image data of individual pixels is data 1 ′, data 2 ′,..., Data n ′.

  The data 1 and the like held by the latch unit 23 and the data 1 ′ and the like held by the line buffer 22 are pixel values representing pixel gradations, and these data are all represented by the same bit length. ing.

The latch unit 23 includes an EXOR (exclusive or) circuit 35 that performs an exclusive OR operation for each data input terminal (in other words, for each source line in the liquid crystal display panel 5). In the example shown in FIG. 9, the left EXOR circuit is denoted by reference numerals 35 ₁ , 35 ₂ ,..., 35 _n . The i-th EXOR circuit from the left corresponds to the image data of the i-th pixel from the left in the latch unit 23 and the image data of the i-th pixel from the left in the line buffer 22. It can be said that these data all correspond to the i-th source line from the left. Each of the EXOR circuits 35 ₁ , 35 ₂ ,..., 35 _n receives an exclusive logic between MSBs (Most Significant Bits) of image data corresponding to the EXOR circuit itself when a comparison instruction signal is input. Find the sum. Then, the operation result of the exclusive OR is input to the output multiplexer 27 as CSD.

For example, EXOR circuit 35 ₁ shown in FIG. 9, when the comparison instruction signal is input, the MSB of the image data of the leftmost pixel of the data for one row stored in the latch section 23, the line An exclusive OR with the MSB of the image data of the leftmost pixel among the data of one row held in the buffer 22 is obtained, and the calculation result is input to the output multiplexer 27 as CSD. The other EXOR circuits 35 ₂ ,..., 35 _n operate similarly.

CSD obtained as a result of this exclusive or operation is then STB is stood up when changing the potential to be set to the source line, the potential of the source line is the first intermediate potential V _a or the second intermediate potential It represents whether or not to cross _Vb .

For example, during the current frame period, No. 1 The left column is positive drive, the source line S ₁ of the leftmost either a potential of V ₀ ~V ₄ is set. In this case, it is assumed that the value of data 1 shown in FIG. 9 is small and the potential of the source line S ₁ is V ₃ . The value of the data 1 'in the leftmost in the next row is small, the potential of the source line S ₁ is a will be set to V _2. In this case, both the data 1, the MSB of the data 1 'is 0, EXOR circuit 35 _1, and the CSD "0". Here, the potential of the source line is also changed from V ₃ to V _2, it does not cross the first intermediate potential V _a. CSD = 0 represents this. Even when the potential of the source line S ₁ changes from V ₂ to V ₃ , changes from V ₁ to V ₀ , or changes from V ₀ to V ₁ , etc. , the result of the exclusive OR of MSB (CSD) are both 0, indicating that no cross the first intermediate potential _{V a.} The CSD is also 0 when the potential does not change.

Further, it is assumed that the value of the data 1 shown in FIG. 9 is small and the potential of the source line S ₁ is V ₃ . Then, the value of the next data 1 of the leftmost in the row 'is large, the potential of the source line S ₁ is a will be set to V _0. In this case, the MSB of data 1 is 0, and the MSB of data 1 ′ is 1. Thus, EXOR circuit 35 _1, and "1" to CSD. At this time, since the electric potential of the source line is changed from V ₃ to V _0, varies across the first intermediate potential V _a. CSD = 1 represents this. When the potential of the source line S ₁ changes from V ₃ to V ₁ , changes from V ₂ to V ₀ , changes from V ₂ to V ₁ , Alternatively, they and even if such would be the potential to reverse changes as a result (CSD) of the exclusive oR of MSB becomes 1 any, the potential across the first intermediate potential V _a is varied Represents.

Here, the case of positive polarity has been described as an example, but the same applies to the case of negative polarity. That is, if the result of the exclusive OR (CSD) of the MSB is 1, this indicates that the potential of the source line changes across the second intermediate potential _Vb , and if the CSD is 0, This means that the potential does not straddle the second intermediate potential _Vb . Considering the ease of circuit configuration, it is preferable to arrange the EXOR circuit in the latch unit 23, but there is no particular limitation. Corresponding to the same source line, the MSB of the image data is compared with the MSB of the next image to calculate the exclusive OR.

FIG. 10 is an explanatory diagram illustrating a configuration example of the output multiplexer 27. In FIG. 10, the portion connected to the i−1th source line, the ith source line, and the i + 1th source line from the left is illustrated, but the portion connected to another source line is illustrated. The configuration is the same. In FIG. 10, ch (i−1), ch (i), and ch (i + 1) represent the i−1th, ith, and i + 1th from the left, respectively. Further, in the example illustrated in FIG. 10, the (i−1) th and (i + 1) th are odd numbers from the left side, and the i th is the even number from the left side. If an odd number position from the left, by the operation of the aforementioned D-A converter 25, when POL is at a high level, the potentials higher than V _COM output from the potential output terminal, when POL is at a low level, V _A potential lower than _COM is output from the potential output terminal. Further, if an even number from the left, by the operation of the aforementioned D-A converter 25, when POL is at a high level, the potentials lower than V _COM output from the potential output terminal, when POL is at a low level , A potential higher than V _COM is output from the potential output terminal.

The potential output terminals U _i−1 , U _i , U _{i + 1} of the output multiplexer 27 are respectively connected to corresponding source lines (not shown). The output multiplexer 27 has an output unit 45 that outputs the potential input from the buffer 26 for each column.

  The output multiplexer 27 includes a first switch 41 and a second switch 42 for each potential output terminal. The first switch 41 is a switch that turns on or off the connection state between the potential output terminal and the first capacitor 31. The second switch 42 is a switch that turns on or off the connection state between the potential output terminal and the second capacitor 32.

In the first capacitor 31 and second capacitor 32, the potential output terminals of the output multiplexer 27 is the potential of the unconnected side _electrode, kept _{V COM} by _{V COM} buffer 29 (see FIG. 5). The first capacitor 31 is connected to a potential output terminal having positive polarity. As a result, the potential of the other electrode of the first capacitor 31 converges a value near the first intermediate potential V _a. The second capacitor 32 is connected to a potential output terminal having a negative polarity. As a result, the potential of the other electrode of the second capacitor 32 converges and becomes a value near the second intermediate potential _Vb . Note that, from the viewpoint of low power consumption, it is preferable that the potential of the electrode not connected to the potential output terminals of the first capacitor 31 and the second capacitor 32 is the common electrode potential, but it may be a ground potential.

Note that kept _{V COM} by even the common electrode _{V COM} buffer 29 (see FIG. 5). The common electrode and the pixel electrode also form a capacitor. When the first switch 41 is turned on, the potential output terminal and the first capacitor 31 are connected. This means that the pixel electrode that is in conduction with the source electrode connected to the potential output terminal is connected to the first capacitor 31. It means that it is in a connected state. Similarly, when the second switch 42 is turned on, the potential output terminal and the second capacitor 32 are connected. This means that the pixel electrode that is in conduction with the source electrode connected to the potential output terminal That is, the two capacitors 32 are connected.

  The on / off of the first switch 41 and the second switch 42 is determined by the states of STB, POL, and CSD input to the output multiplexer 27. The CSD is generated for each column and input from the latch unit 23 (see FIG. 9). The condition for turning on the first switch 41 and the second switch 42 differs depending on whether the column is an odd-numbered column or an even-numbered column. Further, regarding the first switch 41 and the second switch 42, “ON” means that the potential output terminal is connected to the first capacitor 31 or the second capacitor 32. “Off” means that the connection between the potential output terminal and the first capacitor 31 or the second capacitor 32 is disconnected.

A condition for turning on the first switch 41 in the odd-numbered column will be described. Here, the i-1st first switch 41 from the left will be described as an example. The first switches 41 in the odd-numbered columns are turned on for a certain period when all of the following three conditions are satisfied. The first condition is that a rising edge of STB is detected. The second condition is that POL is at a high level. The third condition is that the CSD corresponding to the column in which the first switch 41 itself is arranged is 1. In this example, the CSD output from the (i−1) -th EXOR circuit from the left is 1. When all three conditions are satisfied, the first switches 41 in the odd-numbered columns are turned on for a certain period after detecting the rising edge of STB. In this example, the (i−1) th first switch 41 from the left connects the potential output terminal U _i−1 and the first capacitor 31.

A condition for turning on the second switch 42 in the odd-numbered column will be described. Similarly to the above, the i-1th case from the left will be described as an example. The second switches 42 in the odd-numbered columns are turned on for a certain period when all of the following three conditions are satisfied. The first condition is that a rising edge of STB is detected. The second condition is that POL is at a low level. The third condition is that the CSD corresponding to the column in which the second switch 42 is disposed is 1. In this example, the CSD output from the (i−1) -th EXOR circuit from the left is 1. When all three conditions are satisfied, the second switches 42 in the odd-numbered columns are turned on for a certain period after detecting the rising edge of STB. In this example, the (i−1) th second switch 42 from the left connects the potential output terminal U _i−1 and the second capacitor 32.

  Here, the i-1st first switch 41 and the second switch 42 from the left have been described as examples, but the same applies to other odd-numbered columns.

Next, a condition for turning on the first switch 41 in the even-numbered column will be described. Here, the i-th first switch 41 from the left will be described as an example. The first switches 41 in the even-numbered columns are turned on for a certain period when all of the following three conditions are satisfied. The first condition is that a rising edge of STB is detected. The second condition is that POL is at a low level. The third condition is that the CSD corresponding to the column in which the first switch 41 itself is arranged is 1. In this example, the CSD output from the i-th EXOR circuit from the left is 1. When all three conditions are satisfied, the first switches 41 in the even-numbered columns are turned on for a certain period after detecting the rising edge of STB. In this example, the i-th first switch 41 from the left connects the potential output terminal U _i and the first capacitor 31.

A condition for turning on the second switch 42 in the even-numbered column will be described. Similar to the above, the i-th case from the left will be described as an example. The second switches 42 in the even-numbered columns are turned on for a certain period when all of the following three conditions are satisfied. The first condition is that a rising edge of STB is detected. The second condition is that POL is at a high level. The third condition is that the CSD corresponding to the column in which the second switch 42 is disposed is 1. In this example, the CSD output from the i-th EXOR circuit from the left is 1. When all three conditions are satisfied, the second switches 42 in the even-numbered columns are turned on for a certain period after detecting the rising edge of STB. In this example, the i-th second switch 42 from the left connects the potential output terminal U _i and the second capacitor 31.

  As can be seen from the above description, the first condition and the third condition for turning on the switch are the first switch 41 and the first condition regardless of whether the column is an odd-numbered column or an even-numbered column. Common to the two switches 42.

  The output unit 45 stops the output of the potential input from the buffer 26 while the first switch 41 or the second switch 42 in the column is on. Then, the output of the potential input from the buffer 26 is started on the condition that the first switch 41 or the second switch 42 is turned on and a certain period elapses and the switch is turned off.

The condition that CSD is 1 is included in the condition that the first switch 41 or the second switch 42 is turned on. Therefore, when the potential of the source line is changed across the first intermediate potential V _a or the second intermediate potential V _b when the selected row is switched, the source line is temporarily connected to the first capacitor 31 or the second capacitor. 32, the potential of the source line is set to V _a or V _b (provided that the first and second conditions are also satisfied). Thereafter, the output unit 45 sets the potential input from the buffer 26 to the source line. As a result, an effect of reducing power consumption can be obtained.

For example, taking the case of positive polarity as an example, when the potential of the source line is increased from V ₃ or V ₂ to V ₁ or V ₀ , first, the potential of the source line is set to V _a using the first capacitor 31. Raise to. At this time, the first capacitor 31 contributes to the potential increase, and the potential input from the buffer 26 is not consumed. Although the positive polarity has been described here as an example, the same applies to the negative polarity.

In addition, since the source line is not necessarily connected to the first capacitor 31 or the second capacitor 32 when the selected row is switched, the power consumption can be further suppressed. For example, in the case of positive polarity, assuming that the source line is connected to the first capacitor 31 even when the potential of the source line is changed from V ₃ to V ₂ , the potential of the source line is is raised from V ₃ to V _a, will be further reduced to V _2, the power is wasted. In the present invention, as a condition for connecting the source line to the first capacitor 31 and the second capacitor 32, it is adopted that CSD is 1, that is, the potential changes across the intermediate potentials V _a and V _b. Therefore, the wasteful power consumption as described above can be suppressed.

Note that the first switch 41 that satisfies the ON condition connects the source line connected to the potential output terminal and the first capacitor 31. At this time, the source lines was lower than the potential in the vicinity the first intermediate potential V _a is the first capacitor 31 is raised to a potential near the middle potential V _a. The first capacitor 31 is discharged to such a source line. However, in the source line connected to the first capacitor 31 is also present source line of potential higher than the potential near the first intermediate potential V _a. Therefore, the first capacitor 31 is not only discharged, but also charged from such a source line. Among the electrodes of the first capacitor 31, the potential of the electrode connected to the source line is It is maintained at a potential close to first intermediate potential V _a.

The same applies to the second capacitor 32. That is, not only discharging but also charging is performed, and the potential of the electrode connected to the source line among the electrodes of the second capacitor 32 is maintained at a potential close to the second intermediate potential _Vb. .

  The above-described conditions for turning on the first switch 41 and the second switch 42 are applied within each frame period, and are not applied when switching the frame period. That is, when the selection of the last row is completed and a new frame period is started to select the first row, the above-described conditions for turning on the switches 41 and 42 are not applied. When a new period is started and the first row is selected, for example, when the STB rises, all the first switches 41 and the second switches 42 are turned off, and each output unit 45 of the output multiplexer 27 The output of the potential input from the buffer 26 may be started from the rising edge.

  Alternatively, on / off of the first switch 41 and the second switch 42 may be set also when the frame period is switched. The conditions for turning on the first switch 41 and the second switch 42 when the frame period is switched will be described later.

  Next, the relationship between STB and CSD output timing will be described with reference to FIG. Since the STB rises at time T1, the latch unit 23 reads image data for one line from the line buffer 22 at this time. In accordance with the operation of the latch unit 23, the level shifter 24, the DA converter 25, the buffer 26, and the output multiplexer 27 operate, and potentials are set for the respective source lines. At this time, the first switch 41 and the second switch 42 that satisfy the above-described conditions are once turned on, but the operation thereof is omitted here.

  After time T1, a potential is set for each source line, and the pixel electrodes in the selected row are set to a potential corresponding to the image data for one line. In addition, STH and CLK are input to the shift register 21, and accordingly, the line buffer 22 reads data for the next one line. It is assumed that this data reading is completed by time T2. At time T2, the latch unit 23 holds the data read from the line buffer 22 at time T1. Therefore, at time T2, each EXOR circuit 35 (see FIG. 9) receives the MSB of each image data held in the latch unit 23 and the MSB of each image data in the next row held in the line buffer 22. And CSD can be calculated. For example, the control unit 1 outputs a comparison instruction signal at time T2, causes each EXOR circuit 35 to calculate the exclusive OR of the MSBs, and calculates CSD.

Each EXOR circuit 35 inputs this CSD to the output multiplexer 27. Then, at time T3 when STB rises after time T1, the first switch 41 and the second switch 42 of the output multiplexer 27 refer to this CSD to determine whether or not the third condition is satisfied. That's fine. By determining whether this manner are filled third condition, the potential of the previous source line from time T3, after the time T3, to vary across the intermediate potential V _a and V _b It will be judged whether or not. At time T3, the first condition is satisfied. Whether or not the second condition is satisfied may be determined with reference to the POL in the frame period.

  As shown in FIG. 12, when POL is at a high level, only the first switch 41 in the odd-numbered column can connect the potential output terminal to the first capacitor 31. At time T3, among the first switches 41 in the odd-numbered columns, only the first switch 41 in the column where the CSD calculated at time T2 is 1, the potential output terminal is set to the first for a certain period from time T3. The capacitor 31 is connected. At time T3, the STB rises, so the first condition is satisfied. Note that the above-mentioned fixed period is, for example, the beginning period of the period in which the STB is at a high level. Then, after the period ends, the output unit 45 sets the potential input from the buffer 26 to the source line.

  Of the odd-numbered columns, the column in which the CSD calculated at time T2 is 0 does not turn on the first switch 41. In this case, after the time T3, the output unit 45 sets the potential input from the buffer 26 to the source line without waiting for the elapse of a certain period during which the switches 41 and 42 are turned on.

  Further, when POL is at a high level (see FIG. 12), only the second switch 42 in the even-numbered column can connect the potential output terminal to the second capacitor 32. At time T3, among the second switches 42 in the even-numbered columns, only the second switch in the column where the CSD calculated at time T2 is 1, the potential output terminal is set to the second capacitor for a certain period from time T3. 32. At time T3, the first condition is satisfied. As described above, the certain period is, for example, a period at the beginning of a period in which the STB is at a high level. After the fixed period, the output unit 45 sets the potential input from the buffer 26 to the source line.

  Of the even-numbered columns, the column in which the CSD calculated at time T2 is 0 does not turn on the second switch 42. In this case, after the time T3, the output unit 45 sets the potential input from the buffer 26 to the source line without waiting for the elapse of a certain period during which the switches 41 and 42 are turned on.

  Here, time T3 has been described as an example, but the same processing is repeated for each rising edge of STB.

  As shown in FIG. 13, when POL is at a low level, only the first switch 41 in the even-numbered column can connect the potential output terminal to the first capacitor 31. At time T3, among the first switches 41 in the even-numbered columns, only the first switch 41 in the column in which the CSD calculated at time T2 is 1 has the potential output terminal set to the first for a certain period from time T3. The capacitor 31 is connected. At time T3, the first condition is satisfied. As described above, the certain period is, for example, a period at the beginning of a period in which the STB is at a high level. After the fixed period, the output unit 45 sets the potential input from the buffer 26 to the source line.

  Of the even-numbered columns, the column in which the CSD calculated at time T2 is 0 does not turn on the first switch 41. In this case, after the time T3, the output unit 45 sets the potential input from the buffer 26 to the source line without waiting for the elapse of a certain period during which the switches 41 and 42 are turned on.

  Further, when POL is at a low level (see FIG. 13), only the second switch 42 in the odd-numbered column can connect the potential output terminal to the second capacitor 32. At time T3, among the second switches in the odd-numbered columns, only the second switch in the column where the CSD calculated at time T2 is 1, the potential output terminal is set to the second capacitor 32 for a certain period from time T3. Connect to. At time T3, the first condition is satisfied. This fixed period is as already described. After the fixed period, the output unit 45 sets the potential input from the buffer 26 to the source line.

  Among the odd-numbered columns, the column in which the CSD calculated at time T2 is 0 does not turn on the second switch 42. In this case, after the time T3, the output unit 45 sets the potential input from the buffer 26 to the source line without waiting for the elapse of a certain period during which the switches 41 and 42 are turned on.

Next, a modification of the first embodiment will be described.
When the frame period is switched, the first switch 41 and the second switch 42 may connect the potential output terminal of the output multiplexer 27 to the first capacitor 31 or the second capacitor 32 when a predetermined condition is satisfied. Hereinafter, this operation will be described.

  The control signal STV is used as a condition for switching on and off the first switch 41 and the second switch 42 when the frame period is switched. Therefore, in this modification, the control unit 1 (see FIG. 1) outputs STV not only to the gate driver 3 but also to the source driver 2. The control unit 1 also generates a control signal (denoted as STVD) obtained by delaying STV by one clock signal and outputs the control signal to the source driver 2. In STVD, rising and falling edges are delayed by one clock signal from STV.

  FIG. 14 is an explanatory diagram illustrating an example of an output timing chart of STV, STVD, and the like. As shown in FIG. 14, the control unit 1 sets the STV to the high level before the rising edge of the first STB in the new frame period, and sets the STV to the low level after the falling edge of the STB. . Further, the control unit 1 sets STVD to the high level before the rising edge of the first STB in the new frame period, and sets the STVD to the low level after the falling edge of the STB.

  Further, the control unit 1 switches the POL level at the same timing as the rising edge of STV, for example. As already described, POL is alternately switched between a high level and a low level every frame period.

  When STB becomes high level, the latch unit 23 reads image data of each pixel for one line from the line buffer 22. However, in the present modification, when the new image data for one line is read, the latch unit 23 relates to the MSB of each pixel among the image data of each pixel for one line that has been held so far. , Leave and keep. That is, when the STB becomes high level, not only the image data of each pixel for one line newly read is held, but also the MSB of the image data of each pixel of the previous line held so far. Hold. For example, at time Tb shown in FIG. 14, the latch unit 23 reads image data for a new line and also holds the MSB of the image data of each pixel held from time Ta. Thus, when the image data of a new row is read, the latch unit 23 also holds the MSB of the image data of each pixel in the previous row.

  In this example, the case where the latch unit 23 holds the MSB of the image data of each pixel in the previous row is described as an example. However, even if other components other than the latch unit 23 hold the image data. Good.

  In this modification, the first switch 41 and the second switch 42 in each column are turned on not only when the above-described conditions are satisfied but also when the following conditions are satisfied. However, since the conditions shown below include “STV being high level” or “STVD being high level”, the following switch operation is performed in a new frame period. This is applied when setting the potential according to the image data of the first row.

  A condition for turning on the first switch 41 in the odd-numbered column will be described. The first switches 41 in the odd-numbered columns are turned on for a certain period when the following conditions are satisfied. That is, “STV is at high level”, “STB rising edge is detected”, “POL is at low level”, and “image data one line before” When the fact that the MSB of the image data of the pixel corresponding to the column in which the switch 41 is disposed is all “1” is satisfied, the first switch 41 in the odd-numbered column detects the rising edge of the STB. It will be on for a certain period. That is, the potential output terminal of the odd column and the first capacitor 31 are connected. Further, this fixed period is referred to as a first period. “The MSB of the image data of the pixel corresponding to the column in which the first switch 41 itself is arranged in the image data of the previous line is 1” means that the image data has a higher gradation than the halftone. Is shown.

  In the present modification, the MSB of the image data of each pixel one line before is also held by the latch unit 23 (or another component), so the output multiplexer 27 can refer to the MSB. Good.

“POL is at the low level” and “MSB of the image data of the pixel corresponding to the column in which the first switch 41 itself is arranged among the image data one line before” is “1”. the fact that is filled, in the previous frame period, POL is at a high level, the source line of the potential of the odd-numbered columns of interest means that higher than V _a. And POL is at a low level in a new frame period, so that source line potential lower than V _COM, by turning on the first switch 41, a source line potential near the V _a by utilizing the first capacitor 31 In this case, the charge accumulated in the capacitor can be used to reduce power consumption. That is, in the potential change illustrated in FIG. 15A, when the source line potential is lowered to around V _a , charges can be accumulated in the capacitor, and the charges can be used to reduce power consumption.

  FIG. 16 is an explanatory diagram showing the first period described above. As shown in FIG. 16, the first period may be provided at the beginning of the period in which the STB is at the high level. Note that the second period after the first period shown in FIG. 16 will be described later.

  A condition for turning on the second switch 42 in the odd-numbered column will be described. The second switches 42 in the odd-numbered columns are turned on during the first period (see FIG. 16) when the following conditions are satisfied. That is, “STV is high level”, “STB rising edge is detected”, “POL is high level”, and “second line of image data one line before” When the fact that the MSB of the image data of the pixel corresponding to the column in which the switch 42 is arranged is all “1” is satisfied, the second switch 42 in the odd-numbered column is turned on during the first period. Become. That is, the potential output terminal of the odd-numbered column and the second capacitor 32 are connected.

“POL is at a high level” and “MSB of the image data of the pixel corresponding to the column in which the second switch 42 is arranged among the image data one line before” is “1”. Satisfaction means that POL was at a low level in the previous frame period, and the potential of the source line in the odd-numbered column of interest was lower than _Vb . And POL is at a high level in a new frame period, so that source line potential higher than V _COM, by turning on the second switch 42, the source line potential near V _b by using the second capacitor 32 The power consumption can be reduced accordingly. For example, in the potential change illustrated in FIG. 15B, power consumption when raising the source line potential to around _Vb can be suppressed.

  A condition for turning on the first switch 41 in the even-numbered column will be described. The first switches 41 in the even-numbered columns are turned on during the first period when the following conditions are satisfied. That is, “STV is high level”, “STB rising edge is detected”, “POL is high level”, and “first line of image data one line before” When the fact that the MSB of the image data of the pixel corresponding to the column in which the switch 41 is disposed is all “1” is satisfied, the first switch 41 in the even-numbered column is on during the first period. become. That is, the even-numbered potential output terminal and the first capacitor 31 are connected.

“POL is at a high level” and “MSB of the image data of the pixel corresponding to the column in which the first switch 41 itself is arranged among the image data one line before” is “1”. that are met in the previous frame period POL is at a low level, the source line of the potential of the even-numbered columns of interest means that higher than V _a. And POL is at a high level in a new frame period, so that source line potential lower than V _COM, by turning on the first switch 41, a source line potential near the V _a by utilizing the first capacitor 31 (See FIG. 15A). That is, charges can be accumulated in the capacitor, and the charges can be used to reduce power consumption.

  A condition for turning on the second switch 42 in the even-numbered column will be described. The second switches 42 in the even-numbered columns are turned on during the first period when the following conditions are satisfied. That is, “STV is high level”, “rising edge of STB is detected”, “POL is low level”, and “second line of image data one line before” When the fact that the MSB of the image data of the pixel corresponding to the column in which the switch 42 is disposed is all “1” is satisfied, the second switch 42 in the even-numbered column is turned on during the first period. Become. That is, the potential output terminal of the even column and the second capacitor 32 are connected.

“POL is at the low level” and “MSB of the image data of the pixel corresponding to the column in which the second switch 42 is arranged among the image data one line before” is “1”. Satisfaction means that POL was at a high level in the previous frame period, and the potential of the source line in the even-numbered column of interest was lower than _Vb . And POL is at a low level in a new frame period, so that source line potential higher than V _COM, by turning on the second switch 42, the source line potential near V _b by using the second capacitor 32 The power consumption can be reduced by that amount (see FIG. 15B).

  Furthermore, in the second period after the first period (see FIG. 16), the first switch 41 and the second switch 42 in each column are also turned on when the following conditions are satisfied. The second period is a certain period after the first period in the period in which the STB is first at the high level after the switching of the frame period.

  A condition for turning on the first switches 41 in the odd-numbered columns in the second period will be described. The first switches 41 in the odd-numbered columns are turned on during the second period when the following conditions are satisfied. That is, “STVD is high level”, “STB is high level”, “POL is high level”, “STB is high level, If the image data for one line read by the latch unit 23 satisfies all “the MSB of the image data of the pixel in the column in which the first switch 41 is disposed is 1”, the odd-numbered column The first switch 41 is turned on during the second period. That is, the potential output terminal of the odd column and the first capacitor 31 are connected.

The column in which the first switch 41 itself is arranged in the image data for one line newly read by the latch unit 23 when the POL is at the high level and the STB is at the high level. The fact that the MSB of the image data of the pixel of “1” is satisfied means that the potential of the source line of the odd-numbered column of interest in the first row of the newly started current frame period is means that the higher than V _a. The potential of the source line means that was less than V _COM in the previous frame period. Therefore, in the second period, by turning on the first switch 41, by utilizing the first capacitor 31, the potentials lower than V _COM can be increased to around V _a, correspondingly, reducing power consumption be able to. That is, in the potential change illustrated in FIG. 17A, power consumption when raising the source line potential to around V _a can be suppressed.

  A condition for turning on the second switches 42 in the odd-numbered columns in the second period will be described. The second switches 42 in the odd-numbered columns are turned on during the second period when the following conditions are satisfied. That is, “STVD is high level”, “STB is high level”, “POL is low level”, “STB is high level, If the image data for one line read by the latch unit 23 satisfies all “the MSB of the image data of the pixel in the column in which the second switch 42 is disposed is 1”, the odd-numbered column The second switch 42 is turned on during the second period. That is, the odd-numbered potential output terminal and the second capacitor 32 are connected.

The column in which the second switch 42 is arranged in the image data for one line newly read by the latch unit 23 due to “POL being low level” and “STB being high level” The fact that the MSB of the image data of the pixel of “1” is satisfied means that the potential of the source line of the odd-numbered column of interest in the first row of the newly started current frame period is It means lower than _Vb . Further, in the frame period of potential before its source line means that were potentials higher than V _COM. Therefore, in the second period, by turning on the second switch 42, charge by using the second capacitor 32, the potentials higher than V _COM can be lowered to around V _b, accumulated in this time capacitor Can be used to reduce power consumption. That is, in the potential change illustrated in FIG. 17B, when the source line potential is lowered to around _Vb , charges can be accumulated in the capacitor, and the charges can be used to reduce power consumption.

  A condition for turning on the first switches 41 in the even-numbered columns in the second period will be described. The first switches 41 in the even-numbered columns are turned on during the second period when the following conditions are satisfied. That is, “STVD is high level”, “STB is high level”, “POL is low level”, “STB is high level, If the image data for one line read by the latch unit 23 satisfies all “the MSB of the image data of the pixel of the column in which the first switch 41 itself is arranged is 1”, the even-numbered column The first switch 41 is turned on during the second period. That is, the potential output terminals of the even-numbered columns and the first capacitors 31 are connected.

The column in which the first switch 41 itself is arranged in the image data for one line newly read by the latch unit 23 when the POL is at the low level and the STB is at the high level. The fact that the MSB of the image data of the pixel of “1” is satisfied means that the potential of the source line of the even-numbered column of interest in the first row of the newly started current frame period is means that the higher than V _a. The potential of the source line means that was less than V _COM in the previous frame period. Therefore, in the second period, by turning on the first switch 41, by utilizing the first capacitor 31, the potentials lower than V _COM can be increased to around V _a, correspondingly, reducing power consumption (See FIG. 17 (a)).

  A condition for turning on the second switches 42 in the even-numbered columns in the second period will be described. The second switches 42 in the even-numbered columns are turned on during the second period when the following conditions are satisfied. That is, “STVD is high level”, “STB is high level”, “POL is high level”, “STB is high level, If the image data for one line read by the latch unit 23 satisfies all “the MSB of the image data of the pixel of the column in which the second switch 42 is disposed is 1”, the even-numbered column The second switch 42 is turned on during the second period. That is, the even-numbered potential output terminal and the second capacitor 32 are connected.

The column in which the second switch 42 is disposed in the image data for one line newly read by the latch unit 23 due to the fact that POL is at a high level and STB is at a high level. The fact that the MSB of the image data of the pixel of “1” is satisfied means that the potential of the source line of the odd-numbered column of interest in the first row of the newly started current frame period is It means lower than _Vb . Further, in the frame period of potential before its source line means that were potentials higher than V _COM. Therefore, in the second period, by turning on the second switch 42, by using the second capacitor _32, it is possible to lower the potentials higher than _{V COM} to around _{V b} (FIG. 17 (b) see) . At that time, charges can be accumulated in the capacitor, and the charges can be used to reduce power consumption.

  In addition, the condition that “STVD is at a high level” is included in the condition for turning on the first switch 41 and the second switch 42 in the second period. The condition that “is at a high level” may be used.

  Further, the output unit 45 (see FIG. 10) may start outputting the potential input from the buffer 26 after the second period ends, for example, at the time of switching the frame period. In addition, the output unit 45 outputs the potential input from the buffer 26, for example, from the second period if both the first switch 41 and the second switch 42 in the column are turned off in the second period. You may start.

As described above, even when the frame period is switched, the power consumption can be reduced by turning on the first switch 41 and the second switch 42 when a predetermined condition is satisfied. For example, when a predetermined condition is satisfied, the first switch 41 and the second switch 42 are turned on in the first period, so that _a source line whose potential is higher than Va in the previous frame period is connected to the first capacitor 31. Connected to accumulate charge in the first capacitor 31, or connected a source line having a potential lower than _Vb to the second capacitor 32 in the previous frame period, and using the second capacitor 32 to increase the potential to _Vb It is possible to reduce power consumption at the time of making it. At this time, since the already established conditions as described, for example, such as to raise the V _COM or a potential from the potential of the source lines to reduce the V ₄ to V _b, to suppress wasteful power consumption Can do.

Further, when a predetermined condition is satisfied, so to turn on the first switch 41 and second switch 42 in the second period, the new frame period, the potential of the source line to be a potential above V _a, utilizing the first capacitor 31 can be increased to V _a, it is possible to suppress the power consumption during this period. In addition, by connecting a source line whose potential should be equal to or lower than _Vb to the second capacitor 32, charges can be accumulated in the second capacitor 32, and this charge can be used to reduce power consumption. At this time, since the already established conditions as described, for example, that decreases from raising the electric potential of less than V _COM to V _a to V _3, it is possible to suppress wasteful power consumption.

In the above example, the case of column inversion is shown. The control unit 1 can realize dot inversion by switching the POL level between a high level and a low level for each selection period. In this case, the potential of each source line in each selection period, switches to a potential lower than the high potential and V _COM from V _COM. At this time, in order to reduce the power consumption, it is only necessary to determine the ON state of the first switch 41 and the second switch 42 in each column by applying the conditions at the time of frame period switching described in the above-described modification. . Specifically, when the selected row is switched, the first switch 41 and the second switch 42 are turned on in the first period and the second period (see FIG. 16) after the STB rising edge under the same conditions as in the above-described modification. You just have to decide. Further, the control unit 1 may perform control for each STB so that signals corresponding to STV and STVD shown in FIG. However, the STV for the gate driver 3 is set to the high level only when the frame period is switched.

Next, another modification of the first embodiment will be described.
In the first embodiment, each EXOR circuit 35 compares the image data MSB stored in the latch unit 23 with the image data MSB stored in the line buffer 22. A double D flip-flop may be provided for each bit of image data of each pixel in the circuit (for example, the latch unit 23), and an exclusive OR operation between outputs of the D flip-flop may be performed. FIG. 18 shows an example of a configuration in which the exclusive OR operation of the MSB of image data is performed by providing double D flip-flops. FIG. 18 shows a double D flip-flop corresponding to each bit from LSB (Least Significant Bit: least significant bit) to MSB of image data for one pixel in one line. The input terminal D of each D flip-flop 36 in the first stage takes in the value of 1 bit of the corresponding pixel in the line buffer 22. The output terminal Q of each D flip-flop 36 at the first stage is connected to the input terminal D of each D flip-flop 36 at the second stage. Then, STB is input to CK of each D flip-flop 36, 37. As a result, when STB becomes high level, image data of a certain line (K) is held in each D flip-flop 36 in the first stage. Next, when STB becomes high level, the image data of the line K is held in the second-stage D flip-flop 37, and the image data of the next line is held in the first-stage D flip-flop 36. An EXOR circuit 35 is provided for each pixel of data. The EXOR circuit 35 outputs the output Q of the D flip-flop 36 corresponding to the first MSB and the D flip-flop corresponding to the second MSB. An exclusive OR with the output Q of 37 is obtained, and the operation result is output to the output multiplexer 27 as CSD.

  Thus, the configuration for calculating the exclusive OR of the MSB of the pixel data of a certain row and the MSB of the pixel data of the next row may be various configurations other than the configuration shown in FIG. . In addition, regarding other points, the configurations and operations described in the first embodiment and the modifications thereof are examples, and the present invention may be realized by other configurations and operations. For example, in the above-described modified example, the conditions for turning on the first switch and the second switch in the even-numbered column and the odd-numbered column from the left side are set, respectively. Conditions for turning on the second switch and conditions for turning on the first switch and the second switch in the even-numbered column from the right side may be determined.

[Embodiment 2]
As in the first embodiment, the liquid crystal display device according to the second embodiment includes a control unit 1, a source driver, a gate driver 3, a liquid crystal display panel, and a power supply unit 4 (see FIG. 1). ). However, since the configuration of the source driver is different from that of the first embodiment, hereinafter, the source driver is represented by reference numeral 2a. The source driver 2a and the gate driver 3 receive voltage supply from the power supply unit 4 (see FIG. 1).

  Further, the configuration of the liquid crystal display panel is different from that of the first embodiment. In the second embodiment, the liquid crystal display panel having the configuration illustrated in FIG. 19 is used, while maintaining the polarity of each potential output terminal of the output multiplexer 27 to be positive or negative within one frame period. Realize inversion. Hereinafter, the liquid crystal display panel according to the second embodiment will be described with reference to FIG. Hereinafter, the liquid crystal display panel according to the second embodiment is denoted by reference numeral 5a.

  The liquid crystal display panel 5a sandwiches liquid crystal between a plurality of pixel electrodes 50 arranged in a matrix and a common electrode (not shown in FIG. 19). This point is the same as that of the liquid crystal display panel 5 in the first embodiment.

However, the liquid crystal display panel 5a includes one source line on the left side of each column of pixel electrodes and also includes one source line on the right side of the rightmost pixel column. In other words, the liquid crystal display panel 5a includes n + 1 source lines S _{1 to} S _{n + 1} which is one more than the number n of pixel electrode columns (see FIG. 19). With such a configuration, one column of pixel electrodes is arranged between adjacent source lines.

  In each pixel electrode 50 in the odd-numbered row, the TFT 51 is provided on the left side of the pixel electrode 50, and connects the pixel electrode 50 and the source line on the left side thereof. On the other hand, in each pixel electrode 50 in the even-numbered row, the TFT 51 is provided on the right side of the pixel electrode 50, and connects the pixel electrode 50 and the source line on the right side thereof (see FIG. 19). FIG. 3 illustrates the case where the pixel electrode 50 is connected to the left source line. However, when the pixel electrode 50 is connected to the right source line, for example, the TFT 51 is disposed on the right side of the pixel electrode 50. , TFT, source line, and gate line may be connected. However, here, for convenience, the case where the odd-numbered TFTs are provided on the left side of the pixel electrode and the even-numbered TFTs are provided on the right side of the pixel electrode is illustrated. As long as the pixel electrodes in the even-numbered rows are connected to the source line on the right side, the TFT position itself may be arbitrary.

FIG. 20 is an explanatory diagram illustrating a configuration example of the source driver 2a according to the second embodiment. Configuration examples similar to those in the first embodiment are denoted by the same reference numerals as those in FIG. 5, and detailed description thereof is omitted. The source driver 2a includes a shift register 21, a line buffer 22a, a latch unit 23a, a level shifter 24a, a DA converter 25a, a buffer 26a, an output multiplexer 27a, a mode control unit 28, and a V _COM buffer 29. And a first capacitor 31 and a second capacitor 32. In FIG. 20, the numbers such as “1”, “2”, “3”, “n”, “n + 1”, etc. described at the input and output terminals of the line buffer 22a and the like are the numbers of the terminals from the left side. It represents whether there is. Also in the second embodiment, when “odd number”, “even number”, etc. are simply described, it means “odd number”, “even number”, etc. from the left side.

  The shift register 21 is the same as that in the first embodiment.

  The line buffer 22 a includes signal input terminals corresponding to the signal output terminals of the shift register 21. Each time a data reading instruction signal is input to the signal input terminal, one pixel of image data is read out of one line of image data, and the image data is held. This point is the same as in the first embodiment.

However, the line buffer 22a includes a source line _{S 1 ~S n +} 1 and the same number of signal output terminal. Then, the image data of n pixels for one line is read into the latch unit 23a from the first to nth data output terminals from the left, or the second to n + 1th data output from the left Whether to read from the end into the latch unit 23a is switched according to a control signal (denoted as a terminal control signal) from the control unit 22a. The terminal control signal is a control signal output from the control unit 1 in the second embodiment in addition to the various control signals described in the first embodiment.

  For example, the line buffer 22a includes n + 1 storage areas (not shown) corresponding to n + 1 data output terminals. When the terminal control signal is at a high level, the line buffer 22a stores n image data for one row in a storage area corresponding to the first to nth data output terminals from the left. Deploy. In this case, nothing is stored in the storage area corresponding to the (n + 1) th data output terminal from the left. When the terminal control signal is at a low level, the line buffer 22a stores n image data for one row in a storage area corresponding to the data output terminals from the second to the (n + 1) th from the left. Arrange as follows. In this case, nothing is stored in the storage area corresponding to the leftmost data output end. The other points are the same as those of the line buffer 22 in the first embodiment.

  Further, when the line buffer 22a reads the image data of the odd-numbered rows of the liquid crystal display panel 5a, the control unit 1 sets the terminal control signal to the high level. On the other hand, when the line buffer 22a reads the even-numbered image data of the liquid crystal display panel 5a, the terminal control signal is set to the low level. Accordingly, the odd-numbered image data is read into the latch unit 23a from the first to nth data output terminals from the left of the line buffer 22a. The even-numbered image data is read into the latch unit 23a from the second to n + 1th data output terminals from the left of the line buffer 22a. The controller 1 may switch the level of the terminal control signal alternately between the high level and the low level in the same cycle as the line buffer 22a reads one row of data.

  The latch unit 23a has n + 1 data input terminals and n + 1 potential output terminals, which are the same number as the source lines of the liquid crystal display panel 5a. Then, image data for one line is read from the line buffer 22a at each rising edge of the STB. However, as described above, the data storage mode of the line buffer 22a is a mode of storing data for one line in the storage area corresponding to the first to nth data output terminals from the left (first storage mode and the first storage mode). And a mode (second storage mode) in which data for one line is stored in a storage area corresponding to the second to n + 1th data output terminals from the left.

  In the case of the first storage mode described above, the latch unit 23a has one line via the first to nth data output terminals from the left of the line buffer 22a and the data input terminals corresponding to those of the latch part 23a. N image data per minute is read. The latch unit 23a outputs each potential corresponding to each image data for one line from the first to nth potential output terminals from the left. In this case, since data is not read from the n + 1th data output terminal from the left in the line buffer 22a, the latch unit 23a does not output a potential from the n + 1th potential output terminal from the left.

  In the case of the second storage mode, the latch unit 23a is connected to the second to n + 1th data output terminals from the left of the line buffer 22a and the data input terminals corresponding to those of the latch part 23a. Read n image data for one line. The latch unit 23a outputs each potential corresponding to each image data for one line from the second to n + 1th data output terminals from the left. In this case, since data is not read from the leftmost data output end in the line buffer 22a, the latch unit 23a does not output a potential from the leftmost potential output end.

  Further, the control unit 1 compares the line buffer 22a before the start of the STB and at the timing when the line buffer 22a has completed holding the image data for the next row in the first storage mode or the second storage mode. The instruction signal is output to the latch unit 23a. When the comparison instruction signal is input, the latch unit 23 performs an exclusive OR operation between the MSB of the image data read at the immediately preceding STB rising edge and the image data MSB held in the line buffer 22.

FIG. 21 is an explanatory diagram of image data comparison processing by the latch unit 23a according to the second embodiment. In the present embodiment, the line buffer 22a stores the data for one line by alternately switching the first storage mode and the second storage mode for each row. Therefore, columns and corresponding to the source line S ₁ of the leftmost, the columns corresponding left-to (n + 1) th source line S _{n + 1,} 2 pieces of data do not align in the same column on. Therefore, in the second embodiment, the latch portion 22a is, for example, (n-1) of the EXOR circuit ₃₅ 2 to 35 _n corresponding second from the source line _{S 2} from the left to the n-th source line _{S n} Prepare. Each of the EXOR circuits 35 _{2 to} 35 _n calculates the exclusive OR of the MSBs of the image data corresponding to the same source line as the EXOR circuit itself, and outputs the calculation result to the output multiplexer 27 as CSD.

In the second embodiment, the line buffer 22a switches the first storage mode and the second storage mode described above for each row, and the data of each pixel stored in the line buffer 22a is stored in the same column. The data is read into the latch unit 23a via the output terminal. Therefore, in the second embodiment, the EXOR circuit performs an exclusive OR operation of MSBs not on image data of pixels at the same position in image data for one line but on image data shifted by one pixel. . For example, in the example shown in FIG. 21, EXOR circuit 35 _2, as image data corresponding to the same source line, and the MSB of the data 2 (image data of the second pixel from the left in one line), data 1 '( An exclusive OR operation with the MSB of the image data of the leftmost pixel in one line is performed.

The EXOR circuit 35 _i corresponding to the i-th source line from the left will be described. The EXOR circuit 35 _i corresponds to the MSB of image data read from the i-th data input end from the left as the image data corresponding to the i-th source line, and the i-th data output end from the left in the line buffer 22a. The exclusive OR with the MSB of the image data stored in the storage area is calculated. When the latch unit 23a reads image data for one line from the first to nth data input ends, the “image data read from the i-th data input end from the left” is the left in one line. This is image data of the i-th pixel, and “image data stored in the storage area corresponding to the i-th data output terminal from the left in the line buffer 22a” is the i−1-th pixel from the left in one line. Image data. When the latch unit 23a reads image data from the second to (n + 1) th data input ends, “image data read from the i-th data input end from the left” is i− from the left in one line. The image data of the first pixel, “image data stored in the storage area corresponding to the i-th data output terminal from the left in the line buffer 22a” is the image data of the i-th pixel from the left in the first line. It is.

  The arrangement of the EXOR circuit shown in FIG. 21 is an example, and is not limited to the example shown in FIG. For example, the source driver 2a may be configured such that an EXOR circuit is arranged in the leftmost or n + 1th column from the left, and the exclusive OR operation is also performed in these columns.

In the present embodiment, EXOR circuits 35 _{2 to} 35 _n shown in FIG. 21 are provided, and outputs from the CSD of the column corresponding to the second source line from the left to the CSD of the column corresponding to the nth source line. This will be described as an example.

  The level shifter 24a includes n + 1 potential input terminals and potential output terminals, which are the same number as the source lines of the liquid crystal display panel 5a. Other points are the same as those of the level shifter 24 in the first embodiment. Note that since the number of pixels for one line is n, the potential output terminal of the latch unit 23a is n + 1. Therefore, as described above, the leftmost potential of the latch unit 23a or the (n + 1) th potential from the left side. In some cases, no potential is output from the output terminal. In this case, the level shifter 24a does not output a potential from the potential output terminal corresponding to the potential input terminal to which the potential is not input from the latch unit 23a.

  The DA converter 25a includes n + 1 potential input terminals and potential output terminals, which are the same number as the source lines of the liquid crystal display panel 5a. The other points are the same as those of the DA converter 25 of the first embodiment. Further, similarly to the first embodiment, the control unit 1 switches the control signal POL alternately between a high level and a low level for each frame period.

D-A converter 25a, when POL is at a high level, the output potential of the odd-numbered each potential output terminal from the left and potentials higher than V _COM, the output potential of the even-numbered each potential output terminals from the left V _The potential is lower than _COM . Conversely, when the POL is at a low level, D-A converter 25, the output potential of the odd-numbered each potential output terminal from the left and potentials lower than V _COM, the even-numbered each potential output terminals from the left output the potential is higher than _{V COM} potential.

  The buffer 26a includes n + 1 potential input terminals and potential output terminals, which are the same number as the source lines of the liquid crystal display panel 5a. The other points are the same as those of the buffer 26 of the first embodiment. However, the buffer 26a does not output a potential from a potential output end corresponding to a potential input end to which no potential is input.

The output multiplexer 27a has n + 1 potential input terminals corresponding one-to-one with the potential output terminals of the buffer 26a. The output multiplexer 27a has n + 1 potential output terminals corresponding to the potential input terminals on a one-to-one basis. Each potential output terminal of the output multiplexer 27a is connected to the _{n + 1} source lines S _{1 to} S _{n + 1} included in the liquid crystal display panel 5a in a one-to-one relationship. The output multiplexer 27a outputs the potential input to the i-th potential input terminal from the left from the i-th potential output terminal from the left.

FIG. 22 is an explanatory diagram illustrating an example of the output multiplexer 27a according to the second embodiment. The same elements as those shown in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted. In this example, the EXOR circuit is not provided in the leftmost column and the (n + 1) th column from the left (see FIG. 21). The output in the multiplexer 27a, the leftmost potential output terminals _{U 1} and, n + 1-numbered potential output terminals _{U n + 1} from the left is connected to the output section 45, also, other potential output terminals _U 2 ~U _n Unlike the first switch 41, the first switch 41 and the second switch 42 are not provided. The leftmost output unit 45 and the (n + 1) th output unit 45 from the left output the potential output from the corresponding potential output terminal of the buffer 26a from the potential output terminals U ₁ and U _{n + 1} , respectively.

In addition, each potential output terminals _U 2 ~U _n from second from left to n-th, a first switch 41, second switch 42 is provided. The first switch 41 and the second switch 42 are the same switches as in the first embodiment.

As described above, except that n + 1 potential input terminals and potential output terminals are provided, and that the first switch 41 and the second switch 42 are not provided at the potential output terminals U ₁ and U _{n + 1.} With respect to the output multiplexer 27a, the output multiplexer 27a is the same as the output multiplexer 27 in the first embodiment.

The first capacitor 31 connected to the respective potential output terminals U ₂ ~U _n by the first switch 41 is the same as the first embodiment. Similarly, the second capacitor 32 connected to the respective potential output terminals U ₂ ~U _n by the second switch 42 is also similar to the first embodiment.

  In addition, the condition for turning on the first switch 41 and the second switch 42 at the time of switching the selected row within the frame period is the same as in the first embodiment.

  That is, the first switches 41 in the odd-numbered columns are “detected STB rising edge”, “POL is at high level”, and “columns where the first switches 41 themselves are arranged”. When “corresponding CSD is 1” is satisfied, the signal is turned on for a certain period after the rising edge of STB is detected.

  In addition, the second switch 42 in the odd-numbered column “is that the rising edge of STB has been detected”, “POL is at the low level”, and “the second switch 42 itself is disposed in the column. When “corresponding CSD is 1” is satisfied, the signal is turned on for a certain period after the rising edge of STB is detected.

  In addition, the first switches 41 in the even-numbered columns are “detected STB rising edge”, “POL is at low level”, and “columns where the first switches 41 themselves are arranged”. When “corresponding CSD is 1” is satisfied, the signal is turned on for a certain period after the rising edge of STB is detected.

  In addition, the second switches 42 in the even-numbered columns are “detected STB rising edge”, “POL is at high level”, and “columns in which the second switches 42 themselves are arranged”. When “corresponding CSD is 1” is satisfied, the signal is turned on for a certain period after the rising edge of STB is detected.

The output unit 45 connected to the potential output terminal U ₂ ~U _n is, while the first switch 41 or the second switch 42 of the column is turned on, the output of the potential input from the buffer 26a Stop. The output unit 45 starts outputting the potential input from the buffer 26a on the condition that the first switch 41 or the second switch 42 is turned on and a certain period of time has passed and the switch is turned off. To do. This point is the same as in the first embodiment.

  Moreover, the control part 1 in 2nd Embodiment outputs a terminal control signal in addition to each control signal in 1st Embodiment. Other points are the same as those in the first embodiment.

The relationship between the STB and the CSD output timing is also the same as in the first embodiment (see FIG. 11). However, in the second embodiment, the line buffer 22a completes storing the image data for one line in the first storage mode or the second storage mode before the rising edge of the STB. Thereafter, the control unit 1 may output a comparison instruction signal. In response to the comparison instruction signal, each of the EXOR circuits 35 _{2 to} 35 _n calculates an exclusive OR of the MSBs of the image data corresponding to the same source line, and outputs the calculation result to the output multiplexer 27a as CSD. Then, when the first switch 41 or the second switch 42 of the output multiplexer 27a detects the rising edge of the STB after the CSD is input, whether or not to turn it on with reference to the CSD and the POL at that time. Determine.

Next, the operation when the potential corresponding to the image data on the odd-numbered rows of the liquid crystal display panel 5a is set to the source line will be described. In this case, the line buffer 22a stores the odd-numbered row of image data in the first storage mode. Further, in this state, each of the EXOR circuits 35 _{2 to} 35 _n has the MSB of the image data in the latch unit 23a corresponding to the EXOR circuit itself and the image data MSB stored in the same column in the line buffer 22a. An exclusive OR is calculated and CSD is calculated.

When STB becomes high level, the latch unit 23a reads image data for one line from the line buffer 22a via the first to nth terminals from the left, and the output multiplexer 27a outputs the potential output terminal U _1. by ~U _n, it sets the potential of the source line _S 1 to S _n. Odd rows of pixel electrodes, because it is connected to the source line S ₁ to S _n on the left side, respectively, by the output multiplexer 27a to set the potential of the source line S ₁ to S _n, the potential of each pixel electrode Is set.

In addition, when this time POL is at a high level, D-A converter 25a outputs the potential higher than V _COM from the odd-numbered potential output terminals from the left, than V _COM from the even-numbered potential output terminals from the left Since a low potential is output, the potentials of S ₁ , S ₃ ,... _Are higher than V _COM , and S ₂ , S _{4 ,.}

  Further, as described in the first embodiment, when POL is at a high level, only the first switch 41 in the odd-numbered column can connect the potential output terminal to the first capacitor 31. Of the first switches 41 in the odd-numbered columns, only the first switch 41 in the column in which the CSD calculated at the rising edge of the STB is 1 is set to the potential for a certain period after the rising edge of the STB. The output terminal is connected to the first capacitor 31. After that, the output unit 45 (see FIG. 22) sets the potential input from the buffer 26 to the source line. However, the leftmost output unit 45 sets the potential from the buffer 26 to the source line after the STB rises.

  When POL is at a high level, only the second switch 42 in the even column can connect the potential output terminal to the second capacitor 32. Of the second switches 42 in the even-numbered columns, only the second switch 42 in the column in which the CSD calculated at the rising edge of the STB is 1 is set to the potential for a certain period after the rising edge of the STB. The output terminal is connected to the second capacitor 32. After that, the output unit 45 sets the potential input from the buffer 26 to the source line.

  As a result, when POL is at the high level, the polarities of the odd-numbered rows of the liquid crystal display panel 5a are +, −, +,... From the left as shown in FIG.

Further, when POL is at a low level, D-A converter 25a outputs the potential lower than V _COM from the odd-numbered potential output terminals from the left higher than V _COM from the even-numbered potential output terminals from the left potential , The potentials of S ₁ , S ₃ ,... _Are lower than V _COM , and S ₂ , S ₄ ,... _Are higher than V _COM .

  When POL is at a low level, only the first switch 41 in the even-numbered column can connect the potential output terminal to the first capacitor 31. Of the first switches 41 in the even-numbered columns, only the first switch 41 in the column where the CSD calculated at the rising edge of the STB is 1 has a potential for a certain period after the rising edge of the STB. The output terminal is connected to the first capacitor 31. After that, the output unit 45 (see FIG. 22) sets the potential input from the buffer 26 to the source line. However, as in the case where POL is at a high level, the leftmost output unit 45 sets the potential from the buffer 26 to the source line from when STB rises.

  Further, when POL is at a low level, only the second switch 42 in the odd-numbered column can connect the potential output terminal to the second capacitor 32. Of the second switches 42 in the odd-numbered columns, only the second switch 42 in the column where the CSD calculated at the rising edge of the STB is 1 is set to the potential for a certain period after the rising edge of the STB. The output terminal is connected to the second capacitor 32. After that, the output unit 45 sets the potential input from the buffer 26 to the source line.

  As a result, when POL is at the low level, the polarities of the odd-numbered rows of the liquid crystal display panel 5a are −, +, −,.

Next, the operation when the potential corresponding to the image data of the even-numbered row of the liquid crystal display panel 5a is set to the source line will be described. In this case, the line buffer 22a stores the odd-numbered row of image data in the second storage mode. Further, in this state, each of the EXOR circuits 35 _{2 to} 35 _n has the MSB of the image data in the latch unit 23a corresponding to the EXOR circuit itself and the image data MSB stored in the same column in the line buffer 22a. An exclusive OR is calculated and CSD is calculated.

When STB becomes high level, the latch unit 23a reads image data for one line from the line buffer 22a via the second to n + 1th terminals from the left, and the output multiplexer 27a outputs the potential output terminal U _2. by ~U _{n + 1,} it sets the potential of the source line _S 2 _{~S n + 1.} Even rows of the pixel electrodes, since they are respectively connected to the source line S ₂ ~S n + ₁ on the right, by the output multiplexer 27a to set the potential of the source line S ₂ ~S n + _1, the potential of each pixel electrode Is set.

In addition, when this time POL is at a high level, D-A converter 25a outputs the potential higher than V _COM from the odd-numbered potential output terminals from the left, than V _COM from the even-numbered potential output terminals from the left Since a low potential is output, S ₂ , S ₄ ,... _Are lower than V _COM and S ₃ , S ₅ ,... _Are higher than V _COM .

  Of the first switches 41 in the odd-numbered columns, only the first switch 41 in the column in which the CSD calculated at the rising edge of the STB is 1 is set for a certain period after the rising edge of the STB. The potential output terminal is connected to the first capacitor 31. After that, the output unit 45 (see FIG. 22) sets the potential input from the buffer 26 to the source line. In addition, among the second switches 42 in the even-numbered columns, only the second switch 42 in the column in which the CSD calculated at the rising edge of the STB is 1 is set for a certain period after the rising edge of the STB. The potential output terminal is connected to the second capacitor 32. After that, the output unit 45 sets the potential input from the buffer 26 to the source line.

  However, the (n + 1) th output unit 45 (see FIG. 22) from the left sets the potential from the buffer 26 to the source line after the STB rises.

  As a result, when POL is at a high level, the polarities of the even-numbered rows of the liquid crystal display panel 5a are −, +, −,... From the left as shown in FIG.

Further, when POL is at a low level, D-A converter 25a outputs the potential lower than V _COM from the odd-numbered potential output terminals from the left higher than V _COM from the even-numbered potential output terminals from the left potential , S ₂ , S ₄ ,... _Are higher than V _COM , and S ₃ , S ₅ ,... _Are lower than V _COM .

  Then, among the first switches 41 in the even-numbered columns, only the first switch 41 in the column in which the CSD calculated at the rising edge of the STB is 1 is set for a certain period after the rising edge of the STB. The potential output terminal is connected to the first capacitor 31. After that, the output unit 45 (see FIG. 22) sets the potential input from the buffer 26 to the source line. Of the second switches 42 in the odd-numbered columns, only the second switch 42 in the column in which the CSD calculated at the rising edge of the STB is 1 is set for a certain period after the rising edge of the STB. The potential output terminal is connected to the second capacitor 32. After that, the output unit 45 sets the potential input from the buffer 26 to the source line.

  However, the (n + 1) th output unit 45 (see FIG. 22) from the left sets the potential from the buffer 26 to the source line after the STB rises. This is the same as when POL is at a high level.

  As a result, when POL is at a low level, the polarities of the even-numbered rows of the liquid crystal display panel 5a are +, −, +, −,.

  Therefore, in the second embodiment, dot inversion can be realized in the liquid crystal display panel 5a regardless of whether POL is at a high level or a low level.

  In addition, when the selected row is switched within the frame period, the first switch 41 and the second switch 42 are turned on under the same conditions as in the first embodiment. Therefore, as in the first embodiment, Power consumption can be reduced.

  Also in the second embodiment, a modification similar to that of the first embodiment may be applied. That is, the first switch 41 and the second switch 42 may be turned on when a predetermined condition is satisfied not only when the selected row is switched within the frame period but also when the frame period is switched.

  In this case, as described in the modification of the first embodiment, the control unit 1 (see FIG. 1) outputs STV not only to the gate driver 3 but also to the source driver 2a. Further, the control unit 1 outputs STVD (see FIG. 14) to the source driver 2a.

In this modification, the output multiplexer 27a may comprise a first switch 41 and second switch 42 to the potential output terminal _U 2 ~U _n. The first switch 41 and the second switch 42 of the potential output terminals U ₁ and U _{n + 1} at the left and right ends are turned on only when the frame period is switched, and are always turned off when the selected row is switched within the frame period. It is.

Similarly to the modification of the first embodiment, the latch unit 23a reads the image data of each pixel for one line from the line buffer 22a when the STB becomes high level. Then, among the image data of each pixel for one line that has been held so far, the MSB of each pixel is retained and retained. However, the latch unit 23a includes n + 1 storage areas corresponding to the source lines on a one-to-one basis as storage areas of the MSB, and the storage areas corresponding to the source lines to which the potential based on the image data is set The MSB of the image data is stored. That is, before the rise of STB, if that held the image data corresponding to the source line _S 1 to S _n, upon the rise of STB, corresponding MSB of the image data to the source line _S 1 to S _n Stored in the storage area. In this case, the MSB is not stored in the storage area corresponding to the source line _{Sn + 1} . Further, when the image data corresponding to the source lines S _{2 to} Sn _{+ 1} is held before the rising edge of the STB, the MSB of each image data corresponds to the source lines S _{2 to} Sn _{+ 1} at the rising edge of the STB. Stored in the storage area. In this case, the storage area corresponding to the source line S ₁ MSB is not stored.

If the MSB in the storage area corresponding to the source line S _{n + 1} is not stored, "one of the preceding line of the image data, MSB of the image data of the pixel corresponding to the source line S _{n + 1} is 1" condition that is not met. Similarly, if the MSB in the storage area corresponding to the source line S ₁ is not stored, the condition that "one of the preceding line of the image data, MSB of the image data of the pixel corresponding to the source line S ₁ is a 1" Not satisfied.

  In this example, the case where the latch unit 23a holds the MSB of the image data of each pixel in the previous row is described as an example. However, even if other components other than the latch unit 23a hold the image data. Good.

  Conditions for turning on the first switch 41 and the second switch 42 in each column in the first period (that is, the first period, see FIG. 16) of the period in which the STB is first at the high level after the switching of the frame period. These are the same as the conditions described in the modification of the first embodiment. Hereinafter, conditions for turning on the switches in the odd-numbered columns and the even-numbered columns from the left will be described.

  The first switches 41 in the odd-numbered columns are “STV is high level”, “STB rising edge is detected”, “POL is low level”, and “1 line” If all of the previous image data satisfy that “the MSB of the image data of the pixel corresponding to the column in which the first switch 41 itself is arranged is 1”, it is turned on during the first period. That is, the potential output terminal of the odd column and the first capacitor 31 are connected.

  The second switches 42 in the odd-numbered columns are “STV is high level”, “STB rising edge is detected”, “POL is high level”, and “1 line” If all of the previous image data satisfying that the MSB of the image data of the pixel corresponding to the column in which the second switch 42 is disposed is “1”, it is turned on during the first period. That is, the potential output terminal of the odd-numbered column and the second capacitor 32 are connected.

  The first switches 41 in the even-numbered columns are “STV is high level”, “STB rising edge detected”, “POL is high level”, and “1 line”. If all of the previous image data satisfy that “the MSB of the image data of the pixel corresponding to the column in which the first switch 41 itself is arranged is 1”, it is turned on during the first period. That is, the even-numbered potential output terminal and the first capacitor 31 are connected.

  The second switches 42 in the even-numbered columns are “STV is high level”, “STB rising edge is detected”, “POL is low level”, and “1 line”. If all of the previous image data satisfying that the MSB of the image data of the pixel corresponding to the column in which the second switch 42 is disposed is “1”, it is turned on during the first period. That is, the potential output terminal of the even column and the second capacitor 32 are connected.

  Further, in the second period after the first period (see FIG. 16), the condition described in the modification of the first embodiment is also the condition for turning on the first switch 41 and the second switch 42 in each column. It is the same. Hereinafter, conditions for turning on the switches in the odd-numbered columns and the even-numbered columns from the left will be described.

  The first switches 41 in the odd-numbered columns are “STVD is high level”, “STB is high level”, “POL is high level”, “STB is high level”. The fact that the MSB of the image data of the pixel in the column where the first switch 41 itself is arranged is 1 in the image data for one line newly read by the latch unit 23a due to the high level is satisfied. If so, it is on during the second period. That is, the potential output terminal of the odd column and the first capacitor 31 are connected.

  The second switches 42 in the odd-numbered columns are “STVD is high level”, “STB is high level”, “POL is low level”, “STB is The fact that the MSB of the image data of the pixel in the column where the second switch 42 is arranged is 1 in the image data for one line newly read by the latch unit 23a due to the high level is satisfied. If so, it is on during the second period. That is, the odd-numbered potential output terminal and the second capacitor 32 are connected.

  The first switches 41 in the even-numbered columns are “STVD is high level”, “STB is high level”, “POL is low level”, “STB is The fact that the MSB of the image data of the pixel in the column where the first switch 41 itself is arranged is 1 in the image data for one line newly read by the latch unit 23 due to the high level is satisfied. If so, it is on during the second period. That is, the potential output terminals of the even-numbered columns and the first capacitors 31 are connected.

  The second switches 42 in the even-numbered columns are “STVD is high level”, “STB is high level”, “POL is high level”, “STB is high level”. The fact that the MSB of the image data of the pixel in the column in which the second switch 42 is arranged is 1 in the image data for one line newly read by the latch unit 23 due to the high level is satisfied. If so, it is on during the second period. That is, the even-numbered potential output terminal and the second capacitor 32 are connected.

  In addition, the condition that “STVD is at a high level” is included in the condition for turning on the first switch 41 and the second switch 42 in the second period. The condition that “is at a high level” may be used.

  The output unit 45 (see FIG. 22) may start outputting the potential input from the buffer 26a after the second period, for example, at the time of switching the frame period. In addition, if both the first switch 41 and the second switch 42 in the column are turned off in the second period, the output unit 45 outputs the potential input from the buffer 26a, for example, from the second period. You may start.

  As described above, when the frame period is switched, the first switch 41 and the second switch 42 are turned on under the same conditions as in the modification of the first embodiment, so that the modification of the first embodiment is performed. As in the example, power consumption can be reduced.

  The operations and configurations described in the second embodiment and its modifications are examples, and the present invention may be realized by other configurations and operations. For example, the present invention may be applied to an active matrix liquid crystal display device of an IPS (In Plain Switching) system.

  The present invention is preferably applied to an active matrix liquid crystal display device.

DESCRIPTION OF SYMBOLS 1 Control part 2, 2a Source driver 3 Gate driver 5, 5a Liquid crystal display panel 21 Shift register 22, 22a Line buffer 23, 23a Latch part 24, 24a Level shifter 25, 25a DA converter 26, 26a Buffer 27, 27a Output multiplexer 31 First Capacitor 32 Second Capacitor 35 _{1 to} 35 _n EXOR Circuit

Claims (7)

An active matrix type liquid crystal comprising a common electrode, pixel electrodes arranged in a matrix, source lines arranged along the column direction of the pixel electrodes, and gate lines arranged along the row direction of the pixel electrodes A display panel;
A gate driver for line-sequentially driving the gate lines;
A source driver that sets the potential of the source line according to image data;
Control means for controlling the gate driver and the source driver,
The control means defines a selection period defining pulse signal that defines the selection period of the pixel electrodes in each row for the source driver, and a polarity that defines whether the potential set for each source line is higher or lower than the common electrode potential. Output a control signal, and alternately switch the level of the polarity control signal between the first level and the second level every frame period,
The source driver is
Data holding means for holding one line of image data defining a potential to be set for each source line for each selection period;
Next-row data holding means for holding image data for the next row of image data for one row held by the data holding means;
The same number of potential output terminals as the source lines are provided, and potentials corresponding to the image data held by the data holding means are output from the potential output terminals corresponding to the individual source lines, and potentials are output from the potential output terminals. When the polarity control signal is at the first level, a potential higher than the common electrode potential is output from the odd-numbered potential output terminal from the left, and from the even-numbered potential output terminal from the left. When a potential lower than the common electrode potential is output and the polarity control signal is at the second level, an odd numbered potential output terminal from the left outputs a potential lower than the common electrode potential, and an even numbered number from the left A potential output means for outputting a potential higher than the common electrode potential from a potential output end;
A potential setting unit having an output unit that outputs a potential equal to the potential output from the potential output terminal of the potential output unit to the source line for each source line;
A first capacitor in which one electrode is set to a specific potential;
A second capacitor in which one electrode is set to a specific potential;
Corresponding to the same source line, and comprising an exclusive OR operation means for calculating an exclusive OR by comparing the value of the most significant bit of the image data and the value of the most significant bit of the next image data,
The potential setting means turns on or off the connection between the source line and the electrode of the first capacitor that is not set to the specific potential at the connection end of the output unit and the source line. A first switch; and a second switch that turns on or off the connection between the source line and the electrode of the second capacitor that is not set to the specific potential;
The data holding means fetches and holds image data for one row from the next row data holding means at the rising edge of the selection period defining pulse signal,
The first switch corresponding to the odd-numbered source line from the left detects the rising of the selection period defining pulse signal, the polarity control signal is at the first level, and the exclusive corresponding to the source line On the condition that the calculation result of the logical OR is all 1, the connection between the source line and the electrode of the first capacitor is turned on,
The second switch corresponding to the odd-numbered source line from the left detects the rising of the selection period defining pulse signal, the polarity control signal is at the second level, and the exclusive corresponding to the source line On the condition that the calculation result of the logical OR is all 1, the connection between the source line and the electrode of the second capacitor is turned on,
The first switch corresponding to the even-numbered source line from the left detects that the selection period defining pulse signal has risen, the polarity control signal is at the second level, and the exclusive corresponding to the source line On the condition that the calculation result of the logical OR is all 1, the connection between the source line and the electrode of the first capacitor is turned on,
The second switch corresponding to the even-numbered source line from the left detects the rising edge of the selection period defining pulse signal, the polarity control signal is at the first level, and the exclusive corresponding to the source line On the condition that the calculation result of the logical OR is all 1, the connection between the source line and the electrode of the second capacitor is turned on,
The output unit corresponding to the source line is characterized in that, when the source line is connected to the first capacitor or the second capacitor, the potential is set to the source line after the connection is turned off. Liquid crystal display device. The image data for calculating the exclusive OR is the image data held in the data holding means, and the next image data for calculating the exclusive OR is held in the next row data holding means. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is image data. The first switch corresponding to the odd-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, the polarity control signal is at the second level, And a new frame on condition that the image data corresponding to the source line held by the data holding means before the rising edge of the selection period defining pulse signal is all higher than halftone. During the first period, which is the predetermined period at the beginning of the period in which the selection period defining pulse signal first rises after the start of the period, the source line and the electrode of the first capacitor are set to the specific potential. Turn on the connection with the other electrode,
The second switch corresponding to the odd-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, and the polarity control signal is at the first level. And that the image data corresponding to the source line held by the data holding means before the rising of the selection period defining pulse signal is all satisfied that the gradation is higher than the halftone. During the first period, the connection between the source line and the electrode of the second capacitor that is not set to the specific potential is turned on,
The first switch corresponding to the even-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, and the polarity control signal is at the first level. And that the image data corresponding to the source line held by the data holding means before the rising of the selection period defining pulse signal is all satisfied that the gradation is higher than the halftone. During the first period, the connection between the source line and the electrode of the first capacitor is turned on,
The second switch corresponding to the even-numbered source line from the left first detects the rising edge of the selection period defining pulse signal after the start of a new frame period, and the polarity control signal is at the second level. And that the image data corresponding to the source line held by the data holding means before the rising of the selection period defining pulse signal is all satisfied that the gradation is higher than the halftone. The liquid crystal display device according to claim 1, wherein the connection between the source line and the electrode of the second capacitor is turned on during the first period. The first switch corresponding to the odd-numbered source line from the left indicates that the selection period defining pulse signal first rises after the start of a new frame period, the polarity control signal is at the first level, and On condition that all the image data corresponding to the source line among the image data for one row taken in by the data holding means by the rising edge of the selection period defining pulse signal are satisfied to be higher in gradation than the halftone. During the second period, which is a predetermined period after the first period, the connection between the source line and the electrode of the first capacitor that is not set to the specific potential is turned on,
The second switch corresponding to the odd-numbered source line from the left is that the selection period defining pulse signal first rises after the start of a new frame period, the polarity control signal is at the second level, And the condition that all the image data corresponding to the source line among the image data for one row taken in by the data holding means by the rising edge of the selection period defining pulse signal is higher than the halftone is satisfied. In the second period, the connection between the source line and the electrode of the second capacitor that is not set to the specific potential is turned on,
The first switch corresponding to the even-numbered source line from the left is that the selection period defining pulse signal first rises after the start of a new frame period, the polarity control signal is at the second level, And the condition that all the image data corresponding to the source line among the image data for one row taken in by the data holding means by the rising edge of the selection period defining pulse signal is higher than the halftone is satisfied. In addition, during the second period, the connection between the source line and the electrode of the first capacitor is turned on,
The second switch corresponding to the even-numbered source line from the left is that the selection period defining pulse signal first rises after the start of a new frame period, the polarity control signal is at the first level, And the condition that all the image data corresponding to the source line among the image data for one row taken in by the data holding means by the rising edge of the selection period defining pulse signal is higher than the halftone is satisfied. The liquid crystal display device according to claim 3, wherein the connection between the source line and the electrode of the second capacitor is turned on during the second period.   The liquid crystal display device according to claim 1, wherein the specific potential is a common electrode potential. The liquid crystal display panel includes a source line on a predetermined side of each column of pixel electrodes,
The liquid crystal display device according to claim 1, wherein each pixel electrode is connected to a source line existing on the predetermined side. The liquid crystal display panel includes source lines provided on the left side of each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes,
The pixel electrodes in the odd-numbered rows are connected to the source lines on the predetermined side among the source lines existing on both sides of the pixel electrodes, and the pixel electrodes in the even-numbered rows are connected to the source lines existing on both sides of the pixel electrodes. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is connected to a source line opposite to the predetermined side.

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