JP2012109561A - Organic thin-film transistor having source and drain electrodes with laminate structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an organic thin-film transistor with a bottom gate and bottom contact structure, which has excellent flexibility, durability and element characteristics, and whose area is easily increased.SOLUTION: An organic thin-film transistor with a bottom gate and bottom contact structure has source and drain electrodes including a first conductive layer and a second conductive layer. The first conductive layer includes one or more kinds of materials selected from a group of tungsten oxide, silver oxide, copper oxide, zinc oxide, silver salt, silver and copper. The second conductive layer includes one or more kinds of materials selected from a group of Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, and an alloy containing any of these metals.

Description

  The present invention relates to an organic thin film transistor, and more particularly to an organic thin film transistor having a bottom gate / bottom contact structure.

  Currently, organic semiconductors, oxide semiconductors, microcrystalline silicon semiconductors, solution-applicable low-temperature polysilicon semiconductors, and the like are being actively studied as materials for next-generation thin film active devices. Among them, an organic semiconductor has a high mechanical strength against bending and the like, and can be formed into a layer by a coating method at a low temperature, which is superior to other semiconductor materials in manufacturing an element using a flexible substrate.

  FIG. 17 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / bottom contact structure using an organic semiconductor. In this organic thin film transistor, a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, and a channel portion on the gate insulating layer 3 are formed. A source electrode 7 and a drain electrode 7, an organic semiconductor layer 8 formed on the source electrode 7 and the drain electrode 7, and an overcoat 10 covering the entire element are provided. In this structure, the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged on the same plane, which is also called a coplanar type.

  FIG. 18 is a cross-sectional view showing a layer structure of an organic thin film transistor having a bottom gate / top contact structure using an organic semiconductor. The organic thin film transistor includes a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer 3 formed on the gate electrode 2, an organic semiconductor layer 8 formed on the gate insulating layer 3, A source electrode 7 and a drain electrode 7 formed on the organic semiconductor layer 8 with a channel portion interposed therebetween, and an overcoat 10 covering the entire element are provided. In this structure, the source / drain electrodes and the channel forming portion of the organic semiconductor layer are arranged in different planes, and is also called a staggered type. In addition, as a stagger type structure using an organic semiconductor, a top gate / bottom contact type structure in which the arrangement of layers is upside down from the structure of FIG. 18 is also used.

  In the staggered device, carriers flow from the source electrode through the bulk of the organic semiconductor, then through the interface between the gate insulating layer where the channel formation portion exists and the organic semiconductor, and then flow through the bulk of the organic semiconductor to the drain. To the electrode. Therefore, when the short channel is used, a high resistance value of the organic semiconductor bulk becomes a factor for remarkably reducing the transistor characteristics. On the other hand, the coplanar structure has an advantage that the resistance of the organic semiconductor bulk becomes 0, and the coplanar structure is widely used for fine elements.

  In the coplanar structure, the contact area between the source / drain electrodes and the channel formation part of the organic semiconductor is small compared to the staggered structure, and the contact resistance between them is a critical factor that determines the characteristics. As a technique for solving the problem of contact resistance, a metal layer having a single layer of metal material having excellent adhesion to an organic insulating material is formed on the surface of the gate insulating layer, and an ohmic contact with the organic semiconductor is formed on the lateral portion thereof. An element in which a layer of a material is formed to form a source / drain electrode is known (Patent Document 1). However, the metal material layer is formed by a lift-off method, and there is a problem that the photolithography process and the total number of masks increase.

  Further, an element (Patent Document 2) in which an inorganic barrier layer is formed on an organic insulating film and source / drain electrodes are formed on the inorganic barrier layer, an inorganic insulating layer is stacked on the organic insulating film, and the inorganic insulating layer An element having a source / drain electrode formed thereon (Patent Document 3) is known. However, an inorganic layer inferior in bending stress is formed on the entire surface of the element, and these elements are inferior in flexibility and durability.

JP 2006-147613 A International Publication No. 2007/099689 Japanese Unexamined Patent Publication No. 2006-013480

  An object of the present invention is to provide an organic thin film transistor having a bottom gate / bottom contact structure which is excellent in flexibility and durability and which can be easily increased in area.

That is, the present invention includes a gate electrode, a gate insulating layer that covers the gate electrode and includes an organic insulating material, and a source electrode and a drain electrode on the gate insulating layer, A bottom gate / bottom contact having an organic semiconductor layer covering a region sandwiched between the source electrode and the drain electrode on the gate insulating layer and covering at least a part of the source electrode and the drain electrode An organic thin film transistor having a structure,
The source electrode and the drain electrode have a stacked structure including a first conductive layer stacked on the gate insulating layer and a second conductive layer stacked on the first conductive layer,
The first conductive layer includes one or more materials selected from the group consisting of tungsten oxide, silver oxide, copper oxide, zinc oxide, silver salt, silver and copper,
The second conductive layer includes Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, and Provided is an organic thin film transistor comprising at least one material selected from the group consisting of alloys containing any of these metals.

  In one certain form, the said 1st conductive layer contains 1 or more types of materials chosen from tungsten oxide and silver oxide.

In one certain form, the said 1st conductive layer is tungsten oxide.

  In one certain form, the valence of tungsten of the tungsten oxide is pentavalent or a combination of pentavalent and hexavalent.

  In one certain form, the said 2nd conductive layer consists of an alloy of gold | metal | money, silver, copper, or silver, copper, and palladium.

  In one certain form, the said 1st conductive layer consists only of tungsten oxide, and a 2nd conductive layer consists only of gold, silver, copper, or the alloy of silver, copper, and palladium.

In one certain form, the said source electrode and drain electrode further have the 3rd conductive layer which coat | covers the said 2 conductive layer,
The third conductive layer is made of Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, a compound of these metals, an oxide of these metals or It is formed from a nitride, an alloy containing any of these metals, Si, B, Ge, a compound of these semiconductors, an alloy containing any of these semiconductors, or an oxide semiconductor.

  The organic thin film transistor of the bottom gate / bottom contact structure of the present invention is excellent in flexibility and durability because the flexibility of the organic insulating material is maintained, and the device characteristics are excellent because the gate insulating layer surface is not damaged, In addition, it can be manufactured by a method that can easily increase the area.

It is sectional drawing which shows the structure of the organic thin-film transistor which is the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the organic thin-film transistor which is the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the structure of the laminated body formed in the manufacture process of the organic thin-film transistor of FIG. It is sectional drawing which shows the layer structure of the organic thin-film transistor of a bottom gate and a bottom contact structure. It is sectional drawing which shows the layer structure of the organic thin-film transistor of a bottom gate top contact structure.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a sectional view showing the structure of an organic thin film transistor according to the first embodiment of the present invention. This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and comprises a first conductive layer 4 and a second conductive layer 5 on the gate insulating layer 3. A source electrode and a drain electrode 7 are provided, an organic semiconductor layer 8 is provided between the source and drain electrodes, and a protective layer 10 covering the organic semiconductor layer 8 is provided.

  When the organic thin film transistor is a flexible element that can be bent, materials used for the substrate 1 include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene naphthalate (PEN), and aromatic polyether. Examples thereof include resins such as sulfone (PES) and liquid crystal polymer (LCP), metal foils such as stainless steel, and thinned glass that can be bent by etching. When the organic thin film transistor is an element that cannot be bent, examples of the material used for the substrate 1 include glass and metal.

  As a material of the gate electrode 2, a highly conductive metal and its alloy are preferably used. More preferred are alloys, oxides and nitrides of refractory metals having high resistance to electro-stress migration. In addition, in order to adjust the work function of the metal surface, the gate electrode may have a laminated structure or a surface modification treatment as necessary. In the present invention, the refractory metal refers to a metal having a melting point of 1000 ° C. or higher.

  The gate electrode 2 is formed on the substrate 1 by a commonly used method such as a photolithography method or a printing method.

  Between the substrate 1 and the gate electrode 2, a protective layer may be provided between the substrate 1 and the gate electrode 2 as necessary in order to prevent deterioration of the gate electrode due to the material contained in the substrate 1.

  As the organic insulating material contained in the gate insulating layer 3, a resin having no fluorine atom, such as PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide, polyvinyl alcohol, polyester, polyvinyl chloride, polyvinyl phenol, cyanoethyl pullulan, Examples thereof include fluorine resins such as “Cytop” (registered trademark) manufactured by Asahi Glass Co., Ltd. and “TEFLON” (registered trademark) manufactured by Dupont. Moreover, you may use the copolymer which has a repeating unit contained in these resin, the composition containing this resin or this copolymer. The copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes a polymer compound having no polarization such as polystyrene.

  The gate insulating layer 3 is laminated on the gate electrode 2 by, for example, a method of applying and drying a solution containing an organic insulating material and a solvent. Examples of the solution coating method include spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, and printing.

  When the gate insulating layer 3 is laminated, patterning such as forming a contact hole in the gate insulating layer 3 may be performed as necessary. The organic insulating material is preferably crosslinked and cured by light or heat, and when the patterning is performed, it is more preferable that the organic insulating material has photosensitivity. As the organic insulating material, a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more is preferable. In addition to curing by crosslinking, the organic insulating material may be dried to form a film to ensure a high withstand voltage.

  From the viewpoint of the characteristics of the organic thin film transistor, it is preferable that the organic insulating material is inactive with respect to the solvent used for manufacturing the organic thin film transistor and is insoluble.

  Next, the source electrode and the drain electrode will be described. In this specification, both are collectively referred to as source / drain electrodes. The source / drain electrode 7 is formed through the following steps, for example.

Forming a first conductive layer 4 made of a conductive material on the gate insulating layer 3 by using one method selected from the group consisting of a coating method, an electroless plating method or an atomic layer deposition method;
Forming a second conductive layer 5 by further forming a conductive layer made of a conductive material on the first conductive layer 4 and then patterning the conductive layer into a predetermined shape;
Removing a portion of the first conductive layer 4 not covered with the second conductive layer 5 to form a source electrode and a drain electrode composed of the first conductive layer 4 and the second conductive layer 5;

  The source / drain electrode 7 has a laminated structure composed of the first conductive layer 4 and the second conductive layer 5. By making the source / drain electrodes 7 have a laminated structure, each layer can have a different function. For example, as a function of the first conductive layer 4, a function as an adhesion layer having an effect of improving the adhesion between the gate insulating layer 3 and the source / drain electrodes 7, and metal atoms of the second conductive layer 5 diffuse into the gate insulating layer 3. It is possible to provide a function as a barrier layer that prevents the occurrence of a failure, or to provide a function of a charge injection layer to the organic semiconductor layer in either the first conductive layer 4 or the second conductive layer 5. .

  When the first conductive layer 4 is formed on the organic insulating layer (that is, laminated as a continuous layer), it is preferable to use a coating method, an electroless plating method or an atomic layer deposition method, and a coating method is used. Is more preferable. By using these methods, process damage to the organic insulating material contained in the gate insulating layer 3 is reduced.

  In order to form the first conductive layer 4 by a coating method, the material needs to be ink. Furthermore, in order to obtain the effect of the present invention, it is preferable to use an inorganic conductive layer in which unnecessary portions can be easily removed from the ink state in a subsequent process. Tungsten oxide, silver oxide, copper oxide, silver salt, silver and copper can be converted from an ink state to an inorganic conductive layer by firing at a relatively low temperature, and can be applied to a resin substrate such as a flexible substrate. Among these, tungsten oxide can be made into a sol-gel solution and a film can be easily obtained at about 150 to 200 ° C. by the sol-gel method, and silver oxide can be reduced by immersing it in an ethanol solution and performing ultrasonic treatment after film formation. It is known that the reaction occurs, and further, it is known that it is reduced to silver by performing a heat treatment at less than 200 ° C. using a highly reducing alcohol (for example, triethylene glycol) as a solvent. Yes. Further, the best material is tungsten oxide, and the etching selectivity can be obtained relatively easily with respect to the metal material used in the second conductive layer 5.

  The process damage referred to in this specification means that an operation or process for manufacturing an organic thin film transistor damages its constituent members. For example, when a metal or the like is directly deposited on the gate insulating layer by physical vapor deposition (PVD), the organic insulating material contained in the gate insulating layer is damaged by the energy of the metal vapor. In particular, when the sputtering method included in the PVD method is used, damage is significant.

  In particular, the first conductive layer 4 is preferably formed by applying a solution containing a conductive material and a solvent onto the gate insulating layer 3 and drying it as shown in FIG.

  The first conductive layer 4 includes, for example, polymetalloxane that can be formed from metal alkoxide by a sol-gel method. Examples of the metal alkoxide include titanium, aluminum, tungsten, niobium, zirconium, vanadium, and tantalum.

  A preferred metal alkoxide is tungsten alkoxide. The tungsten oxide layer is easily etched with an alkaline solution that is an orthogonal solvent (orthogonal solvent) with respect to the gate insulating layer 3 and the second conductive layer 5, and the first conductive layer 4 that has become unnecessary is formed on the surface of the gate insulating layer 3. Can be easily removed.

Examples of tungsten alkoxide include tungsten (V) methoxide, tungsten (V) ethoxide, tungsten (V) isopropoxide, tungsten (V) butoxide, and the like. In addition, the valence of tungsten in tungsten oxide obtained from these tungsten alkoxides is pentavalent. Tungsten oxide obtained from tungsten alkoxide has the advantage that the etching time can be shortened because it dissolves very well in an alkaline solution. Furthermore, if the etching time is too short, the solubility can be changed by changing the valence of tungsten in tungsten oxide by applying ozone UV or O ₂ plasma, etc., so it is easy to increase the etching time. It is. Furthermore, since the valence can be increased to 6 with only a simple ozone UV treatment for the coating method, the WO ₃ layer can be easily obtained by the coating method without using a reactive sputtering method or the like. In addition, since the firing temperature can be as low as 150 ° C., it can be applied to a flexible substrate or the like. The tungsten valence in the tungsten oxide of the first conductive layer 4 obtained in this manner is hexavalent tungsten oxide in the vicinity of the end of the second conductive layer 5 where the influence of UV / O ₃ due to ozone UV treatment is strong. There are many pentavalent components under the electrode where there is much WO _{3 and} there is almost no influence of UV / O ₃ . Therefore, the first conductive layer 4 of tungsten oxide finally obtained is a combination of pentavalent and hexavalent.

  When the first conductive layer 4 is formed by the sol-gel method, the solvent of the sol-gel solution used dissolves or disperses the metal alkoxide used and exhibits volatility at room temperature. Further, an orthogonal solvent (orthogonal solvent) that does not cause damage such as dissolving or swelling the lower gate insulating layer 3 is preferable. Examples of such a solvent include propylene glycol monomethyl ether acetate (hereinafter sometimes referred to as “PGMEA”) and aromatic compounds having a fluorine atom. In addition, when the gate insulating layer 3 has a fluororesin, it is necessary to uniformly form a smooth film on the surface having a surface free energy of 30 mN / m or less. An aromatic compound (for example, 2,3,4,5,6-pentafluorotoluene (also known as perfluorotoluene)).

  The sol-gel solution may contain a metal alkoxide stabilizer in order to improve the uniformity and surface smoothness of the formed layer. The metal alkoxide stabilizer comprises, for example, an α-hydroxyketone compound, an α-hydroxyketone derivative, an ethanolamine compound, an α-diketone compound, an α-diketone compound derivative, an α-hydroxycarboxylic acid compound, and a β-diketone compound. It is preferably at least one compound selected from the group.

  In addition, examples of the material included in the first conductive layer 4 include metals, metal compounds, alloys containing metals, semiconductors, semiconductor compounds, and alloys containing semiconductors. The metal compound includes silver salts such as the above metal oxides, oxide semiconductors, and silver chloride.

Examples of the metal include Ti, Ta, Cu, Mo, W, Au, and Ag. Examples of the metal compound include TiN, TaN, TiO ₂ , WO ₃ , MoO ₃ , AgCl, Ag ₂ O, and CuO. Examples of the metal-containing alloy include MoW, TiW, and MoCr. Examples of the semiconductor include Si, Ge, and Ga. Examples of the semiconductor compound include SiC, GaN, and GaAs. Examples of the alloy containing a semiconductor include WSi, MoSi, TiSi and the like. Examples of the oxide semiconductor include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc composite oxide (IGZO), zinc oxide (ZnO), zinc tin oxide (ZTO), CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, etc. are mentioned.

  Among them, Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Ag, Au, Pt, Ir, Co, Fe, V, Zr, a compound of these metals, an alloy containing any of these metals, Si, B, Ge, a compound of these semiconductors, and an alloy containing any of these semiconductors are preferable, silver oxide, copper oxide, zinc oxide, silver salt, silver, and copper are more preferable, and silver oxide is more preferable.

  For example, the first conductive layer 4 contains an oxide or nitride of a metal selected from the group consisting of Ti, Al, W, Nb, Zr, V, and Ta.

The material contained in the first conductive layer 4 is more preferably refractory metal fine particles, oxides and nitrides, and even more preferably metal fine particles, oxides and nitrides having a melting point of 1000 ° C. or higher.
Here, the metal fine particles refer to metals having a particle diameter of 1 nm to 1000 nm. Nanoparticles having an average particle diameter of 3 to 100 nm are preferable, and nanoparticles of 3 to 30 nm are more preferable.

The solution containing the conductive material and the solvent for forming the first conductive layer 4 is, for example, ITO, IZO, IGZO, tungsten oxide (W _x O _y ), titanium oxide other than the metal alkoxide shown above. Product (Ti _x O _y ), titanium niobium oxide (Ti _x Nb _y O _z ), silver oxide, copper oxide, zinc oxide, silver, copper nanoparticle dispersion solution or silver salt (wherein the subscript x , Y and z are numbers greater than 0). Alternatively, the solution is an electroless plating solution containing metal ions of these conductive materials.

  The first conductive layer 4 uses a dispersion liquid or a sol-gel liquid containing a conductive material and a solvent, and spin coating, dip coating, blade coating, capillary coating, slit coating, spray coating, printing, etc. It is preferable to form a film by this coating method.

  Alternatively, the first conductive layer 4 is formed by using an electroless plating solution containing metal ions of the conductive material, spin coating method, dip coating method, blade coating method, capillary coating method, slit coating method, spray coating method, By applying a plating catalyst or a plating catalyst precursor on the entire surface of the gate insulating layer by a printing method, and immersing the plating catalyst or the plating catalyst precursor in the electroless plating solution together with the gate insulating layer or the like to deposit metal or the like. It may be formed.

Furthermore, the first conductive layer 4 and the second conductive layer 5 may be formed of metals. For example, copper is formed as the first conductive layer 4 by a coating method, and gold is formed thereon by sputtering. Thereafter, gold is patterned in the same shape as the source and drain electrodes, and then copper is patterned using gold as a mask. If gold and copper, silver, or a silver alloy, etching selectivity can be obtained.
In one preferred embodiment, the first conductive layer 4 of the source electrode and the first conductive layer 4 of the drain electrode are made of copper, and the second conductive layer 5 of the source electrode and the second conductive layer 5 of the drain electrode are made of gold.

  The method for laminating the first conductive layer 4 may be a method other than those described above, and is not particularly limited as long as it does not damage the gate insulating film. Further, they may be grown and stacked by an atomic layer deposition (ALD) method or the like. When laminating by the ALD method, materials included in the first conductive layer 4 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these And alloys containing any of these metals, oxides of these metals, or nitrides of these metals. In addition, as a metal compound precursor used in the ALD method, titanium nitride (TiN) precursor bis (diethylamido) bis (dimethylamido) titanium (IV) (Bis (diethylamido) bis (dimethylamido) titanium (IV)) ), Tris (ethylmethylamido) (tert-butylimido) tantalum, which is a precursor of tantalum nitride (TaN), and the like.

  Further, the Fermi level of the first conductive layer 4 is preferably equal to or deeper than the energy of the highest occupied orbit (HOMO) of the organic semiconductor layer 7.

  The layer thickness of the first conductive layer 4 is preferably 3 to 500 nm, and more preferably 3 to 50 nm.

  As shown in FIG. 3, the second conductive layer 5 is preferably formed by forming a conductive material on the first conductive layer 4 and then patterning it.

  The second conductive layer 5 can be formed by sputtering from an Ag alloy, for example. Even when the sputtering method is used, since the first conductive layer 4 before patterning functions as a barrier layer, process damage to the organic insulating material is reduced. Examples of the Ag alloy include an Ag—Pd—Cu alloy (APC).

  The material contained in the second conductive layer 5 may be a highly conductive metal, an alloy thereof, an oxide thereof, or a nitride thereof, in addition to the Ag alloy. Among them, Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, or any of these metals Alloys containing are preferred. These metals are very common metals and have high conductivity, and it is possible to obtain a sputtering target relatively easily. Furthermore, even when these metal alloys, oxides, and nitrides are formed, these materials can be easily obtained by reactive sputtering. In the first embodiment of the organic thin film transistor, it is preferable that the material has low electrocost migration resistance at low cost. Examples of the material include Cu.

  The material included in the second conductive layer 5 is specifically illustrated along with a non-limiting combination with the material included in the first conductive layer 4. The conductivity of the second conductive layer 5 is preferably higher than the conductivity of the first conductive layer 4. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the first electrode layer 4, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.

[Table 1]

  The second conductive layer 5 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method in addition to the sputtering method.

  From the viewpoint of forming a fine pattern, the patterning of the second conductive layer 5 is performed using a photolithography method. In that case, as shown in FIG. 4, a mask 9 is formed on the second conductive layer 5, and the portion of the second conductive layer 5 not covered with the mask is removed by etching.

  In order to perform patterning easily, for example, a dispersion liquid or a sol-gel liquid containing a conductive material such as a metal nanoparticle dispersion solution and a solvent is applied to a necessary region on the first conductive layer 4 by a printing method. The patterned second conductive layer 5 may be formed by direct application. Alternatively, by using an electroless plating method, a plating catalyst or a plating catalyst precursor is directly printed on a necessary region on the first conductive layer 4 to perform patterning, and the plating catalyst or the plating catalyst precursor together with the first conductive layer and the like. The patterned second conductive layer 5 may be formed by immersing the body in an electroless plating solution containing metal ions of the conductive material and depositing metal or the like.

  By these patterning, as shown in FIG. 5, the second conductive layer 5 is formed at a desired position suitable for the bottom gate / bottom contact structure.

  The layer thickness of the second conductive layer is preferably 10 to 1000 nm, and more preferably 50 nm to 500 nm.

  Next, using the patterned second conductive layer 5 as a mask, the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the second conductive layer 5, and the first conductive layer 4 is shown in FIG. The source / drain electrode 7 is formed by patterning as shown. For example, when the etching selectivity of the etchant is first conductive layer 4: second conductive layer 5 = 10: 1, when the first conductive layer 4 is etched by 500 nm, the second conductive layer 5 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the second conductive layer is insoluble is used.

  As the alkaline etching solution, a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be adjusted in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more. A commercially available alkaline etching solution may be used, and specific examples include “Melstrip” (trade name) series manufactured by Meltex Co., Ltd. and the like. A more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.

  As a combination of materials for obtaining a desired etching selection ratio, when tungsten oxide is used for the first conductive layer 4, gold, silver, copper, or silver, copper and palladium alloy is used for the second conductive layer 5. Is more preferable. Tungsten oxide of the first conductive layer 4 is soluble in TMAH, but gold, silver, copper, or silver, copper, and a palladium alloy are insoluble. Therefore, a very high selection ratio can be obtained. Further, if only the etching selectivity is taken, the second conductive layer 5 is made of Al, Cd, Co, Cr, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W other than those described above. Zn, Zr, and the like may be used, but are not preferable from the viewpoint of process such as etching and the charge injection property to the semiconductor layer. In particular, from the aspect of charge injection into an organic semiconductor, gold, silver, copper, or silver, copper, and a palladium alloy are preferable. These metals are fired by firing the organic semiconductor layer 8 that has been applied and formed. Compared with the case where no etching is performed, a higher hole injection property to the organic semiconductor layer 8 can be obtained.

  As another patterning method, an alkaline resist stripping solution or the like may be used, and the first conductive layer 4 may be stripped simultaneously with the resist stripping.

  The first conductive layer 4 before patterning functions as a protective layer that protects the gate insulating layer 3 from process damage when forming the second conductive layer 5. The first conductive layer 4 has a function of improving the adhesion between the gate insulating layer 3 and the second conductive layer 5. Further, the first conductive layer 4 has a function as a barrier layer, a function as a charge injection layer to the organic semiconductor layer 8, and the like.

  The function of the first conductive layer 4 as a protective layer refers to a function of protecting the constituent members from physical and chemical external factors generated during the manufacturing process of the organic thin film transistor. For example, in the case of an organic insulating layer, the contact angle and the surface roughness change when the surface is damaged, but these changes can be suppressed by providing a protective layer.

  The function of enhancing the adhesion between the gate insulating layer and the second conductive layer of the first conductive layer 4 is a grid pattern defined in “JISG0202” as a quantitative evaluation by the scratch test method and a method for more easily confirming This can be confirmed by testing.

  The function of the first conductive layer 4 as a barrier layer refers to a function of preventing diffusion of metal molecules into a peripheral film, a function of imparting electromigration and stress migration resistance. This function can be confirmed by conducting composition analysis in the layer thickness direction by XPS, AES, TOF-SIMS, or the like, and confirming that metal atoms are not diffused in the organic insulating film. In addition, regarding electromigration and stress migration, it can be determined that no problem has occurred if there is no significant change in the resistance value of the electrode and the organic thin film transistor is in a desired movement.

  Here, electromigration is caused by the movement of metal atoms in a metal wiring subjected to a large current stress, resulting in void formation or accumulation of atoms, causing failures such as an increase in wiring resistance, disconnection, and short between wirings. A phenomenon. In addition, stress migration refers to the stress that the metal wiring film receives from the protective layer (passivation film) or interlayer insulating film, causing atomic movement in the wiring due to high-temperature treatment or temperature cycle, resulting in fluctuations in resistance value or disconnection. Refers to the phenomenon.

  The function as a charge injection layer into the organic semiconductor layer 8 refers to a function of injecting holes or electrons into the organic semiconductor layer 8. This function can be confirmed by evaluating electrical characteristics of the organic thin film transistor.

  As shown in FIG. 7, the organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer 3 between the source electrode and the drain electrode by, for example, a spin coating method. As a method for laminating the organic semiconductor layer 8, a coating method such as a spin coating method, a dip coating method, a blade coating method, a capillary coating method, a slit coating method, a spray coating method, or a printing method is preferable.

The organic semiconductor material is not particularly limited as long as it is a material that can be dissolved in a solvent and form the organic semiconductor layer 8 by a coating method. Examples of the organic semiconductor material include 6,13-bis (triisopropylsilylethynyl) pentacene (6,13-bis (triisopropylsilylethynyl) pentacene (Tips-Pentacene)), 13,6-N-sulfinylacetamidopentacene (13,6- N-sulfinyl
acetamidopentacene (NSFAAP)), 6,13-dihydro-6,13-methanopentacene-15-one (6,13-Dihydro-6,13-methanopentacene-15-one (DMP)), pentacene-N-sulfinyl-n -Pentacene-N-sulfinyl-n-butylcarbamate adduct, pentacene-N-sulfinyl-tert-butylcarbamate (Pentacene-
Pentacene precursors such as N-sulfinyl-tert-butylcarbamate), [1] benzothieno [3,2-b] benzothiophene ([1] Benzothieno [3,2-b] benzothiophene (BTBT)), porphyrin, soluble group Low molecular weight compounds such as oligothiophene having an alkyl group, etc., polythiophene such as poly (3-hexylthiophene) (P3HT), fluorene copolymer (for example, a copolymer having a fluorenediyl group and a thiophene diyl group), etc. Examples thereof include molecular compounds.

  As shown in FIG. 1, the protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 8 by a spin coating method or the like. At this time, if necessary, the protective layer 10 may be subjected to patterning such as contact hole formation. When performing pattern formation, it is preferable that the organic insulating material contained in the protective layer 10 has photosensitivity. As the organic insulating material, a material having no polarization is preferable, and a material having a dielectric constant of 1.5 (F / m) or more and 4.0 (F / m) or less is desirable. Moreover, you may make it harden | cure by bridge | crosslinking, an organic insulating material may be dried and a film may be formed, and high withstand voltage may be ensured.

  Organic insulating materials include PMMA (polymethyl methacrylate), polystyrene, polyethylene, polyimide-free resin, such as “Cytop” (registered trademark) manufactured by Asahi Glass Co., “TEFLON” (registered trademark) manufactured by Dupont Trademark) and the like. Moreover, you may use the copolymer which has a repeating unit contained in these resin, the composition containing this resin or this copolymer. The copolymer preferably includes a repeating unit having no polarization such as a repeating unit derived from styrene, and the composition preferably includes a polymer compound having no polarization such as polystyrene.

  In one embodiment, the organic thin film transistor manufacturing method of the present invention is such that the source electrode and the drain electrode of the organic thin film transistor having the bottom gate / bottom contact structure include the third conductive layer 6, and the formation of the third conductive layer 6 is as follows. The patterned second conductive layer 5 and a layer of a conductive material are formed on the exposed portion of the first conductive layer 4 so that the second conductive layer 5 is completely covered with the layer. This is done by patterning. This aspect will be described in detail below.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 8 is a sectional view showing the structure of an organic thin film transistor according to the second embodiment of the present invention. This organic thin film transistor has a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 on a substrate 1, and a first conductive layer 4, a second conductive layer 5, and a second conductive layer are formed on the gate insulating layer 3. A source electrode and a drain electrode made of three conductive layers 6 are provided, an organic semiconductor layer 8 is provided between the source / drain electrodes 7, and a protective layer 10 covering the organic semiconductor layer 8 is provided.

  The materials included in the substrate 1, the gate electrode 2, and the gate insulating layer 3 and the formation method of the organic thin film transistor are the same as those in the first embodiment.

  Next, the source / drain electrodes will be described. The source / drain electrode 7 includes a first conductive layer 4, a second conductive layer 5, and a third conductive layer 6. When laminating the first conductive layer on the organic insulating layer, a coating method, an electroless plating method or an atomic layer deposition method is preferably used, and a coating method is more preferably used. By using these methods, process damage to the organic insulating material contained in the gate insulating layer 3 is reduced.

  Among them, the first conductive layer 4 is preferably coated with a solution containing a conductive material and a solvent on the gate insulating layer 3 and dried to form a continuous layer as shown in FIG. Form. The material contained in the first conductive layer 4, the method of laminating the first conductive layer 4, and the function of the first conductive layer 4 are the same as those in the first embodiment.

  The second conductive layer 5 is preferably laminated as a continuous layer on the first conductive layer 4 as shown in FIG. Thereafter, the second conductive layer 5 is patterned using a mask 9 as shown in FIG. 11, and formed at a desired position as shown in FIG. The material contained in the second conductive layer 5 and the method of forming and patterning the second conductive layer 5 are the same as those in the first embodiment.

  As shown in FIG. 13, the third conductive layer 6 is preferably formed as a continuous layer on the first conductive layer 4 and the second conductive layer 5 and then patterned.

  The third conductive layer 6 can be laminated by sputtering from TaN, for example. Thereafter, a mask is formed on the stacked continuous layers by a printing method or the like, and the patterning is performed by removing the portion of the third conductive layer 6 (TaN film) not covered with the mask by wet etching. As an etching solution for TaN, for example, “667501” (trade name) manufactured by Sigma-Aldrich is used. By the patterning, a third conductive layer 6 is formed on the second conductive layer 5 as shown in FIG.

  For example, the third conductive layer 6 is formed so as to cover the upper surface and the side surface of the second conductive layer 5 and the end portion is in contact with the upper surface of the first conductive layer.

  In addition to TaN, the material contained in the third conductive layer 6 may be a metal, a metal compound, an alloy containing a metal, a semiconductor, a compound of a semiconductor, an alloy containing a semiconductor, an oxide semiconductor, or the like. Specific examples of metals, metal compounds, metal-containing alloys, semiconductors, semiconductor compounds, semiconductor-containing alloys, and oxide semiconductors include metals that may be included in the first conductive layer 4, metal compounds, and metals. The same material as an alloy containing a semiconductor, a semiconductor, a compound of a semiconductor, an alloy containing a semiconductor, and an oxide semiconductor can be given. Among these, Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, compounds of these metals, oxides or nitrides of these metals, Alloys containing any of these metals, Si, B, Ge, compounds of these semiconductors, alloys containing any of these semiconductors, ZnO, ZTO (ZnSnO), CdSnO, GaSnO, TlSnO, InGaZnO, CuAlO, SrCuO An oxide semiconductor typified by LaCuOS or the like is preferable.

  If these metals or semiconductors are used, migration performance higher than that of silver or silver / palladium / copper alloy used for the second conductive layer 5 can be obtained, and thus a function as a barrier layer can be obtained. More preferably, an oxide semiconductor material or a material having a high work function such as Pd, Au, Pt, or Ir is more preferable from the viewpoint of charge injection.

  The conductivity of the second conductive layer 5 is preferably higher than the conductivity of the third conductive layer 6. Since the conductivity of the second conductive layer 5 is higher than the conductivity of the third electrode layer 6, it is possible to give the second conductive layer a function as a wiring layer such as a bus line that is indispensable for the element configuration. It is because it becomes.

  Besides the sputtering method, the third conductive layer 6 may be laminated by a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, or an electroless plating method. The third conductive layer 6 may be grown and stacked by an atomic layer deposition (ALD) method or the like. In the case of laminating by the ALD method, materials contained in the conductive layer 6 include Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, Pt, Ir, Co, Fe, V, Zr, and these metals. An alloy containing any of the above, oxides of these metals, nitrides of these metals, and the like.

  Thereafter, the third conductive layer 6 may be patterned by directly printing an etching protective layer by patterning by photolithography or printing.

  In order to easily perform patterning, for example, a dispersion solution or a sol-gel solution containing a conductive material such as a metal fine particle dispersion solution and a solvent is directly applied on the second conductive layer 5 by a printing method, The third conductive layer 6 may be formed. Alternatively, a plating catalyst or a plating catalyst precursor is printed directly on the second conductive layer 5 by using an electroless plating method, and the plating catalyst or the plating catalyst precursor is made of the conductive material together with the second conductive layer or the like. The third conductive layer 6 may be formed by depositing a metal or the like by dipping in an electroless plating solution containing metal ions.

  The layer thickness of the third conductive layer is preferably 10 to 500 nm, and more preferably 10 to 100 nm.

  Next, using the patterned third conductive layer 6 as a mask, the first conductive layer 4 is wet-etched with an alkaline etchant having a high etching selectivity with respect to the third conductive layer 6, and the first conductive layer 4 is shown in FIG. The source / drain electrode 7 is formed by patterning as shown. For example, when the etching selectivity of the etchant is first conductive layer 4: third conductive layer 6 = 10: 1, when the first conductive layer 4 is etched by 500 nm, the third conductive layer 6 has a thickness of 50 nm. Only etched. In this case, more preferably, an etching solution in which the third conductive layer 6 is insoluble is used.

  As the alkaline etching solution, a dilute aqueous solution of potassium hydroxide (KOH) or a dilute aqueous solution of tetramethylammonium hydroxide (TMAH) may be used, and the concentration of the solution may be set in any way for adjusting the etching rate. Although it can be changed, it is preferably 0.1 wt% or more. Moreover, you may use a commercially available alkaline etching liquid and the Melstrip series by Meltex, etc. are mentioned. A more preferred alkaline etching solution is a dilute aqueous solution of tetramethylammonium hydroxide aqueous solution (TMAH) free from metal ions.

  As another patterning method, the third conductive layer 6 and the first conductive layer 4 may be simultaneously peeled and patterned with a TaN etchant that is an alkaline etchant.

The third conductive layer 6 covers the upper surface and side surfaces of the second conductive layer 5 and has a function as a barrier layer.
The third conductive layer 6 covers the upper surface and side surfaces of the second conductive layer 5 and has a function as a charge injection layer into the organic semiconductor layer.

  At this time, in order for the third conductive layer 6 to reliably cover the side surface of the second conductive layer 5, the third conductive layer 6 preferably protrudes 10 nm or more per side with respect to the second conductive layer 5, More preferably, it protrudes about 1000 nm. Therefore, the first conductive layer 4 inevitably has a structure that protrudes from the second conductive layer 5 in the same amount as the third conductive layer 6.

  As shown in FIG. 16, the organic semiconductor layer 8 made of an organic semiconductor material can be laminated on the gate insulating layer between the source electrode and the drain electrode. The material contained in the organic semiconductor layer 8 and the method for forming the organic semiconductor layer 8 are the same as those in the first embodiment.

  As shown in FIG. 8, the protective layer 10 can be laminated by applying a solution containing an organic insulating material and a solvent on the organic semiconductor layer 7. The material contained in the protective layer 10 and the method for forming the protective layer 10 are the same as those in the first embodiment.

  The organic thin film transistor of the present invention can be used for active matrix display devices and circuits. In addition, the printing methods mentioned in the text are the slit coating method, the capillary coating method, the blade coating method, the spray coating method, the plateless printing method represented by the ink jet method, the flexographic printing, the gravure printing, and the offset printing. Plate printing methods represented by screen printing, microcontact printing, and nanoimprinting.

Synthesis example 1
(Synthesis of polymer compound 1)
Styrene (made by Wako Pure Chemical Industries) 2.06 g, 2,3,4,5,6-pentafluorostyrene (made by Aldrich) 2.43 g, 2- [O- [1′-methylpropylideneamino] carboxyamino] ethyl -Methacrylate (made by Showa Denko, trade name “Karenz MOI-BM”) 1.00 g, 2,2′-azobis (2-methylpropionitrile) 0.06 g, 2-heptanone (made by Wako Pure Chemical Industries) 14.06 g Is put in a 50 ml pressure vessel (made by ACE), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to form a viscous 2-heptanone solution in which the polymer compound 1 is dissolved. Got. The high molecular compound 1 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating unit.

高分子化合物１

Polymer compound 1

  The weight average molecular weight calculated | required from the standard polystyrene of the obtained high molecular compound 1 was 32800 (Shimadzu GPC, one "Tskel super HM-H" + one "Tskel super H2000", mobile phase = THF). .

Synthesis example 2
(Synthesis of polymer compound 2)
4-aminostyrene (manufactured by Aldrich) 3.50 g, 2,3,4,5,6-pentafluorostyrene (manufactured by Aldrich) 13.32 g, 2,2′-azobis (2-methylpropionitrile) 0.08 g 25-36 g of 2-heptanone (manufactured by Wako Pure Chemical Industries, Ltd.) was placed in a 125 ml pressure vessel (manufactured by Ace), bubbled with nitrogen, sealed, and polymerized in an oil bath at 60 ° C. for 48 hours to obtain a polymer compound. A viscous 2-heptanone solution in which 2 was dissolved was obtained.
The high molecular compound 2 has the following repeating unit. Here, the number in parentheses indicates the mole fraction of the repeating unit.

高分子化合物２

Polymer compound 2

  The weight average molecular weight calculated | required from the standard polystyrene of the obtained high molecular compound 2 was 132000 (Shimadzu GPC, one "Tskel super HM-H" + one "Tskel super H2000", mobile phase = THF). .

Synthesis example 3
(Synthesis of polymer compound 3)
In toluene (80 mL) containing 6.40 g of 9,9-di-n-octylfluorene-2,7-di (ethylene boronate) and 4.00 g of 5,5′-dibromo-2,2′-bithiophene Under nitrogen, 0.18 g of tetrakis (triphenylphosphine) palladium, 1.0 g of methyltrioctylammonium chloride (manufactured by Aldrich, trade name “Aliquat 336” (registered trademark)), and 24 mL of 2M aqueous sodium carbonate solution were added. It was. The mixture was stirred vigorously and heated to reflux for 24 hours. The viscous reaction mixture was poured into 500 mL of acetone to precipitate a fibrous yellow polymer. The polymer was collected by filtration, washed with acetone and dried in a vacuum oven at 60 ° C. overnight. The resulting polymer is referred to as polymer compound 3. The high molecular compound 3 has the following repeating unit. n indicates the number of repeating units. The weight average molecular weight calculated | required from the standard polystyrene of the high molecular compound 3 was 61000 (Shimadzu GPC, one "Tskel super HM-H" + one "Tskel super H2000", mobile phase = THF).

高分子化合物３

Polymer compound 3

Example 1
(Manufacture of organic thin-film transistors)
Examples of the organic thin film transistor of the present invention will be described with reference to FIGS.

  In this embodiment, a substrate (glass) 1, a gate electrode (Mo) 2 on the substrate 1, a gate insulating film (organic insulating film) 3 on the gate electrode 2, and a first conductive layer on the gate insulating film 3 4 and the second conductive layer 5 and the drain electrode 7 formed of the first conductive layer 4 and the second conductive layer 5 are formed, and an organic semiconductor is formed between the source electrode 7 and the drain electrode 7. Layer 8 was formed to produce an organic thin film transistor.

About the manufactured organic thin-film transistor, the transistor characteristic was measured in the vacuum prober, the characteristic was compared, and the effect of this invention was confirmed. The pressure of the vacuum prober at this time was about 5 × 10 ⁻³ Pa.

Next, the element manufacturing process of the present invention will be described.
First, a Mo (molybdenum) layer was formed on the cleaned substrate 1 by sputtering, and the gate electrode 2 was formed by photolithography. In photolithography, the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd., the developer is “NPD-18” manufactured by Nagase ChemteX, and the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd. As the Mo etching solution, “S-80520” manufactured by Kanto Chemical Co., Inc. was used. Photolithography was performed by the following steps. A film of photoresist “TFR-HPL” was formed on the Mo layer, and irradiated with 365 nm UV light through a photomask. Next, the photoresist was developed using a developing solution “NPD-18”. Next, using the developed photoresist as a mask, the Mo exposed portion of the Mo layer is removed using Mo etching solution “S-80520”, and the remaining photoresist is removed using resist stripping solution “106”. After peeling, the gate electrode 2 was patterned.

  Next, the substrate on which the gate electrode 2 is formed is wet-cleaned, and then the substrate is cleaned with a UV ozone cleaner for 300 seconds, and then a solution containing the polymer compound 1, the polymer compound 2, and 2-heptanone is gated. An organic layer was formed on the electrode 2 by spin coating. Since this organic layer is thermally crosslinkable, it was immediately fired to obtain the gate insulating layer 3. The baking treatment at this time was carried out at 220 ° C. for 25 minutes as the final baking treatment. The layer thickness of the gate insulating layer 3 was about 470 nm.

Next, a sol-gel solution of pentavalent tungsten oxide (W ₂ O ₅ ) was applied onto the gate insulating layer 3 by a spin coating method. After coating, the film was dried in the air for about 5 minutes, and then baked at 150 ° C. for 30 minutes to obtain the first conductive layer 4 shown in FIG. In order to determine the layer thickness of the first conductive layer 4, the layer thickness of the layer formed by applying in advance under the same conditions was 30 nm.

The sol-gel solution of W ₂ O ₅ used for forming the first conductive layer 4 uses tungsten (V) ethoxide as a tungsten alkoxide and is a β-diketone compound as a stabilizer. Acetylacetone was used. 2,3,4,5,6-pentafluorotoluene was used as the solvent for the sol-gel solution of the substrate prepared this time.

  Next, copper (Cu) was formed with a layer thickness of 100 nm on the first conductive layer 4 by a sputtering method, and the second conductive layer 5 shown in FIG. 3 was obtained. Thereafter, the second conductive layer 5 was processed by the photolithography method into the shape of the second conductive layer 5 shown in FIG. In photolithography, the photoresist is “TFR-H PL” manufactured by Tokyo Ohka Kogyo Co., Ltd., the developer is “NPD-18” manufactured by Nagase ChemteX, and the resist stripper is “106” manufactured by Tokyo Ohka Kogyo Co., Ltd. As a Cu etching solution, a mixed acid “Cu-03” manufactured by Kanto Chemical Co., Inc. was used. Photolithography was performed by the following steps. A film of photoresist “TFR-H PL” was formed on the Cu layer, and irradiated with 365 nm UV light through a photomask. Next, the photoresist was developed using a developing solution “NPD-18”. Next, using the developed photoresist as a mask, the portion of the second conductive layer 5 where Cu is exposed is removed using a Cu etching solution “Cu-03”, and the remaining portion is removed using a resist stripping solution “106”. The photoresist was peeled off and the second conductive layer 5 was patterned.

  Next, using the patterned second conductive layer 5 as a mask, a portion of the first conductive layer 4 not covered with the second conductive layer 5 with a tetramethylammonium hydroxide aqueous solution (TMAH aqueous solution: concentration 2.38%) ( The exposed portion was etched to obtain an element structure shown in FIG. The etching time at this time was 90 seconds. Finally, in order to improve the adhesion between the gate insulating film 3 and the first electrode layer 4 and the second electrode layer 5 and to remove water adhering during the process, the final baking is performed in a nitrogen atmosphere with an oxygen concentration of less than 0.1 ppm. This was carried out at 200 ° C. for 10 minutes in a glove box having a moisture concentration of less than 1.0 ppm.

  By providing the first conductive layer 4, the surface of the gate insulating layer 3 can be protected from process damage when the second conductive layer 5 is formed. Further, by providing the first conductive layer 4, adhesion between the gate insulating layer 3 and the second conductive layer 5 is improved. The first conductive layer also functions as a protective layer against diffusion of the second conductive layer 5 into the gate insulating layer 3.

  Next, as the organic semiconductor layer 8, the polymer compound 3 is dissolved in a xylene solution at a concentration of 0.5 wt%, and is applied onto the substrate by a spin coating method in a glove box under a nitrogen atmosphere. The calcination process for 1 minute was implemented. At this time, the thickness of the organic semiconductor layer was about 16 nm. In this way, an organic thin film transistor having the structure shown in FIG. 7 was obtained. At this time, the surface treatment to the source electrode and the drain electrode was not performed.

After that, as a transistor characteristic with a vacuum prober, a transmission (Vg-Id) characteristic of 20 to -40 V and an output (Vd-Id) characteristic of 0 to -40 V were measured. The vacuum degree of the vacuum prober at this time was about 5 × 10 ⁻³ Pa. Table 2 shows the transistor characteristics.

  The gate insulating layer surface roughness Ra of the gate insulating layer was measured using a scanning probe microscope (product name “SPI3800N”, manufactured by SII (Nanotechnology)). The surface contact angle of the gate insulating layer was measured using an automatic contact angle measuring device (trade name “OCA20”, manufactured by Eihiro Seiki Co., Ltd.). Mobility μ, maximum current Ion, threshold voltage Vth, hysteresis, Swing Factor (sub-threshold swing), and On / Off ratio were determined from transmission (Vg−Id) characteristics. Further, the weak inversion region formation starting voltage at which the drain current Id having the transmission (Vg−Id) characteristic rises is defined as the drain current rising voltage Von, and is shown in Table 2 separately from the threshold voltage Vth.

Comparative Example 1
As a comparative example, a substrate (glass) 1, a gate electrode (Mo) 2 on the substrate 1, a gate insulating layer (organic insulating layer) 3 on the gate electrode 2, and a second of the present invention on the gate insulating layer 3 An organic thin film transistor is manufactured by forming a single-layer source electrode and drain electrode of a single metal single layer of the same material as the conductive layer 5, and forming an organic semiconductor layer between the source electrode and the drain electrode. did.

  That is, the first conductive layer 4 was not formed, but the second conductive layer 5 was formed on the gate insulating layer 3 by a sputtering method and patterned by photolithography to form a source electrode and a drain electrode. The organic thin-film transistor was manufactured similarly to 1, and the transistor characteristic was measured. Table 2 shows the obtained transistor characteristics.

Reference example 1
In the same manner as in Example 1, the gate electrode 2 was formed on the substrate 1, and the gate insulating layer 3 was formed on the gate electrode. The gate insulating layer surface roughness Ra and the gate insulating layer surface contact angle of the gate insulating layer were measured. The results are shown in the column of unprocessed gate insulating layer in Table 2.

[Table 2]

  It can be seen that all the transistor characteristics of the organic thin film transistor of Example 1 are improved compared to the organic thin film transistor of Comparative Example 1. Further, regarding the surface roughness and the surface contact angle of the gate insulating layer 3, the organic thin film transistor of Example 1 has greatly reduced process damage to the gate insulating layer when the Cu layer is formed by the sputtering method. The value is equivalent to that of the gate insulating layer not passing through the process in Example 1. In the organic thin film transistor of Comparative Example 1, since the Cu layer was directly formed on the organic insulating layer by a high-power sputtering method, the physical damage to the gate insulating layer was affected by the surface roughness and the surface contact angle of the gate insulating layer 3. It appears remarkably.

  Compared with the organic thin film transistor of Comparative Example 1, the organic thin film transistor of Example 1 had a drain current rising voltage Von close to 0 [V], almost no hysteresis, and the maximum current Ion improved by about two orders of magnitude.

As mentioned above, the organic thin-film transistor with a high characteristic was obtained by the method of this invention. In the organic thin film transistor of the present invention, the protective layer 10 shown in FIGS. 1 and 8 is more preferably formed last. Furthermore, it is more preferable that the first conductive layer (W ₂ O ₅ layer) 4 has a function as a charge injection layer by using a material having a better charge injection property. The organic thin film transistor of the present invention can be used for active matrix display devices and circuits.

  Needless to say, the present invention is not limited to the examples.

1 ... substrate,
2 ... Gate electrode,
3 ... gate insulating layer,
4 ... 1st conductive layer,
5 ... 2nd conductive layer,
6 ... 3rd conductive layer,
7 ... source / drain electrodes,
8 ... Organic semiconductor layer,
9 ... Mask,
10: Protective layer.

Claims (7)

A gate electrode; a gate insulating layer that covers the gate electrode and includes an organic insulating material; a source electrode and a drain electrode on the gate insulating layer; and An organic thin film transistor having a bottom gate / bottom contact structure, which has an organic semiconductor layer covering a region sandwiched between a source electrode and the drain electrode and covering at least part of the source electrode and the drain electrode. And
The source electrode and the drain electrode have a stacked structure including a first conductive layer stacked on the gate insulating layer and a second conductive layer stacked on the first conductive layer,
The first conductive layer includes one or more materials selected from the group consisting of tungsten oxide, silver oxide, copper oxide, zinc oxide, silver salt, silver and copper,
The second conductive layer includes Ag, Al, Au, Cd, Co, Cr, Cu, Fe, Mg, Mo, Ni, Pb, Pd, Pt, Sn, Ta, Ti, V, W, Zn, Zr, and An organic thin film transistor comprising one or more materials selected from the group consisting of alloys containing any of these metals.   The organic thin-film transistor according to claim 1, wherein the first conductive layer includes one or more materials selected from tungsten oxide and silver oxide.   The organic thin film transistor according to claim 1, wherein the first conductive layer is tungsten oxide.   4. The organic thin film transistor according to claim 3, wherein the tungsten valence of tungsten oxide is pentavalent or a combination of pentavalent and hexavalent.   The organic thin-film transistor according to any one of claims 1 to 4, wherein the second conductive layer is made of gold, silver, copper, or an alloy of silver, copper, and palladium.   The organic thin-film transistor according to claim 5, wherein the first conductive layer is made of only tungsten oxide, and the second conductive layer is made of gold, silver, copper, or an alloy of silver, copper, and palladium.   The source electrode and the drain electrode further include a third conductive layer that covers the two conductive layers, and the third conductive layer includes Ti, Mo, Cr, Ta, W, Ni, Pd, Cu, Au, and Pt. Ir, Co, Fe, V, Zr, compounds of these metals, oxides or nitrides of these metals, alloys containing any of these metals, Si, B, Ge, compounds of these semiconductors, these The organic thin-film transistor as described in any one of Claims 1-6 formed from the alloy containing either of these semiconductors, or an oxide semiconductor.

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