JP2012104204A - Testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing apparatus which can dynamically control a conditional branch based on a match detection and a conditional determination based on a logical comparison.SOLUTION: A match control circuit MC generates a match signal that indicates a pin value, an expected value, and a comparison result when a match flag is asserted. A fail stack register 10 holds an output value of a logical comparator DC. A flash hold register 14 receives a stack pass signal that is asserted when a fail has not occurred in the past and a match signal; holds one of the signals corresponding to a first pattern control signal that is generated in an execution cycle of a first control instruction described in a pattern program; and outputs it as a hold match signal. A match hold selector 16 receives the match signal and the hold match signal; and outputs, as a pin match signal, one of the signals corresponding to a second pattern control signal that is generated in an execution cycle of a second control instruction described in the pattern program.

Description

  The present invention relates to a semiconductor device test apparatus.

  A test apparatus is used to evaluate a semiconductor device such as a memory or an SOC (System On Chip). The test apparatus evaluates a DUT (device under test) based on a test sequence program (also simply referred to as a test program) defined by the user. The test apparatus sequentially executes the processes described in the test program in synchronization with the test cycle.

  The test apparatus has a function of comparing data read from the DUT with an expected value. This is referred to as “logical comparison (processing)” in this specification. In the test apparatus, it may be determined whether the status signal from the DUT satisfies a predetermined condition, and the pattern program may execute conditional branch processing according to the determination result. This conditional branch determination process is also referred to as “match detection” process or simply match process. For example, a DUT incorporating a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit outputs a LOCK signal indicating whether or not a transition to a certain appropriate state is made after the power is turned on. The test apparatus monitors this LOCK signal, detects that the PLL circuit or DLL circuit has transitioned from the unlocked state to the locked state, and executes the subsequent test sequence. The conditional branching process in this case is performed for the LOCK signal.

  As another example, consider a NAND flash memory (hereinafter simply referred to as a flash memory). When a flash memory is instructed to write or read data from the outside, it is necessary to prohibit external access while the processing is being executed. Therefore, the flash memory is in a state indicating whether the data writing / reading process is being executed (busy state) or a state where the next process may be started (ready state) after the process is completed. A signal (hereinafter simply referred to as status signal R / B or R / B signal) is output. For example, in the status signal R / B, a high level indicates a ready state, and a low level indicates a busy state. A memory tester that evaluates such a flash memory monitors the R / B signal and executes conditional branch processing.

The outline of the match detection process is as follows. What is match detection processing?
1. The status signal defined as the detection target is
2. In a predefined test cycle,
3. Determine whether it matches the expected value,
4). It can be defined as a process of branching (jumping) to a predetermined test sequence when they match.

  A test pin (status signal) that is a target of match detection is described by a mnemonic called “MACTH” in the test program. A test cycle for performing match detection is described by a mnemonic called a flag sense instruction such as “FLAG”. An expected value is also defined in the test program, and a test pattern address indicating a predetermined test sequence is also defined in the test program.

JP 2000-40389 JP 2005-44499 A

The flash memory test is performed, for example, as follows. FIG. 1 is a flowchart showing a test procedure of a NAND flash memory.
First, data is written to the DUT (S100). Subsequently, it is determined whether or not the writing is completed (S102). This determination is performed by “match detection” for the R / B signal from the DUT. If the R / B signal is not asserted (N in S102), it is determined that the writing has not been completed, and the count value indicating the cumulative number of writing is incremented (S120). If the count value has not reached the upper limit value (N in S122), write is tried again (S100). When the count value reaches the upper limit (Y in S122), the test is terminated.

  When the R / B signal is asserted (Y in S102), it is determined that the writing is completed. Subsequently, data is read from the DUT (S104), and it is determined whether it is correct by comparing it with an expected value (S106). This determination is made by “logical comparison”. If the written data is correct as a result of the logical comparison (Y in S106), the DUT or one block is determined to be a pass (S108), the test relating to the DUT or the block is terminated, and the next DUT or the next block is determined. Start the test. If the written data is not correct (N in S106), the count value indicating the cumulative number of times of writing is incremented (S130). If the count value has not reached the upper limit value (N in S132), writing is tried again (S100). When the count value reaches the upper limit (Y in S132), the test is terminated.

  Flash memory has a limited number of writes. Therefore, when a plurality of flash memories are measured simultaneously, if a certain DUT is determined to fail and a write retry occurs, it is not preferable that another DUT that has been determined to pass is subject to a write retry. Therefore, the test apparatus is required to have a function of prohibiting subsequent writing of the DUT that has been determined to pass.

  In other words, the flash memory test apparatus requires conditional branching (S102) based on match detection and conditional branching (S108) based on logical comparison.

  The present invention has been made in such a situation, and one of exemplary purposes of an embodiment thereof is to provide a test apparatus capable of dynamically controlling conditional branching based on match detection and conditional determination based on logical comparison. is there.

One embodiment of the present invention relates to a test apparatus. The test apparatus includes a plurality of logical comparators, a plurality of match control circuits, a plurality of fail stack registers, a plurality of flash hold registers, and a plurality of match hold selectors.
Each of the plurality of logical comparators is provided for each pin of the device under test, and generates a comparison signal indicating whether the corresponding pin value matches or does not match the expected value. Each of the plurality of match control circuits MC is provided for each pin. When the match flag is asserted, the match control circuit MC generates a match signal indicating whether or not the corresponding pin value matches the expected value. Each of the plurality of fail stack registers is provided for each pin and holds a comparison signal from a corresponding logical comparator. Each of the plurality of flash hold registers is provided for each pin, and is based on an output value of a corresponding fail stack register and is asserted when a failure has not occurred in the past, and a corresponding match control circuit. And receive a match signal. The flash hold register holds one corresponding to the first pattern control signal generated in the execution cycle of the predetermined first control instruction described in the pattern program, and outputs it as a hold match signal. Each of the plurality of match hold selectors is provided for each pin, receives a match signal from the corresponding match control circuit and a hold match signal from the corresponding flash hold register, and performs predetermined second control described in the pattern program. And a plurality of match hold selectors that output one of them according to the second pattern control signal generated in the instruction execution cycle as a pin match signal.

  According to this aspect, by describing an instruction for generating the first pattern control signal and the second pattern control signal in the pattern program, a conditional branch based on a match signal indicating a match detection result for each test cycle, and a match The branch processing based on the hold match signal holding the signal and the branch processing based on the stack path signal indicating the comparison result of the logical comparison can be dynamically switched and controlled.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to provide a platform that can dynamically control conditional branching based on match detection and conditional determination based on logical comparison.

It is a flowchart which shows the test procedure of NAND type flash memory. It is a block diagram which shows the whole structure of the test apparatus which concerns on embodiment. FIGS. 3A and 3B are circuit diagrams showing a specific configuration example of the flash hold register. 4 is a truth table showing the operation of the flash hold register of FIG. FIGS. 5A and 5B are circuit diagrams showing specific configuration examples of the match hold selector.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 2 is a block diagram showing an overall configuration of the test apparatus 2 according to the embodiment. The test apparatus 2 is a memory tester that tests a DUT 1 including a flash memory, for example, and has a function of measuring a plurality of DUTs 1 simultaneously. Although only blocks corresponding to a single DUT 1 are shown in FIG. 1, actually, a similar block is provided for each of the plurality of DUTs 1.

The test apparatus 2 has a plurality of channels CH _{1 to} CH _N. Each channel CH is associated with each pin of DUT1. The pattern generator PG executes instructions for each test cycle based on a pattern program defined by the user, and generates various control signals, test patterns, expected values, etc. according to the instructions and controls the entire test apparatus 2. . Examples of the control signal include a flash hold load / clear signal (Flash_Hold_Load, Flash_Hold_clear), a write enable signal (/ WE), a chip enable signal (/ CE), pattern control signals CNT1 and CNT2, which will be described later.

  The test apparatus 2 includes a logic comparator DC, a match control circuit MC, a fail stack register 10, a logic gate 12, a flash hold register 14, and a match hold selector 16 provided for each channel CH. The test apparatus 2 further includes a hold matrix circuit 23, a flash counter 24, a limit register 25, a determination circuit 26, an OR gate 27, a NAND gate 28, and a logic gate 20 provided for each DUT.

The logical comparator DC is a unit that performs a “logical comparison” process. The i-th channel logical comparator DC _i compares the value of the data or signal from the corresponding pin of the DUT 1 with the expected value EXP output from the pattern generator PG, and outputs a comparison signal S1 indicating the comparison result. . The comparison signal S1 is “0” when coincidence (pass) and “1” when disagreement (fail).

  The fail stack register 10 holds a comparison signal S1 generated by the logical comparator DC. The fail stack register 10 is reset when a clear signal (Clear signal) generated by the pattern generator PG is asserted. Specifically, when the data stored in the fail stack register 10 is transferred to the subsequent flash hold register 14, that is, when a Flash_Hold_Load signal described later is asserted, the fail stack register 10 is cleared.

  The logic gate 12 logically inverts the value stored in the fail stack register 10. The output signal (stack_pass signal) of the logic gate 12 is asserted (“1”) when the corresponding pin of the DUT 1 is determined to pass.

The match control circuit MC is a unit that performs “match detection” processing. The match control circuit MC is similar to the logic comparator DC in that a signal at a certain pin is compared with an expected value, but specifically performs the following processing.
The match control circuit MC compares the status signal from the corresponding pin of the DUT 1 with the expected value EXP generated by the pattern generator PG in the test cycle in which the match flag FLG generated by the pattern generator PG is asserted. A match signal (match signal) indicating the comparison result is output. The match signal is “1” when matching (pass), and “0” when mismatching (fail).
Note that the match control circuit MC of a channel that is not a target for match detection outputs a match signal indicating the path “1”. As a result, in the subsequent logic gate 20, when the logical product of the match signals of a plurality of channels is taken, the match signals of channels that are not subject to match detection can be masked.

  In addition to the corresponding stack_pass signal and the corresponding match signal, the flash hold register 14 includes a first pattern control signal CNT1, a flash hold load signal (Flash_Hold_Load signal), and a flash hold clear signal (Flash_Hold_clear) as control signals according to the pattern program. Signal).

  The Flash_Hold_Load signal is asserted in the cycle in which the load instruction described in the pattern program is executed. When the Flash_Hold_Load signal is asserted, the flash hold register 14 holds one of the stack_pass signal and the match signal corresponding to the first pattern control signal CNT1. The held value is output as a hold match signal (hold_match signal). A clear signal (Flash_Hold_clear signal) is asserted in a cycle in which a clear instruction described in the pattern program is executed. When the Flash_Hold_Load signal is asserted, the flash hold register 14 clears the held value.

  In the pattern program, a predetermined instruction (referred to as a first control instruction) for generating the first pattern control signal CNT1 can be described. That is, the first control pattern signal CNT1 is dynamically generated in a cycle in which the first control command is executed. In other words, the match signal can be held in the flash hold register 14 in a certain test cycle, and the stack_pass signal can be held in another test cycle. This is one of the features not found in conventional test equipment.

  FIGS. 3A and 3B are circuit diagrams showing a specific configuration example of the flash hold register 14. The first control pattern signal CNT1 includes first data Match_Mode_Sel [2] and second data Match_Mode_Sel [3]. The first data Match_Mode_Sel [2] is asserted in a cycle in which the match signal is to be selected in response to the first control instruction. The second data Match_Mode_Sel [3] is asserted in a cycle in which the stack_pass signal is to be selected.

The flash hold register 14a of FIG. 3A includes a register (latch circuit) 30, a first AND gate 32, a second AND gate 34, and a first OR gate 36.
The first AND gate 32 generates a logical product of the first data Match_Mode_Sel [2] and “match”. The second AND gate 34 generates a logical product of the second data Match_Mode_Sel [3] and the stack_pass signal. The first OR gate 36 generates a logical sum of output signals of the first AND gate 32 and the second AND gate 34.
When the Flash_Hold_Load signal is asserted, the output signal of the first OR gate 36 is loaded into the register 30. When the Flash_Hold_clear signal is asserted, the value of the register 30 is cleared. According to the flash hold register 14a, the match signal and the stack_pass signal can be switched and held dynamically every test cycle.

  FIG. 3B shows a configuration of the flash hold register 14b of the modification of FIG. The flash hold register 14b further receives a match mode signal (Match_Mode signal) and a flash hold mode signal (Flash_Hold_Mode signal). Note that the Match_Mode signal and the Flash_Hold_Mode (1-4) signals are static values read from the mode control register and are not data that can be changed for each test cycle.

  The flash hold register 14b of FIG. 3B can be switched between the “dynamic control mode” and the “static control mode”. In the dynamic control mode, the flash hold register 14b is controlled according to the first control pattern signal CNT1. That is, it operates in the same manner as the flash hold register 14 of FIG. In the static control mode, the flash hold register 14b is controlled according to the Flash_Hold_Mode (1 to 4) signal, not the first control pattern signal CNT1. The Match_Mode signal is a control signal for switching between the dynamic control mode and the static control mode, and is set to the dynamic control mode when “0” and to the static control mode when “1”.

  The first selector 38 receives the match signal and the output of the first AND gate 32, and selects one corresponding to the Match_Mode signal. The second selector 40 receives the stack_pass signal and the output of the second AND gate 34 and selects one corresponding to the Match_Mode signal.

The logic circuit 36 b includes a third selector 37 and an AND gate 39 in addition to the first OR gate 36.
The AND gate 39 generates a logical product of the Match_Mode signal and the Flash_Hold_Mode 1/2/3/4 signal. The third selector 37 is controlled by the output of the AND gate 39. The third selector 37 is through when the Match_Mode signal is “0” (dynamic control mode). Further, when the Match_Mode signal is “1” (static control mode), the third selector 37 passes one corresponding to the Flash_Hold_Mode (1/2/3/4) signal and sets the other value to “0”. . For example, when Flash_Hold_Mode 1 or Flash_Hold_Mode 3 is “1”, the match signal is passed, and when Flash_Hold_Mode 2 or Flash_Hold_Mode 4 is “1”, the stack_pass signal is passed.

  According to the flash hold register 14b of FIG. 3B, the mode can be switched by the Match_Mode signal, and the control by the pattern program and the control by the register can be switched.

  FIG. 4 is a truth table showing the operation of the flash hold register 14b of FIG. Those skilled in the art can use various modifications of the flash hold register 14b that satisfies the truth table of FIG.

  Returning to FIG. The match hold selector 16 is provided for each pin. The match hold selector 16 receives the corresponding match signal and the corresponding hold_match signal, selects one corresponding to the second control signal CNT2, and outputs it as a pin match signal (match_pin signal). The second control signal CNT2 is generated in an execution cycle of a predetermined second control instruction described in the pattern program.

  FIGS. 5A and 5B are circuit diagrams showing a specific configuration example of the match hold selector 16. The second control pattern signal CNT2 described above includes third data Match_Mode_Sel [0] and fourth data Match_Mode_Sel [1]. The third data Match_Mode_Sel [0] is asserted in a cycle in which the match signal is to be selected according to the second control instruction. The fourth data Match_Mode_Sel [1] is asserted in a cycle in which the hold_match signal is to be selected.

  The flash hold register 14a of FIG. 5A includes a third AND gate 42, a fourth AND gate 44, and a second OR gate 46. The third AND gate 42 generates a logical product of the third data Match_Mode_Sel [0] and “match”. The fourth AND gate 44 generates a logical product of the fourth data Match_Mode_Sel [1] and the hold_match signal. The second OR gate 46 generates a logical sum of the output signals of the third AND gate 42 and the fourth AND gate 44 and outputs the logical sum as a match_pin signal.

  According to the match hold selector 16a, the match signal and the hold_match signal can be switched dynamically every test cycle.

  FIG. 5B shows a configuration of the match hold selector 16b of the modified example of FIG. The match hold selector 16b receives a Match_Mode signal and a Flash_Hold_Mode (1 to 4) signal, similarly to the flash hold register 14b of FIG.

  The match hold selector 16b in FIG. 5B can switch between the dynamic control mode and the static control mode. In the dynamic control mode, the match hold selector 16b is controlled according to the second control pattern signal CNT2. That is, the operation is similar to that of the match hold selector 16a of FIG. In the static control mode, the match hold selector 16b is controlled according to the Flash_Hold_Mode (1 to 4) signal, not the second control pattern signal CNT2.

  The fourth selector 48 receives the match signal and the output of the third AND gate 42, and selects one according to the Match_Mode signal. The fifth selector 50 receives the hold_match signal and the output of the fourth AND gate 44 and selects one in accordance with the Match_Mode signal. The configuration of the logic circuit 46b is the same as that of the logic circuit 36b in FIG. When the Match_Mode signal is “1” (static control mode), the sixth selector 47 passes one corresponding to the Flash_Hold_Mode (1/2/3/4) signal and sets the other value to “0”. For example, when any of the Flash_Hold_Modes 1 to 4 is “1”, the hold_match signal is allowed to pass, and when all of them are “0”, the match signal is allowed to pass.

  According to the match hold selector 16b of FIG. 5B, the pattern program control (dynamic control mode) and the register control (static control mode) can be switched by the Match_Mode signal.

  Returning to FIG. The match_pin signal generated in each channel indicates the result of condition determination for each pin (channel). The logic gate 20 generates a logical product of match_pin signals for each of a plurality of pins of the common DUT, and outputs a DUT match signal (match_dut signal). The match_dut signal indicates the result of condition determination in units of DUT. Further, the logic gate 22 generates a logical product of a plurality of match_dut signals generated for each of the plurality of DUTs, and outputs the logical product as a total match signal (match_total signal). The pattern generator PG performs conditional branching based on the match_total signal.

  A hold matrix circuit 23, a flash counter 24, a limit register 25, a determination circuit 26, an OR gate 27, and a NAND gate 28 are provided for each DUT 1. The hold matrix circuit 23 performs a logical operation on the flash_hold signal generated for each of a plurality of pins of the common DUT.

A flash_hold signal of a pin is “1”.
(I) Indicates that a pass is determined by detecting the match of the pin. (Ii) Indicates that no failure has occurred in the data of the pin.
The hold matrix circuit 23 generates an inhibit signal (Inhibit) S2 that is asserted when the flash_hold signal of all the pins of the corresponding DUT is “1”. The inhibition signal S2 can be generated by taking the logical product of the flash_hold signals of a plurality of pins.

  The hold matrix circuit 23 asserts the count increment signal (FCINC) and increments the flash counter 24 when at least one of the flash_hold signals of all the pins of the corresponding DUT is “0”.

  The flash counter 24 counts up under the control of the hold matrix circuit 23. The count value of the flash counter 24 indicates the number of times that the corresponding DUT match detection has failed or the number of times that the corresponding DUT has been failed in the logical comparison. In the limit register 25, an upper limit value LIMIT indicating the maximum number of retries is written. The determination circuit 26 compares the count value of the flash counter 24 with the upper limit value LIMIT, and when the count value reaches the upper limit value, asserts ("1") the hard fail signal (Hard_Fail) S3 that is the output. The OR gate 27 generates a logical sum of the output S2 of the hold matrix circuit 23 and the output S3 of the determination circuit 26.

The output S4 of the OR gate 27 is
(I) When a failure occurs in the matching detection of the corresponding DUT (ii) When a failure is detected in the logical comparison of the corresponding DUT (iii) Asserted when the count value reaches the upper limit ( “1”).

  When the output S4 of the OR gate 27 is asserted ("1"), the comparison judgment by the logical comparator DC is stopped, and the output S1 of the logical comparator DC is fixed to "1".

  The NAND gate 28 generates a negative logical product of the write enable signal (/ WE), the chip enable signal (/ CE), and the output of the OR gate 27, and outputs it to the write enable terminal and the chip enable terminal of the DUT 1. . “/” Indicates inverted logic.

The above is the configuration of the test apparatus 2. Next, the operation and usage will be described.
The test apparatus 2 can be operated in any of the following plurality of modes, that is, the first to fourth flash hold modes when simultaneously testing a plurality of flash memories. Here, the case of the dynamic control mode (Match_Mode 1 = 0) will be described.

1. First flash hold mode The control signals used in this mode are shown below.
Match_Mode_Sel [0] = 0
Match_Mode_Sel [1] = 1
Match_Mode_Sel [2] = 1
Match_Mode_Sel [3] = 0

  In the first flash hold mode, subsequent rewriting is prohibited for a DUT that has already been programmed. Specifically, the pin of the R / B signal is set as a match detection target. A match signal indicating the result of match detection is loaded into the register 30 of the flash hold register 14 in response to the load command. In the first flash mode, the flash_hold signal indicates the result of match detection. The inhibit signal S2 generated by the hold matrix circuit 23 is asserted when the match detection of all the pins of the corresponding DUT is a pass. When the inhibition signal S2 is asserted, the operations of the plurality of logical comparators DC corresponding to the DUT are stopped. Further, by asserting the inhibit signal S2, the / WE signal and the / CE signal are masked by the NAND gate 28, and overwriting and erasing of the DUT 1 can be prohibited.

2. Second Flash Hold Mode Control signals used in this mode are shown below.
Match_Mode_Sel [0] = 0
Match_Mode_Sel [1] = 1
Match_Mode_Sel [2] = 0
Match_Mode_Sel [3] = 1

  In this mode, the stack_pass signal is held in the register 30 of the flash hold register 14. That is, the comparison result between the data read from the DUT and the expected value is held in the corresponding pin. If the read data is correct at all pins of a certain DUT, the inhibition signal S2 generated by the hold matrix circuit 23 is asserted, the comparison operation of the logical comparator DC is stopped, and the / CE signal and / WE signal Is masked.

  When the test is completed, the Hold_Flash_clear signal is asserted and the flash hold register 14 is cleared. As a result, the inhibit signal S2 is negated, and the next block can be erased.

3. Third Flash Hold Mode The third flash hold mode can implement the following functions in addition to the first flash hold mode.
After writing data to a certain DUT, when the match detection of that DUT is a failure, the flash counter 24 counts up. When the count value reaches the upper limit value, the hard fail signal S3 is asserted, the comparison operation of the logical comparator DC is stopped, and the / CE signal and / WE signal are masked. Further, clearing of the flash counter 24 is prohibited.

  When the output match_total of the logic gate 22 is asserted, that is, when the match detection is passed in all the DUTs, the Flash_Hold_clear signal and the FCCLEAR signal are asserted in preparation for the next address test, and the flash hold register 14 and the flash counter 24 To clear.

  In this mode, a DUT in which programming has not been completed within the maximum allowable number of retries can be rejected by a series of operations. This rejection is performed by asserting the inhibition signal S2 for all the logical comparators DC corresponding to the DUT. If the value of the flash counter 24 is read after the test is completed, it can be determined in which DUT a hard failure has occurred.

4). Fourth Flash Hold Mode In the fourth flash mode, the following functions can be realized in addition to the second flash hold mode.
In this mode, the flash counter 24 counts the number of erases for the corresponding DUT. When no pass determination is made by the maximum allowable number set by the upper limit value LIMIT, the hard fail signal S3 is asserted. As a result, the comparison by the logical comparator DC stops (always pass determination), and thereafter, the count-up of the flash counter 24 stops and keeps the value. Further, when the hard fail signal S3 is asserted, the clearing of the flash counter 24 is prohibited. Thereby, it is possible to reject the defective DUT and prevent the entire test time from being prolonged by the defective DUT.

The above is the operation of the test apparatus 2.
Thus, according to the test apparatus 2, the flash hold register 14 and the match hold selector 16 can be controlled in units of cycles by changing the value of Match_Mode_Sel [0: 3] by the pattern program. In other words, conditional branches based on match detection and conditional branches based on logical comparison can be flexibly programmed.
Furthermore, the number of retries based on match detection and the number of retries based on logical comparison can be flexibly set by the pattern program.

  It is assumed that the flash hold register 14 and the match hold selector 16 cannot perform program control (dynamic control) but only register control (static control). In this case, since the flash hold register 14 and the match hold selector 16 cannot be switched in the middle of one pattern program, the flash hold mode cannot be changed in the middle of the program. Therefore, it is necessary to divide the pattern into a plurality of pattern programs. On the other hand, according to the test apparatus 2 according to the embodiment, various modes can be switched with a single program.

5. Others Match_Mode_Sel [0] = 1
Match_Mode_Sel [1] = 0
Then, the match signal output from the match control circuit MC is selected by the match hold selector 16. That is, conditional branching based on the match signal can be performed.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  In the embodiments, the logic system in which “assert” is assigned to a high level and “negate” is assigned to a low level has been described as an example. However, those skilled in the art can understand that they may be inverted. In this case, an inverter or a logic gate having an inverting input may be used as appropriate.

  Although the case where the test apparatus 2 is a tester for flash memory has been described in the embodiment, the present invention is not limited to this. The test apparatus 2 may be a tester for testing other memories, or a tester for testing SOC or the like. Further, the state to be determined by the match detection process can be arbitrarily set without being limited to those described above, and these are also included in the scope of the present invention.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 1 ... DUT, CNT1 ... 1st control pattern signal, 2 ... Test apparatus, CNT2 ... 2nd control pattern signal, MC ... Match control circuit, DC ... Logic comparator, 10 ... Fail stack register, 12 ... Logic gate, 14 ... Flash hold register, 16 ... match hold selector, 20, 22 ... logic gate, 23 ... hold matrix circuit, 24 ... flash counter, 25 ... limit register, 26 ... determination circuit, 27 ... OR gate, 28 ... NAND gate, 30 ... Register, PG ... Pattern generator, 32 ... First AND gate, 34 ... Second AND gate, 36 ... First OR gate, 37 ... Third selector, 38 ... First selector, 40 ... Second selector, 42 ... Third AND gate, 44 ... 4th AND gate, 46 ... 2nd OR gate, 47 ... 6th selector, 48 The fourth selector, 50 ... fifth selector.

Claims (5)

A plurality of logical comparators, each provided for each pin of the device under test, each generating a comparison signal indicating a match or mismatch between the corresponding pin value and an expected value. When,
Each of the plurality of match control circuits provided for each of the pins generates a match signal indicating a match or mismatch between the corresponding pin value and the expected value when the match flag is asserted. A plurality of match control circuits;
A plurality of fail stack registers provided for each of the pins, each of which holds the comparison signal from the corresponding logical comparator;
A plurality of flash hold registers provided for each of the pins, each of which is a stack pass signal that is asserted when no failure has occurred in the past based on the output value of the corresponding fail stack register; Receiving a match signal from the corresponding match control circuit, holding one corresponding to the first pattern control signal generated in the execution cycle of the predetermined first control instruction described in the pattern program, and holding the match signal Multiple flash hold registers that output as
A plurality of match hold selectors provided for each of the pins, each of which receives the match signal from the corresponding match control circuit and the hold match signal from the corresponding flash hold register; A plurality of match hold selectors that output one as a pin match signal according to a second pattern control signal generated in an execution cycle of a predetermined second control instruction described in
A test apparatus comprising: The first pattern control signal includes first data asserted in a cycle for selecting the match signal and second data asserted in a cycle for selecting the stack path signal.
The flash hold register is
A first AND gate that generates a logical product of the first data and the match signal;
A second AND gate for generating a logical product of the second data and the stack path signal;
A first OR gate for generating a logical sum of output signals of the first AND gate and the second AND gate;
A register for holding the output of the first OR gate in response to a load signal asserted in an execution cycle of a load instruction described in a pattern program;
The test apparatus according to claim 1, comprising: The second pattern control signal includes third data asserted in a cycle for selecting the match signal, and fourth data asserted in a cycle for selecting the hold match signal,
The match hold selector
A third AND gate for generating a logical product of the third data and the match signal;
A fourth AND gate for generating a logical product of the fourth data and the hold match signal;
A second OR gate for generating a logical sum of output signals of the third AND gate and the fourth AND gate;
The test apparatus according to claim 1, comprising: The flash hold register is
Further receiving the match mode signal and the mode control signal stored in the register,
When the match mode signal is at the first level, one is held according to the pattern control signal, and when the match mode signal is at the second level, one is held according to the mode control signal. The test apparatus according to claim 1. The match hold selector
Further receiving the match mode signal and the mode control signal stored in the register,
When the match mode signal is at the first level, one corresponding to the pattern control signal is held, and when the match mode signal is at the second level, one corresponding to the mode control signal is output. The test apparatus according to claim 1.

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