JP2012100111A - Device and method for uninterruptible switching - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve uninterruptible switching in an OTN transmission device having no common clock, such as an intra-office clock.SOLUTION: In the present invention, signals of two lines branched into a plurality of transmission channels by a transmission side branching means are respectively subjected to clock reproduction and signal identification. Individual identified signals are respectively written in two buffers by using reproduced transmission clocks. A common clock is generated from the two reproduced transmission clocks. Two signal detection means respectively read the signals written in the buffers by using the common clock; recognize boundaries of the two signals; compare the boundaries of the two signals; adjust a differential delay between detected two signals; and switch the two read signals by using the common clock.

Description

  The present invention relates to an uninterruptible switching device and method, and more particularly to an uninterruptible switching device and method for performing uninterruptible switching in a network without a synchronous network such as OTN (Optical Transport Network).

  In an optical transmission system, there is an uninterruptible switching technique for electrical paths as a technique for improving the reliability of a layer 1 transmission apparatus. Non-instantaneous switching technology is a technique in which a signal is branched on the transmission side, the same signal is transmitted on multiple paths, and the delay difference of the signals transmitted on the multiple paths on the reception side is adjusted, and then 1 bit is selected by the selector. This is a technique for switching a route without disconnecting a signal by switching a failure or a plan by switching without omission (see, for example, Patent Document 1 and Non-Patent Document 1).

JP 2007-228282 A

Kawase et al. “Study of uninterrupted frame switching method in SDH network”, IEICE Transactions B-I, vol. J78-B-I, no. 12, pp. 764-772, December 1995.

  The conventional non-instantaneous switching technology is based on the assumption that SDH (Synchronous Digital Hierarchy) is used as a signal. A feature of SDH is that a common intra-office clock is prepared in a synchronous network, that is, in all telephone stations. The in-station clock is separately transmitted to a central office and is distributed to all telephone stations in a clock path network formed by a device different from the transmission device that is to be switched without interruption.

  FIG. 13 shows an example of a conventional uninterruptible switching device using a common clock.

The signal branched into two by the transmission side branching unit 10 is transmitted to the reception side device via the transmission path 1 and the transmission path 2. The transmitted signal is subjected to photoelectric conversion (not shown), and then clock recovery and data identification are performed in CDR (Clock and Data Recovery) units 21 ₁ and 21 ₂ . In order to distinguish the clock reproduced by the CDR units 21 ₁ and 21 ₂ from the intra-station clock, it is referred to as “transmission path clock” here. The identified data is transferred from the received clock to the in-station clock. Specifically, after data is written using a transmission path clock in a buffer using 2-port FIFOs 22 ₁ , 22 ₂ , the data is read using a local clock. On the transmission side, the transmission signal is generated using a common intra-office clock at all telephone stations, so that the transmission path clock and the intra-office clock have the same frequency on average.

The difference between the two is that the transmission line clock has slight delay fluctuations and frequency fluctuations due to temperature changes while being transmitted through an optical fiber or the like. These are called wander. When signals are transmitted through different paths, they are affected by different wanders. However, the signals transmitted through the transmission path 1 and the transmission path 2 are common to the transmission path clocks using the buffers 22 ₁ and 22 ₂ . By switching to the in-station clock, the influence of wander can be absorbed, and two systems of signals operating with the same clock can be obtained at the subsequent stage of the buffers 22 ₁ and 22 ₂ . Since the frame detection units 23 ₁ , 23 ₂ and the selection unit 25 of the buffer rear stages 22 ₁ , 22 ₂ all operate with a single intra-station clock, the selection unit does not lose 1 bit at the time of failure switching or plan switching. 25 can be switched.

  On the other hand, a standard called OTN (Optical Transport Network) has recently been used in transmission apparatuses. OTN is an international standard for optical transmission networks defined by ITU-T. Unlike SDH (Synchronous Digital Hierarchy), OTN does not have an internal clock. Therefore, in the transmission apparatus using OTN, the above-mentioned uninterruptible switching method cannot be applied as it is.

  Also, in the prior art, it is assumed that the service is provided after adjusting the delay difference between the multiple paths when setting the electrical path to enable switching without interruption, and the delay is adjusted dynamically during operation. It is not considered to do.

  The present invention has been made in view of the above points, and enables an uninterruptible switching in an OTN transmission apparatus that does not have a common clock such as an intra-station clock, and adjusts a delay dynamically to provide an uninterruptible service being provided. It is an object of the present invention to provide a non-instantaneous switching device and method capable of switching switching.

In order to solve the above problems, the present invention (Claim 1) is an uninterruptible switching device that selects and outputs one of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock regeneration / data identification means for performing clock recovery and signal identification for a plurality of signals branched into a plurality of transmission paths by the transmission side branching means,
A plurality of buffers for writing each signal output from the clock recovery / data identification means using the recovered transmission clock,
Common clock generating means for generating a common clock from a plurality of the transmission clocks recovered by the clock recovery / data identification means;
Frame detection means for recognizing a frame boundary of a signal read from the buffer using the common clock;
A delay difference detecting means for detecting a delay difference by comparing a frame boundary of the signal detected by the frame detecting means;
A delay difference adjusting means for adjusting a delay difference between a plurality of signals detected by the frame detecting means;
Selection means for switching a plurality of signals output from the frame detection means using the common clock.

The present invention (Claim 2) provides the common clock generating means according to Claim 1,
Clock switch means for selecting and outputting one of a plurality of input clocks;
Phase-locked loop means for outputting a signal in which the phase of the signal is synchronized based on the clock selected by the clock switch means.

Further, the present invention (Claim 3) provides the frame detection means according to Claim 1,
Means for reading a signal written in the buffer using the transmission clock;

The present invention (Claim 4) is an uninterruptible switching device that selects and outputs one of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock regeneration / data identification means for performing clock recovery and signal identification for a plurality of signals branched into a plurality of transmission paths by the transmission side branching means,
A plurality of buffers for writing each signal output from the clock recovery / data identification means using the recovered transmission clock,
A clock generation means for generating a read clock and a common clock for reading a signal transmitted from the buffer;
A plurality of frame detection means for recognizing a frame boundary of the signal read from the buffer using the read clock;
Delay difference adjusting means for dynamically adjusting the delay difference of the frames detected by the frame detecting means;
Selection means for switching a plurality of signals output from the frame detection means using the common clock.

Further, according to the present invention (Claim 5), the clock generation means of Claim 4
A plurality of clock switch means for selecting and outputting one of the plurality of input clocks;
A clock control / phase synchronization means for controlling a clock frequency based on an external clock control information from an input signal from the clock switch means;

  According to the present invention (Claim 6), the signal of Claims 1 to 5 is an OTN (Optical Transport Network) signal.

Further, the present invention (Claim 7) is an uninterruptible switching method for selecting and outputting one of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock recovery / data identification means;
Multiple buffers,
A common clock generating means;
A plurality of frame detection means;
A delay difference detection means;
A delay difference adjusting means;
A selection means;
In the non-instantaneous switching device having
The plurality of clock recovery / data identification means,
A plurality of signals branched into a plurality of transmission paths by the branching means on the transmission side, respectively, perform clock recovery and signal identification,
Write each signal output from the clock recovery / data identification means to each of the plurality of buffers using the recovered transmission clock,
The common clock generating means generates a common clock from the regenerated plurality of transmission clocks;
Each of the plurality of frame detection means recognizes a frame boundary of the signal read from the buffer using the common clock,
The delay difference detecting means detects a delay difference by comparing frame boundaries,
The delay difference adjusting means adjusts the delay difference by comparing a frame boundary of the detected signal,
The selection means switches a plurality of signals read using the common clock.

  The present invention (invention 8) reads out the signal written in the buffer by using the transmission clock in claim 7.

Further, the present invention (Claim 9) is an uninterruptible switching method for selecting and outputting one of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock recovery / data identification means;
Multiple buffers,
Clock generation means;
A plurality of frame detection means;
A delay difference adjusting means;
A selection means;
In the non-instantaneous switching device having
The plurality of clock recovery / data identification means respectively perform a clock recovery and signal identification for a plurality of signals branched to a plurality of transmission paths by the transmission side branching means,
Write the respective signals output from the clock recovery / data identification means to the plurality of buffers using the recovered transmission clock,
The clock generation means generates a read clock and a common clock for reading a signal transmitted from the buffer;
The frame detection means recognizes a frame boundary of the signal read from the buffer using the read clock,
The delay difference adjusting means dynamically adjusts the delay difference of the frame;
The selection means switches a plurality of signals read using the common clock.

  In the present invention (claim 10), the signals of claims 7 to 9 are OTN (Optical Transport Network) signals.

  As described above, according to the present invention, a common clock is generated using a transmission path clock regenerated from a signal transmitted through a plurality of paths, and switching without interruption is performed by using the common clock. Is possible. Since one clock is interrupted at the time of failure switching, it is possible to shift from the interrupted clock to the other normal clock without discontinuity in phase or frequency.

It is an example of composition of an uninterruptible switching device in a 1st embodiment of the present invention. It is a block diagram of the common clock generation part in the 1st Embodiment of this invention. It is an example of an output of the common clock generation part in the 1st Embodiment of this invention. It is a structural example of the uninterruptible switching device in the 2nd Embodiment of this invention. It is a structural example of the uninterruptible switching device in the 3rd Embodiment of this invention. It is a structural example of the clock generation part in the 3rd Embodiment of this invention. It is an example of the delay adjustment in the 3rd Embodiment of this invention. It is an operation mode of the dynamic delay control system in the third embodiment of the present invention. It is a flowchart of the dynamic delay adjustment in the 3rd Embodiment of this invention. It is a figure which shows the time-dependent change of the clock output in the 3rd Embodiment of this invention. It is a structural example of the uninterruptible switching device in the 4th Embodiment of this invention. It is a structural example of the clock generation part in the 4th Embodiment of this invention. It is an example of the uninterruptible switching device using the common clock of the prior art.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 shows a configuration example of an uninterruptible switching device according to a first embodiment of the present invention.

  In this figure, the same components as those in FIG.

The uninterruptible switching device shown in FIG. 1 includes a common clock generation unit 30 in the configuration of FIG. 12, generates a common clock by the common clock generation unit 30, and the wander is absorbed by the FIFOs 22 ₁ and 22 ₂ . The common clock generation unit 30 generates a common clock from a plurality of transmission path clocks regenerated by the CDR units 21 ₁ and 21 ₂ .

The transmitted signal is written to the buffers 22 ₁ and 22 ₂ by the transmission path clock, and is read from the buffers 22 ₁ and 22 ₂ by the common clock 26, so that the clocks of the two systems of signals are shared. Since the buffer ₂₂ 1, 22 ₂ from the subsequent frame detecting section ₂₃ 1, 23 ₂ and the selection unit 25 is operating in the common clock, the delay difference of two signals is adjusted using a buffer ₂₂ 1, 22 ₂ Later, it is possible to switch signals without interruption.

  FIG. 2 shows a configuration example of the common clock generation unit in the first embodiment of the present invention.

  The common clock generation unit 30 includes a clock switch unit 31 and a phase locked loop unit 32. The clock switch unit 31 receives clocks 1 and 2 as transmission path clocks. The clock switch unit 31 selects and outputs either clock 1 or clock 2. The output signal is input to the phase locked loop unit 32.

  FIG. 3 shows the output of the common clock generation unit in the first embodiment of the present invention.

  FIG. 2A shows a case where two clocks are input to the common clock generation unit 30 and the clock 1 is selected. The common clock output follows the clock 1.

  On the other hand, FIG. 4B shows a case where two clocks are input to the common clock generation unit 30 and the clock 2 is selected. In this case, the common clock output follows the clock 2.

  FIG. 2C shows a state in which two clocks are input to the common clock generation unit 30 and the clock selected at time T0 is switched from clock 1 to clock 2. Until the time T0, the common clock output follows the clock 1, but at the time T0, the input to the phase locked loop unit is instantaneously switched from the clock 1 to the clock 2 (or with a short interruption time). The common clock output gradually shifts from clock 1 to clock 2 in accordance with the time constant of the unit. At the time T1, the common clock output completely follows the clock 2. Although not shown, the same operation is performed when the clock 2 is switched to the clock 1.

  FIG. 4D shows a case where two clocks are input to the common clock generation unit 30 and the clock 1 selected at time T2 is cut off. The clock switch unit 31 detects that the clock 1 selected at the time T2 is cut off (or is notified of the cut off from the block located in the preceding stage), and forcibly selects the clock of the clock switch unit 31 as the clock 1 To clock 2 Accordingly, since the input of the phase locked loop unit 32 is switched, the common clock output gradually shifts from the clock 1 to the clock 2 according to the time constant of the phase locked loop unit 32. At time T3, the common clock output completely follows the clock 2.

[Second Embodiment]
FIG. 4 shows a configuration example of an uninterruptible switching device according to the second embodiment of the present invention. In the figure, the same components as those in FIG. In the present embodiment, a clock is generated by the common clock generation unit 40, and the wander is absorbed by the selection unit 25.

In the present embodiment, the common clock generator 40 is provided in the same manner as in the first embodiment, except that the read clocks of the buffers (FIFOs) 22 ₁ and 22 ₂ are the transmission path clocks. It is a point using. The selection unit 25 operates with a common clock, and the switching from the transmission path clock to the common clock is performed by the selection unit 25.

  As a configuration example of the common clock generation unit 40, the one shown in the first embodiment can be used.

[Third Embodiment]
In the present embodiment, an uninterruptible switching device that performs dynamic delay adjustment will be described.

  FIG. 5 shows a configuration example of the uninterruptible switching device according to the third embodiment of the present invention. In the figure, the same components as those in FIG.

The uninterruptible switching device according to the present embodiment is characterized by a configuration capable of dynamic delay adjustment. For this purpose, a clock generation unit 50 is provided. In this embodiment, the clock generator 50 generates a clock, and the wander is absorbed by the buffers (FIFOs) 22 ₁ and 22 ₂ .

The clock generation unit 50 receives clocks 1 and 2 as transmission path clocks, and outputs a read clock 1, a read clock 2 and a common clock. Read clock 1 is used when reading a signal which has been transmitted through the transmission line 1 from the buffer (FIFO) 22 _1. Read clock 2 is used when reading the signal transmitted to the transmission path 2 from the buffer (FIFO) 22 _2. The common clock is used for the operation of the selection unit 25.

  FIG. 6 shows a configuration example of the clock generation unit in the third embodiment of the present invention.

The clock generation unit 50 includes switches 51 ₁ and 51 ₂ , two clock control / PLL (phase synchronization) units 52 ₁ and 52 ₂ , a clock selection unit 53, and a PLL unit 54.

The signals transmitted through the transmission lines are clock-reproduced and identified by the CDR units 21 ₁ and 21 ₂ , respectively. Each signal is written in buffers (FIFO) 22 ₁ and 22 ₂ with clock 1 and clock 2 which are transmission path clocks, respectively. It is input to the clock 1 and clock 2 switch 51 ₁ and the switch 51 ₂ is branched respectively. Switch 51 ₁ and the switch 51 ₂ outputs each selected clock 1 or clock 2. The output clock is input to the clock control / PLL units 52 ₁ and 52 ₂ , and the clock frequency is controlled and output when adjusting the delay.

Further, it is possible to shift from one clock without skipping phase and frequency to the other clocks when the clock is switched by the switch 51 ₁ or switch 51 _2. The output of the clock control / PLL section ₅₂ 1, 52 ₂ is used as a read clock for the buffer. The output of the clock control / PLL section ₅₂ 1, 52 ₂ is also input to the clock selector 53. The clock selection unit 53 selects one of the input clocks and inputs the selected clock to the PLL unit 54.

  A PLL unit 54 is provided after the clock selection unit 53, and the clock selected by the clock selection unit 53 is input. When the clock selection unit 53 switches the clock selection, the PLL unit 54 can shift from one clock to the other without jumping in phase or frequency.

  Here, dynamic delay adjustment will be described.

  FIG. 7 shows a configuration example of a delay adjustment unit (clock control / PLL unit) in the third embodiment of the present invention.

  7, the interface corresponds to the CDR unit 21 in FIG. 6, the FIFO corresponds to the FIFO 22 in FIG. 6, and the clock adjustment unit corresponds to the CLK control / PLL unit 52 in FIG. An interface (IF) unit 21 regenerates the clock of the input signal. The signal is input to the FIFO 22, and the recovered clock is used as a write clock for the FIFO 22 and input to the clock adjustment unit 52. The clock adjustment unit 52 changes the frequency of the clock based on external delay control information.

  For example, as shown in FIG. 7A, when the clock frequency is intentionally lowered by 1 ppm in a certain time range, the delay time increases because the read clock of the FIFO 22 is slower than the write clock. As shown in FIG. 7B, when the clock frequency is intentionally increased by 1 ppm within a certain time range, the delay time decreases because the read clock of the FIFO 22 is earlier than the write clock. The change of the clock frequency changes the frequency continuously or discretely within a range that does not affect the client signal. The clock frequency should be within the ODU clock deviation specified in Recommendation G.709. In addition, the FIFO 22 is prevented from overflowing or underflowing by intentionally changing the clock. The intentional amount of change in the clock frequency can take any value within a range that does not affect the client signal. If the amount of change is increased, the desired delay time can be set earlier.

  Next, the operation of the non-instantaneous switching method based on dynamic delay control will be described. As shown in FIG. 8, there are four phases in the operation of the method. The horizontal axis represents time, and the vertical axis represents the delay difference between the two signals.

• “No signal received” state: Time to time T0. State where two signals are not received or only one is received;
"Delay difference unadjusted" state: Time from time T0 to time T1. A state where two signals are received and the delay difference is not adjusted;
"Delay difference adjustment" state: Time from time T1 to time T2. In the middle of receiving two signals and adjusting the delay difference;
・ "Delay difference adjustment complete" state: After time T2. A state in which two systems of signals have been received and the delay difference adjustment has been completed;
When delay difference adjustment is complete, failure switching triggered by a failure such as fiber breakage or planned switching that saves the signal to another path in advance can be switched without interruption without bit loss. .

  FIG. 9 is a flowchart of dynamic delay adjustment in the third embodiment of the present invention.

  When the delay adjusting unit 52 receives two signals (step 101, Yes), the delay adjusting unit 52 detects the delay difference (step 102) and adjusts the delay difference (step 103). The processing in step 102 is repeated until the delay difference between the two signals becomes zero by the delay difference adjustment (step 104, No). When the delay difference becomes zero (step 104, Yes), the delay difference adjustment is completed. As a result (step 105), an operator instruction or signal disconnection is detected and switched (step 106).

  FIG. 10 schematically shows changes in the clock frequency at each stage. In the state where two systems of signals (hereinafter referred to as the first system signal and the second system signal) are input to the uninterruptible switching device shown in FIG. An example of switching to the second system signal will be described. In the illustrated example, it is assumed that the transmission path of the first system signal is shorter than the transmission path of the second system signal. In FIG. 10, b indicates the frequency of the clock 1, c indicates the frequency of the clock 2, and a indicates the frequency of the common clock. Further, when the CLK control / PLL unit 52 in FIG. 6 is operating, the clock frequency is also shown.

In the “signal not received” state (to time T0) shown in FIG. 10, only the first system signal is received. For this reason, the common clock (FIG. 10A) follows the clock 1 (FIG. 10B). This condition, SW51 ₁ of Figure 6 selects the clock 1 is realized by also selecting the clock 1 side CLK_SEL53.

In the “delay difference unadjusted” state (time T0 to T1) shown in FIG. 10, the second system signal is received and there are two transmission path clocks. The common clock (FIG. 10A) continues to follow the clock 1 (FIG. 10B). The clock 2 (FIG. 10C) is different from the clock 1 because it is affected by the wander of the transmission path through which the second signal is transmitted. However, since the clocks originally have the same frequency, the average frequency is the same. SW51 ₂ in FIG. 6 selects the clock 2.

In the “delay difference adjustment” state shown in FIG. 10 (from time T1 to time T2), the fact that the delay time of the first system signal is shorter than that of the second system signal is based on the frame detection results of the two system frame detection units. Judging and adjusting the delay time of the first system signal by increasing the amount of FIFO used. The CLK control / PLL section 52 ₁ of FIG. 6 Clock 1 is a line clock (FIG. 10 (b)) is inputted, a frequency controlled clock 1 (FIG. 10 (d)) is output. The clock 1 (FIG. 10B) is used as a FIFO write clock, and the frequency-controlled clock 1 (FIG. 10D) is used as a FIFO read clock. In the case of FIG. 10, since the frequency of the frequency-controlled clock 1 (FIG. 10 (d)) is intentionally lowered, the FIFO usage will gradually increase. When the delay difference between the first system signal and the second system signal becomes 0, the frequency control is terminated (time T2). Note that the common clock output during frequency control follows the clock 1 during frequency control because the first system signal is used as the active system (FIG. 10E). That is, CLK_SEL 53 in FIG. 6 selects the clock 1 side.

In the “delay difference adjustment complete” state (time T2 to T3) shown in FIG. 10, the FIFO read clock is shared. Although read clock 2 shown in FIG. 6 is at the stage of the time T2 is used line clock 2, which the read clock 2 by switching the SW51 ₂ of Figure 6 the clock 1 so as to follow the clock 1 ( FIG. 10 (f)). By the time constant with the CLK controller / PLL section 52 ₂ continue to follow the gradual clock 1 as illustrated in FIG. 10 (f). Therefore, after the read clock 2 completely follows the clock 1, the first signal FIFO is the write clock 1 and the read clock is the clock 1, and the second signal FIFO is the write clock 2. Thus, the read clock becomes clock 1 and the read clocks of both systems are shared. In FIG. 10, the read clock is shared after the delay difference adjustment is completed, but the clock may be shared before the delay difference adjustment.

Thereafter, when the signal of the first system is interrupted at time T3, DATA_SEL 25 in FIG. 6 is switched from the first system side to the second system side, and the signal is switched from the first system to the second system without instantaneous interruption. Since the clock 1 is a line clock Concomitantly also disconnected, replaced from state SW51 ₂ has selected the clock 1 of FIG. 6 detects that the the state of selecting the clock 2. Similarly, the CLK_SEL 53 in FIG. 6 changes from the state in which the clock 1 side is selected to the state in which the clock 2 side is selected. Accordingly, the read clock 2 gradually follows from the clock 1 to the clock 2 after the time T3 as shown in FIG. 10 (FIG. 10 (g)). In this state, the common clock follows FIG. 10 (g).

[Fourth Embodiment]
Also in this embodiment, dynamic delay adjustment is performed.

  FIG. 11 shows a configuration example of an uninterruptible switching device according to the fourth embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In the present embodiment, a case where a common clock is generated by the common clock generation unit and clock control is performed is shown. The wander is absorbed by a FIFO (not shown) in the selection unit 25.

In the present embodiment, clock adjustment units 60 ₁ and 60 ₂ and a clock generation unit 70 are provided to perform dynamic delay adjustment.

Clock adjusting portion 60 ₁ of the transmission line 1 side receives a clock 1 from the CDR unit 21 _1, and outputs the control the frequency of the clock 1 based on the clock control information from outside. Clock adjusting portion 60 ₂ of the same transmitted channel 2 side receives the clock 2 from the CDR unit 21 _2, and outputs the control the frequency of the clock 2 based on the clock control information from outside.

The clocks output from the clock adjusting units 60 ₁ and 60 ₂ are used as read clocks for the buffers (FIFOs) 22 ₁ and 22 ₂ on the transmission path 1 side and the transmission path 2 side, respectively. Outputs from the clock adjustment units 60 ₁ and 60 ₂ are input to the clock generation unit 70.

  The clock generation unit 70 outputs a common clock, and the clock is used for the operation of the selection unit 25 and the like.

  FIG. 12 shows the configuration of the clock generator in the fourth embodiment of the present invention.

  The clock generation unit 70 includes a clock switch unit 71 and a PLL unit 72.

  The clock switch unit follows the selection setting when two signals are input. Further, when one of the signals of two systems is input, if one of them is disconnected, if the unselected one is disconnected, the selected one is switched to the other if it is disconnected.

  Thereby, when the clock is switched by the clock switch unit 71, it is possible to shift from one clock to the other without jumping in phase or frequency.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

10 Branching section 21 CDR section 22 Buffer (FIFO)
23 frame detection unit 24 delay difference detection unit 25 selection unit 30 common clock generation unit 31 clock switch unit 32 phase locked loop unit 40 common clock generation unit 50 clock generation unit 51 switch 52 clock control / PLL unit 53 clock selection unit 54 PLL ( Phase synchronization) unit 70 Clock generation unit 71 Clock switch unit 72 Phase synchronization loop unit

Claims (10)

An uninterruptible switching device that selects and outputs either of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock regeneration / data identification means for performing clock recovery and signal identification for a plurality of signals branched into a plurality of transmission paths by the transmission side branching means,
A plurality of buffers for writing each signal output from the clock recovery / data identification means using the recovered transmission clock,
Common clock generating means for generating a common clock from a plurality of the transmission clocks recovered by the clock recovery / data identification means;
Frame detection means for recognizing a frame boundary of a signal read from the buffer using the common clock;
A delay difference detecting means for detecting a delay difference by comparing a frame boundary of the signal detected by the frame detecting means;
A delay difference adjusting means for adjusting a delay difference between a plurality of signals detected by the frame detecting means;
Selection means for switching a plurality of signals output from the frame detection means using the common clock;
A non-instantaneous switching device characterized by comprising: The common clock generation means includes
Clock switch means for selecting and outputting one of a plurality of input clocks;
Phase-locked loop means for outputting a signal whose phase is synchronized based on the clock selected by the clock switch means;
2. The uninterruptible switching device according to claim 1, comprising: The frame detection means includes
2. The uninterruptible switching device according to claim 1, further comprising means for reading a signal written in the buffer using the transmission clock. An uninterruptible switching device that selects and outputs either of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock regeneration / data identification means for performing clock recovery and signal identification for a plurality of signals branched into a plurality of transmission paths by the transmission side branching means,
A plurality of buffers for writing each signal output from the clock recovery / data identification means using the recovered transmission clock,
A clock generation means for generating a read clock and a common clock for reading a signal transmitted from the buffer;
A plurality of frame detection means for recognizing a frame boundary of the signal read from the buffer using the read clock;
Delay difference adjusting means for dynamically adjusting the delay difference of the frames detected by the frame detecting means;
Selection means for switching a plurality of signals output from the frame detection means using the common clock;
A non-instantaneous switching device characterized by comprising: The clock generation means includes
A plurality of clock switch means for selecting and outputting one of the plurality of input clocks;
Clock control / phase synchronization means for controlling the clock frequency based on the clock control information from the outside, the input signal from the clock switch means,
The uninterruptible switching device according to claim 4. The uninterruptible switching device according to any one of claims 1 to 5, wherein the signal is an OTN (Optical Transport Network) signal. A non-instantaneous switching method for selecting and outputting either of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock recovery / data identification means;
Multiple buffers,
A common clock generating means;
A plurality of frame detection means;
A delay difference detection means;
A delay difference adjusting means;
A selection means;
In the non-instantaneous switching device having
The plurality of clock recovery / data identification means,
A plurality of signals branched into a plurality of transmission paths by the branching means on the transmission side, respectively, perform clock recovery and signal identification,
Write each signal output from the clock recovery / data identification means to each of the plurality of buffers using the recovered transmission clock,
The common clock generating means generates a common clock from the regenerated plurality of transmission clocks;
Each of the plurality of frame detection means recognizes a frame boundary of the signal read from the buffer using the common clock,
The delay difference detecting means detects a delay difference by comparing frame boundaries,
The delay difference adjusting means adjusts the delay difference by comparing a frame boundary of the detected signal,
The non-instantaneous switching method, wherein the selection unit switches a plurality of signals read using the common clock. The method for switching without interruption according to claim 7, wherein a signal written in the buffer is read using the transmission clock. A non-instantaneous switching method for selecting and outputting either of signals transmitted through a plurality of transmission paths,
On the receiving side,
A plurality of clock recovery / data identification means;
Multiple buffers,
Clock generation means;
A plurality of frame detection means;
A delay difference adjusting means;
A selection means;
In the non-instantaneous switching device having
The plurality of clock recovery / data identification means respectively perform a clock recovery and signal identification for a plurality of signals branched to a plurality of transmission paths by the transmission side branching means,
Write the respective signals output from the clock recovery / data identification means to the plurality of buffers using the recovered transmission clock,
The clock generation means generates a read clock and a common clock for reading a signal transmitted from the buffer;
The frame detection means recognizes a frame boundary of the signal read from the buffer using the read clock,
The delay difference adjusting means dynamically adjusts the delay difference of the frame;
The non-instantaneous switching method, wherein the selection unit switches a plurality of signals read using the common clock. The non-instantaneous switching method according to any one of claims 7 to 9, wherein the signal is an OTN (Optical Transport Network) signal.

Images