JP2012098772A - Digital output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which does not malfunction due to noise and can supply current to a capacitive load, thereby solving a problem in which a digital output device, which detects a value of the current flowing through a load and, if an overcurrent flows, turns a switch off and cuts off the current flowing through the load, malfunctions due to noise and the like and, for the capacitive load, incorrectly recognizes a rush current as an overcurrent to disable current supply to the load.SOLUTION: A digital output device detects overcurrent flowing for a given period of time, forcefully cuts off a current supply to a load by using a current stopping part, and when the overcurrent does not flow, releases the current stopping part. Furthermore, when the number of times the overcurrent flows for the given period of time reaches a predetermined number of times, the device stops the release of the current stopping part. This prevents malfunction due to noise and can supply current to a capacitive load.

Description

  The present invention relates to a digital output device that supplies power to a load and stops supplying current to the load when an overcurrent flows, and is particularly suitable for a functional safety application that requires high reliability and high availability. The present invention relates to a digital output device.

  FIG. 6 shows a configuration of a digital output device that controls current supply to the load. The load includes various devices such as a field device that detects a process amount such as a flow rate and pressure and operates a process such as a valve.

  In FIG. 6, reference numeral 10 denotes a digital output device which supplies current to a load 20 such as a field device, and stops supplying current in the case of an abnormality. The digital output device 10 includes an overcurrent detection unit 11, a latch 12, a switch control unit 13, a switch 14, and a resistor 15.

  A power source 21 is connected between terminals 16 and 19, and a load 20 is connected between terminals 17 and 18. The output current of the power source 21 is supplied to the load 20 via the overcurrent detection unit 11 and the switch 14. The switch control unit 13 controls on / off of the switch 14 based on the input control signal. When the switch 14 is turned on, a current is supplied to the load 20, and when the switch 14 is turned off, the current supply to the load 20 is stopped.

  When a failure such as a short circuit occurs in the load 20, an excessive current flows through the load 20, which may cause burnout of the power supply 21 or abnormalities in other devices. For this reason, the digital output device 10 monitors the current flowing through the load 20 and immediately stops supplying the current to the load 20 when an excessive current flows. Hereinafter, the operation of the digital output device 10 will be described. The switch 14 is turned on when the input signal is at a high level and turned off when the signal is at a low level. The switch 14 is controlled to be turned on by the switch control unit 13.

  The output of the overcurrent detection unit 11 is input to the clock terminal of the latch 12, and the output (high level) of the switch control unit 13 is input to the data terminal D. The output of the latch 12 is assumed to be open drain.

  The overcurrent detection unit 11 monitors the current flowing through the load 20 and maintains the output at a low level when the current supplied to the load 20 is normal.

  When the current flowing through the load 20 exceeds a predetermined current threshold, the overcurrent detection unit 11 changes its output from a low level to a high level. The latch 12 latches the output (high level) of the switch control unit 13 at the rising edge of the output of the overcurrent detection unit 11. For this reason, the output is turned on, and the input signal of the switch 14 becomes a low level regardless of the output level of the switch control unit 13. The switch 14 is turned off, and the current supply to the load 20 is stopped.

  The maintenance staff inputs a clear signal to the latch 12 after removing the cause of the overcurrent. The latch 12 is cleared by this clear signal, and its output is turned off. For this reason, the current supply to the load 20 can be controlled by the switch controller 13.

  In Patent Document 1, the current detection unit 101 and the voltage detection unit 102 detect the current value flowing through the switch and the voltage value output to the device, perform diagnosis using the voltage value and the current value, A digital output device for detecting whether or not there is an influence on other devices when switching between is described.

JP 2006-209618 A

However, such a digital output device has the following problems.
In the digital output device of FIG. 6, if the overcurrent detection unit 11 erroneously detects that an overcurrent has flowed due to the influence of external noise or the like, the latch 12 is set, the switch 14 is turned off, and no current is supplied to the load 20. As a result, the operation stops. Moreover, in order to cancel this, there also existed a subject that the maintenance person had to input the clear signal manually and to clear the latch 12. FIG.

  When the load 20 is a capacitive load, a large inrush current flows when the switch 14 is turned on. For this reason, the overcurrent detection unit 11 mistakenly recognizes this inrush current as an overcurrent, and the latch 12 is set and the switch 14 is turned off. Therefore, there is a problem that current cannot be supplied to the load 20.

  This will be described with reference to FIG. FIG. 7A shows the state of the switch 14, and FIG. 7B shows a change in current flowing through the load 20. When the switch 14 is turned on at time T1, a large inrush current flows through the load 20 as shown in (B), and exceeds the current threshold of the overcurrent detection unit 11 at time T2. For this reason, the latch 12 is set, the switch 14 is turned off, and the current supply to the load 20 is stopped.

  For this reason, in order to supply a current to the capacitive load 20, the current threshold of the overcurrent detection unit 11 must be made larger than the inrush current. However, if the current threshold is increased, the overcurrent detection sensitivity decreases, so the load There is also a problem that an excessive current flows through 20, causing a failure of the load 20 or the power source 21, and adversely affecting other devices.

  An object of the present invention is to realize a digital output device that is not affected by noise and can supply a current even with a capacitive load.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a digital output device that supplies current to a load and stops supplying current to the load when an overcurrent flows,
An overcurrent detector that monitors the current flowing through the load and detects that an overcurrent has flowed;
When the output signal of the overcurrent detection unit is input and it is detected that the overcurrent has flowed for a predetermined time, a current stop unit that stops the current supply to the load;
When the output signal of the overcurrent detector is input and no overcurrent flows, the current supply stop of the current stop unit is canceled and the number of times the overcurrent has flowed for a predetermined time is counted. A stop release signal generator for preventing the current supply stop of the current stop unit from being released when the numerical value reaches a predetermined number of times;
It is equipped with. There is no malfunction due to noise or the like, and current can be supplied to the capacitive load.

The invention according to claim 2 is the invention according to claim 1,
The current stop part,
A time measuring unit that receives an output signal of the overcurrent detection unit and detects that the overcurrent has flowed for a predetermined time; and
A current stop signal generator that is set by the output signal of the time measuring unit and outputs a signal for forcibly stopping the current supplied to the load; and
It consists of Configuration is simplified.

The invention according to claim 3 is the invention according to claim 1 or 2,
The stop cancellation signal generation unit,
A signal indicating that the overcurrent has flowed for a predetermined time is input, the number of times of this signal is counted, and a counter that outputs a signal when the predetermined number of times is reached;
The output signal of the overcurrent detection unit and the output signal of the counting unit are input, and when the overcurrent has not occurred, a signal for canceling the current supply stop of the current stop unit is generated, and the counting unit When the output signal is input, a signal generator that does not generate a signal for canceling the current supply stop,
It consists of Configuration is simplified.

The present invention has the following effects.
According to the first, second, and third aspects of the invention, when the overcurrent continues for a predetermined time, the current supply to the load is stopped, and when the overcurrent disappears, the current supply stop is canceled, The number of times that the overcurrent has continued for a predetermined time is counted, and the current supply stoppage is not canceled when this number reaches the predetermined number.

  Since the current supply is not stopped until the overcurrent continues for a predetermined time, even if an overcurrent signal is output for an extremely short time due to noise or the like, there is an effect that the current supply to the load is not stopped.

  In addition, the current supply to the load is stopped when the overcurrent continues for a predetermined time, and the current stop is canceled when the overcurrent disappears. Therefore, the current is also supplied to the capacitive load through which the inrush current flows at the start-up. There is also an effect of being able to.

  Furthermore, since the current supply stoppage is not canceled when the number of times that the overcurrent has flowed for a predetermined time reaches the predetermined number of times, in the case of an overcurrent due to a permanent failure of the load, the current to the load There is also an effect that the supply can be stopped.

It is the block diagram which showed one Example of this invention. It is a characteristic view which shows operation | movement of the Example of FIG. It is a characteristic view which shows operation | movement of the Example of FIG. It is a characteristic view which shows operation | movement of the Example of FIG. It is a characteristic view which shows operation | movement of the Example of FIG. It is a block diagram of the conventional digital output device. It is a characteristic view when a capacitive load is connected.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital output device according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 6, and description is abbreviate | omitted. Further, it is assumed that the switch control unit 13 outputs a signal (high level) for turning on the switch 14.

  In FIG. 1, reference numeral 30 denotes a digital output device, which includes an overcurrent detection unit 11, a current stop unit 31, a stop release signal generation unit 32, a switch control unit 13, a switch 14, and a resistor 15. The current stop unit 31 includes a clock generation unit 33, a counter 34, and a latch 12. The stop release signal generation unit 32 includes a signal generation unit 35 and a counting unit 36. A power source 21 is connected between terminals 16 and 19, and a load 20 is connected between terminals 17 and 18.

  The output current of the power source 21 is supplied to the load 20 via the overcurrent detection unit 11 and the switch 14. The overcurrent detection unit 11 monitors the current flowing through the load 20, and when the current exceeds a predetermined current threshold, the output is shifted to a high level. This predetermined current threshold is set to a value somewhat larger than the maximum current value that flows when the load 20 is normal.

  The output clock of the clock generator 33 is input to the clock terminal of the counter 34, and the output signal of the overcurrent detector 11 is input to the clock enable EN of the counter 34. The counter 34 counts the clock input to the clock terminal when the output signal of the overcurrent detection unit 11 becomes high level, and sets the output signal output from the output terminal Q to high level when the count value reaches a predetermined value. It is assumed that the count value is returned to 0 at the next rising edge of the output clock.

  The counter 34 corresponds to a time measuring unit and detects that an overcurrent has flowed for a predetermined time. The predetermined time is set to be slightly longer than the time during which the output signal is maintained at a high level when the overcurrent detection unit 11 malfunctions due to noise.

  An output signal of the counter 34 is input to the clock terminal of the latch 12, and a signal for controlling the switch 14 output from the switch control unit 13 is input to the data terminal D. The latch 12 latches the signal applied to the data terminal D at the rising edge of the clock (output signal of the counter 34) input to the clock terminal. The latch 12 corresponds to a current stop signal generator, and outputs a signal for forcibly stopping the current supplied to the load.

  The output terminal Q of the latch 12 and the output terminal of the switch control unit 13 are connected and pulled up by the resistor 15. The switch 14 is controlled by the output signals of the latch 12 and the switch control unit 13 and is turned on when these signals are at a high level. Further, since the latch 12 has an open drain output, when the output signal of the counter 34 rises, the output of the latch 12 is turned on. For this reason, regardless of the level of the output signal of the switch control unit 13, the signal input to the switch 14 becomes low level, the switch 14 is turned off, and the current supply to the load 20 is stopped.

  The output signal of the overcurrent detection unit 11 is input to the signal generation unit 35. The signal generator 35 outputs a clear signal to the counter 34 and the clear terminal CLR of the latch 12 when the output signal of the overcurrent detector 11 becomes low level (not overcurrent). For this reason, the count value of the counter becomes 0, and the output of the latch 12 is turned off. Since the switch 14 is controlled by the output signal of the switch control unit 13, the switch 14 is turned on and a current is supplied to the load 20. That is, the signal generator 35 outputs a signal for canceling the stop of the current supply to the load 20.

  The output signal of the counter 34 is input to the counting unit 36. The counter 36 counts the rising edge of the output signal of the counter 34 and outputs a signal to the signal generator 35 when the count value exceeds a predetermined value. The signal generator 35 stops clearing the latch 12 when the output signal of the counter 36 is input. Further, when a clear signal is input from the outside, the counter 36 outputs a signal to the signal generator 35, clears the latch 12, and sets its count value to zero. That is, when the number of times counted by the counting unit 36 reaches a predetermined number, a signal is output to the signal generating unit 35 so as not to cancel the current supply stop to the load 20.

  Next, the operation of this embodiment will be described in detail with reference to the drawings. It is assumed that the output signal of the counter 34 becomes high when the count value reaches 7, and the count value returns to 0 at the next rising edge of the clock.

  FIG. 2 is a characteristic diagram showing an operation when the pulse width of the output signal of the overcurrent detector 11 is shorter than the time until the output signal of the counter 34 becomes high level. 2, (A) is the waveform of the output clock of the clock generator 33, (B) is the waveform of the output signal of the overcurrent detector 11, (C) is the count value of the counter 34, and (D) is the counter 34 of the counter 34. The waveform of the output signal, (E) is the output of the latch 12, and (F) is the state of the switch 14.

  When the output signal of the overcurrent detection unit 11 becomes high level at time T10, the count value of the counter 34 increases from the next rising edge T11 of the output clock. When the output signal of the overcurrent detection unit 11 becomes low level at time T12, the counter 34 is cleared by the output signal of the signal generation unit 35, and the count value returns to zero. Since the maximum value of the count value of the counter 34 is 3, the output signal of the counter 34 does not become high level. Therefore, the output of the latch 12 is not turned on as shown in (E), and the switch 14 is kept on as shown in (F).

  Thus, when the pulse width of the output signal of the overcurrent detection unit 11 is narrow, the switch 14 does not turn off. For this reason, even if the overcurrent detection unit 11 malfunctions due to noise or the like, the current supply to the load 20 is not interrupted.

  FIG. 3 shows an example in which the pulse width of the output signal of the overcurrent detection unit 11 is slightly longer than the time during which the output signal of the counter 34 is at a high level.

  3, (A) to (F) are the output clock waveform of the clock generation unit 33, the waveform of the output signal of the overcurrent detection unit 11, the count value of the counter 34, and the output signal of the counter 34, as in FIG. , The output state of the latch 12, and the state of the switch 14.

  When the output signal of the overcurrent detection unit 11 becomes high level at time T20, the counter 34 starts counting. When the count value of the counter 34 becomes 7 at time T21, the output signal becomes high level. For this reason, the output of the latch 12 is turned on and the switch 14 is turned off.

  When the switch 14 is turned off, no overcurrent flows, and the output signal of the overcurrent detection unit 11 becomes a low level. Therefore, at time T22, the counter 34 and the latch 12 are cleared by the output of the signal generator 35, and the switch 14 is turned on again. Since the cause of the overcurrent has not been eliminated, the output signal of the overcurrent detection unit 11 becomes a high level again, and the counter 34 starts counting from 0.

  At time T23, the cause of the overcurrent is eliminated, and the output signal of the overcurrent detection unit 11 becomes low level. The counter 34 is cleared to 0 by the signal generator 35.

  In this example, the switch 14 is turned off between times T21 and T22, and the current is temporarily not supplied to the load 20. However, when the cause of the overcurrent is eliminated, the original state is automatically restored.

  FIG. 4 shows an example in which the load 20 is a capacitive load and an inrush current flows. 4, (A) to (D) represent changes in the current flowing through the load 20, the output signal of the overcurrent detection unit 11, the output state of the latch 12, and the state of the switch 14, respectively.

  When the switch 14 is turned on at time T30, the current flowing through the load 20 gradually increases as shown in FIG. When it becomes larger than the current threshold Ir of the overcurrent detection unit 11 at time T31, the output signal becomes a high level as shown in (B).

  When the count value of the counter 34 reaches a predetermined value at time T32, the latch 12 is turned on and the switch 14 is turned off. As a result, no overcurrent flows, the counter 34 and the latch 12 are cleared, and as a result, the switch 14 is turned on. This transition is repeated several times.

  Since current flows intermittently through the load 20, the capacity is charged, and the peak value of the current flowing through the load 20 gradually decreases. At time T33, the peak value of the current flowing through the load 20 becomes smaller than the current threshold Ir. For this reason, the output of the latch 12 is not turned on, and the on state of the switch 14 is maintained. In this way, even if the load 20 has a capacity, current can be supplied to the load 20.

  FIG. 5 shows an example when a constant failure occurs in the load 20 and an overcurrent flows. 5, (A) to (C) represent the output signal of the overcurrent detection unit 11, the count value of the counting unit 36, and the state change of the output of the latch 12, respectively.

  When an overcurrent flows through the load 20 at time T40, the output signal of the overcurrent detection unit 11 becomes a high level, and the counter 34 starts counting. When the count value of the counter 34 reaches a predetermined value at time T41, the output of the latch 12 is turned on and the switch 14 is turned off. For this reason, the counter 34 and the latch 12 are cleared. This state is repeated.

  As shown in (B), the counter 36 counts the output signal of the overcurrent detector 11. When the counted value reaches a predetermined value (N) at time T42, the counting unit 36 prohibits the latch 12 from being cleared. Since no current is supplied to the load 20, no overcurrent is generated. For this reason, the count value of the counting unit 36 remains N, and the switch 14 maintains the OFF state.

  When the cause of the overcurrent is removed and a clear signal is input from the outside at time T43, the counter 36 is cleared and the count value becomes zero. The counting unit 36 clears the latch 12. For this reason, the switch 14 is turned on. Since the cause of the overcurrent has been eliminated, no overcurrent flows.

  Thus, in the case of an overcurrent due to a permanent cause, the latch 12 is not cleared after a certain time. For this reason, current supply to the load 20 is prohibited until a clear signal is input from the outside. The predetermined value N is set to a value larger than the number of ON / OFF repetitions in the case of the capacitive load in FIG.

  In the embodiment of FIG. 1, the counter 34 is used to detect that the overcurrent has flowed for a certain period of time, and the time clock during which the overcurrent flows is counted. However, the present invention is not limited to this configuration. . In short, any configuration that can detect that an overcurrent has flowed for a predetermined time may be used.

  Further, although the latch is used as a configuration for generating a signal for forcibly cutting off the current flowing through the load, another configuration, for example, an RS flip-flop may be used. In short, any configuration that generates a signal forcibly shutting off by the output signal of the counter 34 may be used.

  Further, although the output of the latch 12 is an open drain, other configurations may be used. In short, any configuration that forcibly cuts off the current flowing through the load 20 in preference to the output of the switch control unit 13 may be used.

  The overcurrent detection unit 11 detects the overcurrent by comparing the resistance for detecting the current value and the voltage at both ends of the resistor with the current type position, but may have other configurations.

  Furthermore, although the stop cancellation signal generating unit 32 is configured by the signal generating unit 35 and the counting unit 36, other configurations may be used.

DESCRIPTION OF SYMBOLS 11 Overcurrent detection part 12 Latch 14 Switch 30 Digital output device 31 Current stop part 32 Stop release signal generation part 33 Clock generation part 34 Counter 35 Signal generation part 36 Count part

Claims (3)

In a digital output device that supplies current to a load and stops supplying current to the load when an overcurrent flows,
An overcurrent detector that monitors the current flowing through the load and detects that an overcurrent has flowed;
When the output signal of the overcurrent detection unit is input and it is detected that the overcurrent has flowed for a predetermined time, a current stop unit that stops the current supply to the load;
When the output signal of the overcurrent detector is input and no overcurrent flows, the current supply stop of the current stop unit is canceled and the number of times the overcurrent has flowed for a predetermined time is counted. A stop release signal generator for preventing the current supply stop of the current stop unit from being released when the numerical value reaches a predetermined number of times;
A digital output device comprising: The current stopping unit is
A time measuring unit that receives an output signal of the overcurrent detection unit and detects that the overcurrent has flowed for a predetermined time; and
A current stop signal generator that is set by the output signal of the time measuring unit and outputs a signal for forcibly stopping the current supplied to the load; and
The digital output device according to claim 1, comprising: The stop cancellation signal generator is
A signal indicating that the overcurrent has continued for a predetermined time is input, the number of times of this signal is counted, and a counter that outputs a signal when the predetermined number of times is reached;
The output signal of the overcurrent detection unit and the output signal of the counting unit are input to generate a signal for canceling the current stop of the current stop unit when no overcurrent has occurred, and the output of the counting unit When a signal is input, a signal generator that does not generate a signal for canceling the current stop,
The digital output device according to claim 1, wherein the digital output device is configured as follows.

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