JP2012093500A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with excellent display quality.SOLUTION: A liquid crystal display device comprises: a first substrate including an insulating substrate, a dielectric mirror formed in an island-like shape on the insulating substrate, a polysilicon semiconductor layer formed on the dielectric mirror and having a source region and a drain region, a gate insulating film covering the insulating substrate, the dielectric mirror, and the polysilicon semiconductor layer, a gate electrode formed on the gate insulating film, a source electrode contacting the source region of the polysilicon semiconductor layer, a drain electrode contacting the drain region of the polysilicon semiconductor layer, and a pixel electrode electrically connected to the drain electrode; a second substrate disposed facing the first substrate; and a liquid crystal layer held between the first substrate and the second substrate.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  2. Description of the Related Art In recent years, flat display devices have been actively developed. In particular, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix liquid crystal display device in which a thin film transistor (TFT) is incorporated as a switching element in each pixel has a configuration in which a transmissive liquid crystal display panel and a backlight are combined.

  In a configuration in which a top gate type polysilicon TFT provided with a polysilicon semiconductor layer is applied as a switching element, an increase in off-current is a problem as the backlight brightness increases. That is, when the polysilicon semiconductor layer absorbs the backlight light, the drain current of the TFT increases. This increase in drain current is noticeable when the TFT is off, and is referred to as light leakage current. In recent years, there has been a tendency to increase the luminance of the backlight due to the demand for higher luminance of the screen, and accordingly, the display quality can be adversely affected by crosstalk or flicker due to an increase in light leakage current.

JP 07-306409 A JP 2000-298290 A

  An object of the present embodiment is to provide a liquid crystal display device with good display quality.

According to this embodiment,
An insulating substrate, a dielectric mirror formed in an island shape on the insulating substrate, a polysilicon semiconductor layer formed on the dielectric mirror and having a source region and a drain region, the insulating substrate, and the dielectric A mirror, a gate insulating film covering the polysilicon semiconductor layer, a gate electrode formed on the gate insulating film, a source electrode in contact with the source region of the polysilicon semiconductor layer, and the polysilicon semiconductor A first substrate comprising: a drain electrode in contact with the drain region of the layer; and a pixel electrode electrically connected to the drain electrode; a second substrate disposed opposite the first substrate; There is provided a liquid crystal display device comprising: a liquid crystal layer held between the first substrate and the second substrate.

FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device according to the present embodiment. FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG. FIG. 3 schematically shows a cross-sectional structure including the switching elements of the array substrate shown in FIG. FIG. 4 is a cross-sectional view schematically showing a first configuration example of the dielectric mirror. FIG. 5 is a diagram illustrating an example of the relationship between the emission spectrum of the backlight and the reflection spectrum of the dielectric mirror in the first configuration example. FIG. 6 is a diagram showing the measurement result of the light leakage current. FIG. 7 is a diagram showing the result of simulating the change in the light leakage current due to the refractive index of the silicon nitride layer. FIG. 8 is a cross-sectional view schematically showing a second configuration example of the dielectric mirror. FIG. 9 is a diagram illustrating an example of the relationship between the emission spectrum of the backlight and the reflection spectrum of the dielectric mirror in the second configuration example. FIG. 10 is a diagram showing a simulation result of TFT characteristics.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type transmissive liquid crystal display panel LPN, a driving IC chip 2 and a flexible wiring board 3 connected to the liquid crystal display panel LPN, a backlight 4 that illuminates the liquid crystal display panel LPN, and the like. I have.

  The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown). Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  The backlight 4 is disposed on the back side of the array substrate AR. As such a backlight 4, a light source provided with a light emitting diode (LED) is applied, but the detailed structure is not described.

  FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG.

  In the active area ACT, the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like. ing. The gate line G and the auxiliary capacitance line C extend along the first direction X, respectively. The gate lines G and the auxiliary capacitance lines C are alternately arranged in parallel along the second direction Y orthogonal to the first direction X. The source line S extends along the second direction Y that intersects the gate line G and the auxiliary capacitance line C, respectively. The source lines S are arranged in parallel along the first direction X. That is, the gate line G and the auxiliary capacitance line C and the source line S are substantially orthogonal.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. Each auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a counter electrode CE, and the like. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE.

  The switching element SW is constituted by, for example, an n-channel thin film transistor (TFT). The switching element SW is electrically connected to the gate line G and the source line S. In the active area ACT, m × n switching elements SW are formed.

  The pixel electrode PE is formed on the array substrate AR and is electrically connected to the switching element SW. In the active area ACT, m × n pixel electrodes PE are formed. The counter electrode CE has a common potential, for example, and is formed in common to the plurality of pixel electrodes PE via the liquid crystal layer LQ. The counter electrode CE is electrically connected to the power supply unit VS.

  In the present embodiment, the counter electrode CE may be formed on the array substrate AR, or may be formed on the counter substrate CT. In the liquid crystal display panel LPN having the configuration in which the counter electrode CE is formed on the array substrate AR together with the pixel electrode PE, the liquid crystal layer LQ is mainly used by utilizing the horizontal electric field formed between the pixel electrode PE and the counter electrode CE. The liquid crystal molecules that make up the are switched. Such a liquid crystal mode includes an IPS (In-Plane Switching) mode, an FFS (Fringe Field Switching) mode, and the like.

  Further, in the liquid crystal display panel LPN having the configuration in which the counter electrode CE is formed on the counter substrate CT, the liquid crystal layer LQ is configured mainly using the vertical electric field formed between the pixel electrode PE and the counter electrode CE. Switching liquid crystal molecules. Such liquid crystal modes include a TN (Twisted Nematic) mode, an OCB (Optically Compensated Bend) mode, and a VA (Vertical Aligned) mode.

  FIG. 3 schematically shows a cross-sectional structure including switching elements SW of array substrate AR shown in FIG.

  That is, the array substrate AR is formed by using a first insulating substrate 10 having light transparency such as a glass substrate. The array substrate AR includes a dielectric mirror 20 disposed on the first insulating substrate 10, a switching element SW disposed on the dielectric mirror 20, a pixel electrode PE electrically connected to the switching element SW, and the like. It has. The switching element SW shown here is a top-gate thin film transistor.

  The dielectric mirror 20 is formed in an island shape on the upper surface 10T of the first insulating substrate 10. The dielectric mirror 20 functions as a base (or undercoat layer) of the switching element SW, and is removed from the opening that transmits backlight and contributes to display. Although the detailed structure of such a dielectric mirror 20 will be described later, it is formed of a dielectric multilayer film in which a high refractive index insulating film and a low refractive index insulating film are laminated.

  The polysilicon semiconductor layer SC of the switching element SW is formed on the upper surface 20T of the dielectric mirror 20. The polysilicon semiconductor layer SC has a source region SCS and a drain region SCD on both sides of the channel region SCC. The polysilicon semiconductor layer SC is formed in a forward taper shape upward. That is, the angle θ formed between the end surface SCE of the polysilicon semiconductor layer SC and the upper surface 20T of the dielectric mirror 20 is an acute angle.

  Further, the end surface SCE is located on the inner side of the position immediately above the end surface 20E of the dielectric mirror 20. That is, the polysilicon semiconductor layer SC is not formed over the entire upper surface 20T of the dielectric mirror 20. The polysilicon semiconductor layer SC is not formed on the frame-shaped upper surface 20T connected to the four end surfaces 20E of the dielectric mirror 20.

  As a technique for forming the polysilicon semiconductor layer SC on the dielectric mirror 20 having such a shape, a resist receding or half-tone exposure technique is used for etching the insulating film and the polysilicon semiconductor layer SC forming the dielectric mirror 20. Etc. are applicable.

  The gate insulating film 11 includes an upper surface 10T of the first insulating substrate 10 where the dielectric mirror 20 is not formed, an end surface 20E of the dielectric mirror 20, an upper surface 20T of the dielectric mirror 20 where the polysilicon semiconductor layer SC is not formed, The end surface SCE and the upper surface SCT of the polysilicon semiconductor layer SC are covered.

  The gate electrode WG of the switching element SW is formed on the gate insulating film 11 and is located immediately above the channel region SCC of the polysilicon semiconductor layer SC. The gate electrode WG is covered with the first interlayer insulating film 12. The first interlayer insulating film 12 is also disposed on the gate insulating film 11. The gate insulating film 11 and the first interlayer insulating film 12 are formed of an inorganic material such as silicon oxide and silicon nitride, for example.

  The source electrode WS and the drain electrode WD of the switching element SW are formed on the first interlayer insulating film 12. The source electrode WS is in contact with the source region SCS of the polysilicon semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the first interlayer insulating film 12. The drain electrode WD is in contact with the drain region SCD of the polysilicon semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the first interlayer insulating film 12. The gate electrode WG, the source electrode WS, and the drain electrode WD are formed of a conductive material such as molybdenum, aluminum, tungsten, or titanium.

  The switching element SW having such a configuration is covered with the second interlayer insulating film 13. That is, the source electrode WS and the drain electrode WD are covered with the second interlayer insulating film 13. The second interlayer insulating film 13 is also disposed on the first interlayer insulating film 12.

  The pixel electrode PE is formed on the second interlayer insulating film 13. The pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 13. Such a pixel electrode PE is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE is covered with the first alignment film 14.

  According to such a configuration of the present embodiment, since the dielectric mirror 20 is disposed between the polysilicon semiconductor layer SC of the switching element SW and the first insulating substrate 10, the backlight light from the backlight 4. When the array substrate AR is illuminated by the above, the backlight light directed to the switching element SW is reflected by the dielectric mirror 20 after passing through the first insulating substrate 10.

  For this reason, it is possible to reduce the backlight light reaching the polysilicon semiconductor layer SC, and to reduce the light leakage current. Thereby, it is possible to suppress the occurrence of display defects due to crosstalk, flicker, etc., and to provide a liquid crystal display device with good display quality.

  In addition, since the dielectric mirror 20 is not disposed in the opening that contributes to display, the backlight passes through the array substrate AR. For this reason, it is possible to suppress a decrease in the transmittance of the liquid crystal display panel LPN due to the arrangement of the dielectric mirror 20.

  On the other hand, when the end surface SCE of the polysilicon semiconductor layer SC is located immediately above the end surface 20E of the dielectric mirror 20, a steep gap is formed between the upper surface 10T of the first insulating substrate 10 and the upper surface SCT of the polysilicon semiconductor layer SC. In particular, the gate insulating film 11 covering the end surface SCE may be locally thin. In this case, there is a fear that the gate electrode WG formed on the gate insulating film 11 and the polysilicon semiconductor layer SC are electrically connected (gate leakage).

  On the other hand, according to the configuration of the present embodiment, since the end surface SCE of the polysilicon semiconductor layer SC is located on the inner side of the position immediately above the end surface 20E of the dielectric mirror 20, the gate insulating film 11 is The end surface SCE and the upper surface SCT of the polysilicon semiconductor layer SC can be coated with a film thickness necessary to ensure insulation. Therefore, it is possible to suppress the occurrence of gate leak.

  Next, a first configuration example of the dielectric mirror 20 applicable to the present embodiment will be described.

  FIG. 4 is a cross-sectional view schematically showing a first configuration example of the dielectric mirror 20. Here, only the main part necessary for the description is shown, and a cross section including the gate electrode WG straddling the channel region SCC of the polysilicon semiconductor layer SC is shown.

The first insulating substrate 10 is a glass substrate having a thickness of 0.7 mm, for example. The dielectric mirror 20 is disposed on the first insulating substrate 10. The polysilicon semiconductor layer SC is disposed on the dielectric mirror 20 and has a thickness of 49 nm. The gate insulating film 11 is, for example, a SiO ₂ thin film having a thickness of 195 nm, and covers the first insulating substrate 10, the dielectric mirror 20, and the polysilicon semiconductor layer SC. The gate electrode WG is disposed on the gate insulating film 11.

  The dielectric mirror 20 includes a first silicon nitride layer 21 formed on the first insulating substrate 10, a first silicon oxide layer 22 stacked on the first silicon nitride layer 21, and a first silicon oxide layer. A second silicon nitride layer 23 stacked on the material layer 22, a second silicon oxide layer 24 stacked on the second silicon nitride layer 23, and a second silicon oxide layer 24. The third silicon nitride layer 25 and the third silicon oxide layer 26 stacked on the third silicon nitride layer 25 are also included.

The first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 are, for example, 60 nm thick SiN thin films having a refractive index of 1.89. The first silicon oxide layer 22, the second silicon oxide layer 24, and the third silicon oxide layer 26 are, for example, 73 nm thick SiO ₂ thin films having a refractive index of 1.55.

  According to the dielectric mirror 20 composed of a laminate of such a high-refractive index insulating film and a low-refractive index insulating film, light having a specific wavelength can be efficiently reflected. At this time, the optical film thicknesses (n · d; n is the refractive index of the insulating film and d is the film thickness of the insulating film) of the high refractive index insulating film and the low refractive index insulating film are It is desirable to set the wavelength to 1/4 of the specific wavelength.

  The backlight 4 applied in the present embodiment includes a white light source made of a light emitting diode. Such an emission spectrum of the backlight 4 has an emission peak with the highest light intensity in the vicinity of 450 nm. For this reason, the optical film thickness of the high refractive index insulating film and the low refractive index insulating film is set to about 113 nm (= 450 nm / 4).

In this embodiment, the optical film thickness of the SiN thin film that is the high refractive index insulating film is 113.4 nm (= 60 nm * 1.89), and the optical film thickness of the SiO ₂ thin film that is the low refractive index insulating film is 113.nm. 2 nm (= 73 nm * 1.55). According to the dielectric mirror 20 having such a configuration, it is possible to selectively reflect light in the vicinity of 450 nm where the light intensity of the backlight 4 is the highest.

In the illustrated example, the dielectric mirror 20 has a configuration in which a set of a SiN thin film, which is a high refractive index insulating film, and a SiO ₂ thin film, which is a low refractive index insulating film, is stacked for three cycles. Then, the effect of reflecting the backlight light (that is, the effect of reducing the light leakage current by reducing the backlight light reaching the polysilicon semiconductor layer SC) can be obtained. Further, as the number of cycles increases (that is, as the number of high refractive index insulating films and low refractive index insulating films constituting the dielectric mirror 20 increases), the reflectance increases and the effect of reducing the light leakage current increases. .

FIG. 5 is a diagram illustrating an example of the relationship between the emission spectrum of the backlight 4 and the reflection spectrum of the dielectric mirror 20 in the first configuration example. In FIG. 5, the horizontal axis represents the wavelength (nm), and the vertical axis represents the reflectance of the reflection spectrum. In the figure, “BL” is the emission spectrum of the backlight 4, and the vertical axis is the light intensity (au) although not shown. “1 cycle”, “2 cycle”, and “3 cycle” in the figure indicate the first insulating substrate 10 of light incident from the first insulating substrate 10 side when the dielectric mirror 20 having the respective configurations is applied. It is the reflection spectrum which calculated the reflectance in the side. Further, in the “0 cycle” in the figure, the reflectance at the first insulating substrate 10 side of the light incident from the first insulating substrate 10 side when the undercoat layer is applied instead of the dielectric mirror 20 was calculated. It is a reflection spectrum. The other conditions are the same, the polysilicon semiconductor layer SC is 49 nm thick, and the gate insulating film is a 195 nm thick SiO ₂ thin film.

  The configuration in which the “1 cycle”, “2 cycle”, or “3 cycle” dielectric mirror 20 is applied corresponds to this embodiment. The configuration in which the “one-cycle” dielectric mirror 20 is applied is that the dielectric mirror 20 including the first silicon nitride layer 21 and the first silicon oxide layer 22 is applied, and the polysilicon semiconductor layer SC is the first silicon. This corresponds to the structure formed on the oxide layer 22. The configuration in which the “two-cycle” dielectric mirror 20 is applied includes the first silicon nitride layer 21, the first silicon oxide layer 22, the second silicon nitride layer 23, and the second silicon oxide layer 24. This corresponds to the configuration in which the dielectric mirror 20 is applied and the polysilicon semiconductor layer SC is formed on the second silicon oxide layer 24. The configuration to which the “3-cycle” dielectric mirror 20 is applied corresponds to the configuration shown in FIG. Unlike the present embodiment, the “0 cycle” is a 50 nm thick SiN thin film formed on the entire surface of the first insulating substrate 10 as an undercoat layer, and a 100 nm film formed on the entire surface of the SiN thin film. This corresponds to a configuration in which the polysilicon semiconductor layer SC is formed on the SiO thin film.

  As shown in the figure, the emission spectrum of the backlight 4 has an emission peak in the vicinity of 450 nm, whereas in the “1 cycle” reflection spectrum, the reflectance at a wavelength of 450 nm is about 10%. In the reflection spectrum of "", the reflectance at a wavelength of 450 nm is about 20%, and in the reflection spectrum of "3 cycles", the reflectance at a wavelength of 450 nm is about 30%. Thus, it was confirmed that the reflectance with respect to light near a specific wavelength (here, 450 nm) increases as the number of cycles increases.

  FIG. 6 is a diagram showing the measurement result of the light leakage current. Here, a plurality of prototypes configured to apply the respective dielectric mirrors 20 of “1 cycle”, “2 cycles”, and “3 cycles” and a plurality of prototypes configured of “0 cycle” The light leakage current was measured under the same conditions.

  When the average value of the light leakage current in “0 cycle” is 100%, the light leakage current in “1 cycle” is reduced by 17%, the light leakage current in “2 cycles” is reduced by 22%, It was confirmed that the light leakage current in “3 cycles” was reduced by 25%.

FIG. 7 is a diagram showing the result of simulating the change in the light leakage current due to the refractive index of the silicon nitride layer. Here, as described above, the first silicon oxide layer 22, the second silicon oxide layer 24, and the third silicon oxide layer 26 are all formed of SiO having a refractive index of 1.55 and a thickness of 73 nm. ₂ thin films. The first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 all have a constant optical film thickness (about 113 nm), but have a refractive index of 1.89 to 2. Different SiN thin films were applied in the range up to .2.

  When the first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 are SiN thin films having a refractive index of 1.89 and a thickness of 60 nm, “0 cycle” When the light leakage current at 100% is assumed to be 100%, the light leakage current at “1 cycle” is reduced by about 5%, the light leakage current at “2 cycles” is reduced by about 15%, and the light leakage current at “3 cycles” is reduced. The light leakage current was reduced by about 25%.

  When the first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 are 56 nm thick SiN thin films having a refractive index of 2.0, “0 cycle” When the light leakage current at 100% is assumed to be 100%, the light leakage current at “1 cycle” is reduced by about 7%, the light leakage current at “2 cycles” is reduced by about 22%, and the light leakage current at “3 cycles” is reduced. The light leakage current was reduced by about 40%.

  When the first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 are 54 nm thick SiN thin films having a refractive index of 2.1, “0 cycle” When the light leakage current at 100% is assumed to be 100%, the light leakage current at "1 cycle" is reduced by about 10%, the light leakage current at "2 cycles" is reduced by about 30%, and the light leakage current at "3 cycles" is reduced. The light leakage current was reduced by about 50%.

  When the first silicon nitride layer 21, the second silicon nitride layer 23, and the third silicon nitride layer 25 are 51 nm thick SiN thin films having a refractive index of 2.2, “0 cycle” When the light leakage current at 100% is assumed to be 100%, the light leakage current at “1 cycle” is reduced by about 13%, the light leakage current at “2 cycles” is reduced by about 37%, and the light leakage current at “3 cycles” is reduced. The light leakage current was reduced by about 58%.

  As described above, even when the “1-cycle” dielectric mirror 20 is applied, the light leakage current of 5% can be reduced when the refractive index of the silicon nitride layer is 1.89, and silicon When the refractive index of the nitride layer is increased to 2.2, the light leakage current of 13% can be reduced. That is, even if the number of cycles is the same, the greater the difference between the refractive index of the high refractive index insulating film and the refractive index of the low refractive index insulating film that constitutes the dielectric mirror 20, the greater the reflectivity and the light leakage. It was confirmed that the current reduction effect was increased. It was also confirmed that the greater the number of cycles, the greater the reflectivity and the greater the effect of reducing light leakage current. In other words, if the difference between the refractive index of the high refractive index insulating film and the refractive index of the low refractive index insulating film is large, the number of cycles for obtaining the same reflectance can be reduced, that is, the dielectric mirror 20 The number of layers constituting the can be reduced.

  Next, a second configuration example of the dielectric mirror 20 applicable to the present embodiment will be described.

  FIG. 8 is a cross-sectional view schematically showing a second configuration example of the dielectric mirror 20. Here, only the main part necessary for the description is shown, and a cross section including the gate electrode WG straddling the channel region SCC of the polysilicon semiconductor layer SC is shown. This second configuration example is different from the first configuration example shown in FIG. 4 in that the dielectric mirror 20 is composed of a single high refractive index insulating film and a single low refractive index insulating film. It is different. In the second configuration example, the same components as those in the first configuration example are denoted by the same reference numerals, and detailed description thereof is omitted.

  The dielectric mirror 20 includes a silicon nitride layer 21 formed on the first insulating substrate 10 and a silicon oxide layer 22 stacked on the silicon nitride layer 21. Each of the silicon nitride layer 21 and the silicon oxide layer 22 has an optical film thickness of about 113 nm, and is optimized to reflect light having a specific wavelength of 450 nm.

The silicon oxide layer 22 is a 73 nm thick SiO ₂ thin film having a refractive index of 1.54, for example. The silicon nitride layer 21 has a refractive index of 1.89 or more and 2.6 or less. The film thickness of the silicon nitride layer 21 is appropriately determined according to the refractive index so that the optical film thickness is about 113 nm.

  As described above, the greater the difference between the refractive index of the high-refractive index insulating film and the refractive index of the low-refractive index insulating film that constitutes the dielectric mirror 20, the higher the reflectivity, the greater the effect of reducing the light leakage current. To do. For this reason, it is desirable that the refractive index of the silicon nitride layer 21 be as high as possible. In order to improve the refractive index of the silicon nitride layer 21, for example, when the silicon nitride layer 21 is formed by a CVD method, the gas flow rate is adjusted to bring the film quality closer to silicon (Si). It is feasible. However, if the refractive index of the silicon nitride layer 21 is excessively increased, insulation cannot be maintained, and normal TFT characteristics cannot be obtained in the switching element SW. Therefore, the refractive index of the silicon nitride layer 21 is 2. 6 or less is desirable.

FIG. 9 is a diagram illustrating an example of the relationship between the emission spectrum of the backlight 4 and the reflection spectrum of the dielectric mirror 20 in the second configuration example. In FIG. 9, the horizontal axis represents the wavelength (nm), and the vertical axis represents the reflectance of the reflection spectrum. In the figure, “BL” is the emission spectrum of the backlight 4, and the vertical axis is the light intensity (au) although not shown. Each reflection spectrum in the figure shows the first light of light incident from the first insulating substrate 10 side when the dielectric mirror 20 having a configuration in which the refractive index and film thickness of the silicon nitride layer 21 are different from each other is applied. The reflectance on the insulating substrate 10 side is calculated. The other conditions are the same, the silicon oxide layer 22 is a 73 nm thick SiO ₂ thin film having a refractive index of 1.54, the polysilicon semiconductor layer SC is 49 nm thick, and gate insulation The film is a SiO ₂ thin film having a thickness of 195 nm.

  The silicon nitride layer 21 having a refractive index of 1.89 has a film thickness of 60 nm so that the optical film thickness is about 113 nm. Similarly, the silicon nitride layer 21 having a refractive index of 2.0 has a thickness of 56 nm, the silicon nitride layer 21 having a refractive index of 2.2 has a thickness of 51 nm, and silicon having a refractive index of 2.4. The nitride layer 21 has a thickness of 47 nm, the silicon nitride layer 21 with a refractive index of 2.6 has a thickness of 43 nm, and the silicon nitride layer 21 with a refractive index of 2.8 has a thickness of 40 nm. The silicon nitride layer 21 having a refractive index of 3.0 has a thickness of 37 nm, the silicon nitride layer 21 having a refractive index of 3.2 has a thickness of 35 nm, and has a refractive index of 3.4. The nitride layer 21 has a thickness of 33 nm.

  As shown in the figure, the emission spectrum of the backlight 4 has an emission peak in the vicinity of 450 nm, whereas the refractive index n and film thickness d (nm) of the silicon nitride layer 21 are (n, d). = (1.89,60), the reflectance at a wavelength of 450 nm is 8%, and similarly, the reflectance at (n, d) = (2.0,56) is 10%. The reflectance at (n, d) = (2.2, 51) is 14%, the reflectance at (n, d) = (2.4, 47) is 18%, and (n, d ) = (2.6, 43) reflectivity is 22%, (n, d) = (2.8, 40) reflectivity is 27%, (n, d) = (3 .0, 37) has a reflectance of 32%, (n, d) = (3.2, 35) has a reflectance of 36%, and (n, d) = (3.4, 33). )so A reflectance of 40%.

  Thus, it was confirmed that the higher the refractive index of the silicon nitride layer 21 constituting the dielectric mirror 20, the higher the reflectivity for light near a specific wavelength (450 nm in this case) in the reflection spectrum.

  FIG. 10 is a diagram showing simulation results for a TFT characteristic drain voltage of 10 V, a gate insulating film of 80 nm, a transistor channel width of 4.5 μm, and a channel length of 3 μm.

In the figure, the vertical axis represents the drain current Id (au), and the horizontal axis represents the gate voltage Vg (V). A in the figure is a simulation result of TFT characteristics when the refractive index of the silicon nitride layer 21 formed on the first insulating substrate 10 is equivalent to that of silicon (Si) (here, ε _r = 12). It corresponds to. B in the drawing corresponds to a simulation result of TFT characteristics when silicon is formed on the first insulating substrate 10 instead of the silicon nitride layer 21. About other conditions, both are the same.

When the silicon nitride layer 21 which is an insulator is applied, even if the refractive index is increased to the same level as that of silicon, normal TFT characteristics (TFT when the silicon nitride layer 21 with ε _r = 7.5 is applied) It was confirmed that TFT characteristics substantially equivalent to the characteristics were obtained. On the other hand, when silicon, which is a semiconductor, is applied, off-current increases and on-current decreases, so that TFT characteristics sufficient as a switching element of a liquid crystal display panel cannot be obtained.

  Thus, by setting the difference between the refractive index of the high-refractive index insulating film and the refractive index of the low-refractive index insulating film constituting the dielectric mirror 20 as large as possible within a range where insulation can be secured, TFT characteristics can be set. It is possible to selectively reflect light of a specific wavelength without impairing it, and it is possible to suppress the occurrence of light leakage current. Therefore, occurrence of crosstalk and flicker can be suppressed.

  As described above, according to this embodiment, it is possible to provide a liquid crystal display device with good display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer PE ... Pixel electrode SW ... Switching element SC ... Polysilicon semiconductor layer 20 ... Dielectric mirror 21 ... Silicon nitride layer 22 ... Silicon oxide layer

Claims (5)

An insulating substrate, a dielectric mirror formed in an island shape on the insulating substrate, a polysilicon semiconductor layer formed on the dielectric mirror and having a source region and a drain region, the insulating substrate, and the dielectric A mirror, a gate insulating film covering the polysilicon semiconductor layer, a gate electrode formed on the gate insulating film, a source electrode in contact with the source region of the polysilicon semiconductor layer, and the polysilicon semiconductor A first substrate comprising: a drain electrode in contact with the drain region of the layer; and a pixel electrode electrically connected to the drain electrode;
A second substrate disposed opposite the first substrate;
A liquid crystal layer held between the first substrate and the second substrate;
A liquid crystal display device comprising:   The liquid crystal display device according to claim 1, wherein an end face of the polysilicon semiconductor layer is located inside a position immediately above the end face of the dielectric mirror.   The liquid crystal display device according to claim 1, further comprising a backlight including a light source disposed on a back side of the first substrate and made of a light emitting diode.   The dielectric mirror includes a silicon nitride layer formed on the insulating substrate, and a silicon oxide layer stacked on the silicon nitride layer, and the silicon nitride layer and the silicon oxide layer. 4. The liquid crystal display device according to claim 1, wherein each of the physical layers has an optical film thickness of about 113 nm.   The liquid crystal display device according to claim 4, wherein the silicon nitride layer has a refractive index of 1.89 or more and 2.6 or less.

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