JP2012090179A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve diversity of output images.SOLUTION: When a camera image mode is selected, an H zoom circuit 12a fetches video data comprising pixel data of a plurality of pixels in a raster scanning form. An LM controller 14a accesses a line memory 16a in order to write in and read the video data outputted from the H zoom circuit 12a. Multipliers 18a, 20a and an adder 24a composite the video data of a present line outputted from the H zoom circuit 12a and the video data of a previous line read by the LM controller 14a. When an ODS mode is selected instead of the camera image mode, the LM controller 14a writes color data of 256 colors respectively corresponding to 256 pieces of color numbers into the line memory 16a. The LM controller 14a reads the color data corresponding to a specified color number from the line memory 16a.

Description

  The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus that processes visible data having different properties.

  An example of this type of data processing apparatus is disclosed in Patent Document 1. According to this background art, the address generation circuit is activated by a start signal, and generates a column address and a row address in synchronization with a clock signal. Still image data is written into the graphic memory based on the generated column address and row address. The sampling circuit captures moving image data based on the sampling signal. The selector circuit selects one of the still image data written in the graphic memory and the moving image data captured by the sampling circuit based on the switching signal. The line memory latches the image data output from the selector circuit based on the latch signal. As a result, a circuit for processing moving image data and a circuit for processing still image data are shared, and the circuit scale is reduced.

Japanese Patent Laid-Open No. 8-18953

  However, in the background art, color data of a plurality of colors respectively corresponding to a plurality of predetermined color numbers is not processed, and there is a limit to the diversity of output images.

  Therefore, a main object of the present invention is to provide a data processing apparatus capable of enhancing the diversity of output images.

  A data processing apparatus according to the present invention (10: reference numeral corresponding to the embodiment; the same applies hereinafter) includes a capturing unit (12a) that captures pixel data of a plurality of pixels corresponding to the first mode, and pixel data captured by the capturing unit. Access means (34-36, 42-44, 50-58, 62-70, S5) for accessing the memory (16a) for writing and reading out, pixel data captured by the capture means and the access means from the memory Combining means (18a to 24a, S3) for combining the read pixel data, a memory corresponding to a second mode in which the color data corresponding to a plurality of predetermined colors is replaced with the first mode Writing means (32, 40, 48, S7) for writing to the memory, and reading means (34 to 36, 42 to 44, 62 to 70, S11) for reading out color data corresponding to the designated color from the memory.

  Preferably, the writing means outputs write address output means (40) for outputting a plurality of write addresses respectively corresponding to a plurality of colors, and color data for outputting color data of a plurality of colors in parallel with the output of the write address output means Output means (48) is included.

  More preferably, the reading means includes read address output means (42 to 44) for outputting a read address corresponding to the designated color.

  Preferably, pixel data of one pixel is expressed by a first number of bits, while color data of one color is expressed by a second number of bits that is N times the first number (N: an integer equal to or greater than 2). The access means includes combining means (52 to 54) for combining pixel data of N pixels in relation to data writing, and dividing means (62 to 64) for dividing pixel data of N pixels in relation to data reading. Including.

  Preferably, mixing means (26) for mixing the pixel data output from the adding means corresponding to the first mode and the color data output from the reading means corresponding to the second mode is further provided.

  Preferably, the pixel data of a plurality of pixels captured by the capturing unit corresponds to data forming an object scene image.

  According to the present invention, when the first mode is selected, an image having a desired magnification is created based on the captured pixel data of a plurality of pixels. On the other hand, when the second mode is selected, an image having a desired color or pattern is created by controlling the designation of the color number. This increases the diversity of the output image.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

It is a block diagram which shows the basic composition of one Example of this invention. It is a block diagram which shows the structure of one Example of this invention. (A) is an illustrative view showing an example of an access operation of the line memory in the camera image mode, and (B) is an illustrative view showing an example of an access operation of the line memory in the OSD mode. It is a block diagram which shows an example of a structure of the LM controller applied to the FIG. 2 Example. (A) is an illustrative view showing an example of an output operation of a video clock, (B) is an illustrative view showing an example of an output operation of a video read select signal, and (C) is an output of a video R / W address signal. It is an illustration figure which shows an example of operation | movement, (D) is an illustration figure which shows an example of output operation of LM read data, (E) is an illustration figure which shows an example of output operation of a read buffer, (F) Is an illustrative view showing an example of an output operation of video read data, (G) is an illustrative view showing an example of an output operation of video write data, and (H) is an illustrative view showing an example of an output operation of a write buffer. (I) is an illustrative view showing one example of an output operation of LM write data. (A) is an illustrative view showing an example of an output operation of a CPU clock, (B) is an illustrative view showing an example of an output operation of a CPU write enable signal, and (C) is an output operation of a CPU write select signal. It is an illustration figure which shows an example, (D) is an illustration figure which shows an example of output operation of a CPU write address signal, (E) is an illustration figure which shows an example of output operation of CPU write data. (A) is an illustrative view showing an example of an output operation of a video clock, (B) is an illustrative view showing an example of an output operation of a video read select signal, and (C) is an output of a video R / W address signal. It is an illustration figure which shows an example of operation | movement, (D) is an illustration figure which shows an example of output operation | movement of LM read data and video read data. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 2 Example.

Embodiments of the present invention will be described below with reference to the drawings.
[Basic configuration]

  Referring to FIG. 1, the data processing apparatus of this embodiment is basically configured as follows. The capturing unit 1 captures pixel data of a plurality of pixels corresponding to the first mode. The access unit 2 accesses the memory 6 for writing and reading out the pixel data captured by the capturing unit 1. The synthesizing unit 3 synthesizes the pixel data captured by the capturing unit 1 and the pixel data read from the memory 6 by the access unit 2. The writing means 4 stores in the memory 6 corresponding to the second mode in which the color data of the plurality of colors respectively corresponding to the plurality of color numbers set corresponding to the plurality of predetermined colors is replaced with the first mode. Write. The reading unit 5 reads out from the memory 6 color data corresponding to a designated color number that is a color number corresponding to a designated color that designates one of a plurality of predetermined colors.

When the first mode is selected, an image having a desired magnification is created based on the captured pixel data of a plurality of pixels. On the other hand, when the second mode is selected, an image having a desired color or pattern is created by controlling the designation of the color number. This increases the diversity of the output image.
[Example]

  Referring to FIG. 2, the data processing apparatus 10 of this embodiment uses video data representing an object scene captured by an imaging apparatus (not shown) and / or colors for drawing characters such as figures and characters. Processing circuits PRC1 and PRC2 each processing data are included.

  The CPU 28 sets one of a camera image mode and an OSD (on-screen display) mode, which are alternatively selected, in each of the processing circuits PRC1 and PRC2. The processing circuits PRC1 and PRC2 execute a common processing operation when a common operation mode is set, and execute different processing operations when different operation modes are set.

  When the camera image mode is set, the H zoom circuit 12a captures video data in a raster scanning manner and adjusts the horizontal zoom magnification of the captured video data. Video data having the adjusted horizontal zoom magnification is supplied to the LM controller 14a line by line as video light data. The LM controller 14a converts the supplied video light data of each line into LM write data, and supplies the converted LM write data to the line memory 16a together with the R / W signal and the ADRS signal.

  Here, both the video light data and the LM light data are formed by pixel data of a plurality of pixels. One pixel is expressed by 8 bits. However, video write data is data defined with 8 bits as 1 byte, whereas LM write data is data defined with 16 bits as 2 bytes. Accordingly, one pixel is assigned to each byte in the video light data, while two pixels are assigned to each byte in the LM write data.

  The R / W signal is a signal indicating whether the access mode is “read” or “write”. The H level indicates “read” while the L level indicates “write”. The ADRS signal is a signal indicating the address value of the access destination, and the address value is set to “0” at a timing corresponding to the head of each line, and is updated every time a period corresponding to two pixels elapses. The upper limit value of the address value corresponds to ½ of the number of horizontal pixels of the image represented by the video light data. For example, if the number of horizontal pixels is “640”, the address value is incremented from “0” to “319” every time a period corresponding to two pixels elapses.

  Referring to FIG. 3A, line memory 16a is formed by a total of 1024 addresses each having a capacity of 8 bits. The LM write data converted by the LM controller 14a is written to an address indicated by the ADRS signal when the R / W signal indicates “write”.

  In the camera image mode, the LM controller 14a switches the setting of the R / W signal between “read” and “write” during a period in which the ADRS signal indicates a common address (= 2 pixel period). Strictly speaking, the R / W signal is set to “read” in the first half pixel period, and is set to “write” in the second half pixel period. As a result, the pixel data of the two pixels are first read from the designated address, and then the pixel data of another two pixels are written to the designated address.

  The video light data is output from the H zoom circuit 12a in a raster scanning manner, and the numerical value indicated by the ADRS signal is updated as described above in each line, so that the read pixel data of the two pixels belongs to the previous line and is written. The pixel data of 2 pixels belongs to the current line. Further, the horizontal positions of the two pixels coincide between the previous line and the current line.

  The data read from the line memory 16a in this way is given to the LM controller 14a as LM read data. The LM read data is also data in which 2 pixels are assigned to each byte (= 16 bits). The LM controller 14a converts such data into data in which one pixel is assigned to each byte (= 8 bits), and outputs the converted data as video read data.

  The multiplier 18a multiplies the video read data output from the LM controller 14a, that is, the video data of the previous line by a coefficient K. On the other hand, the multiplier 20a multiplies the video light data from the H zoom circuit 12a, that is, the video data of the current line by a coefficient “1-K”. Here, the coefficient K indicates a numerical value correlated with the vertical zoom magnification, and is output from the coefficient generation circuit 22a. The adder 24a adds the output of the multiplier 18a and the output of the multiplier 20a to each other. As a result, video data with the vertical zoom magnification adjusted is output from the processing circuit PRC1.

  When the OSD mode is set, the CPU 28 gives CPU write data to the LM controller 14a. The LM controller 14a defines the given CPU write data as LM write data, and provides the defined LM write data to the line memory 16a together with the R / W signal and the ADRS signal.

  Here, both the CPU write data and the LM write data are 256-byte data in which 1 byte is expressed by 8 bits. The 256 bytes are assigned 256 colors in a predetermined order. The numerical value indicated by the ADRS signal increases from “0” to “255” for each byte. Further, the R / W signal continuously indicates “write” during a period in which the LM write data is supplied to the line memory 16a.

  As a result, the LM write data is written into the line memory 16a in the manner shown in FIG. Data indicating the 0th color is written to the 0th address, data indicating the 1st color is written to the 1st address, and data indicating the 1st color is written to the 1st address. Similarly, the 255th color data is written to the 255th address.

  After such a writing process is completed, the LM controller 14a reads data indicating the color designated by the CPU 28 from the line memory 16a as LM read data. At this time, the R / W signal continuously indicates “read”, and the ADRS signal indicates a numerical value corresponding to the designated color. The LM read data read in this way is given to the multiplier 18a as video read data.

  When the OSD mode is set, the variable K continuously indicates “1”. For this reason, the multiplier 20a and the adder 24a are substantially meaningless, and the video read data is output from the processing circuit PRC1 as it is.

  The operation of the processing circuit PRC2 is the same as that of the processing circuit PRC1 described above in both the camera image mode and the OSD mode. Accordingly, by replacing “a” attached to the reference number with “b”, redundant description is omitted.

  The mixer 26 mixes the data thus output from the processing circuits PRC1 and PRC2 at a specified ratio. The mixed data generated thereby is output as video data to an LCD monitor (not shown).

  Each of the LM controllers 14a and 14b is configured as shown in FIG. In addition to the CPU write data described above, the CPU 28 outputs a CPU write enable signal, a CPU write select signal, a video read select signal, a CPU write address signal, and a video R / W address signal.

  Among them, the CPU write enable signal is directly input to the AND gates 32, 40 and 48 and also input to the AND gates 36, 44, 58 and 70 via the inverters 34, 42, 50 and 68. The CPU write select signal is directly input to the AND gate 32. The video read select signal is input directly to the AND gates 36 and 70 and also input to the AND gate 58 via the inverter 56. The CPU write address signal is directly input to the AND gate 40. The video R / W address signal is directly input to the AND gate 44.

  The AND gate 32 performs an AND process on the CPU write enable signal and the CPU write select signal and inputs the AND signal to the OR gate 38. The AND gate 36 performs AND processing on the inverted signal output from the inverter 34 and the video read select signal, and inputs the AND signal to the OR gate 38. The OR gate 38 performs an OR process on the AND signal output from the AND gate 32 and the AND signal output from the AND gate 36, and outputs the OR signal as an R / W signal.

  The AND gate 40 performs an AND process on the CPU write enable signal and the CPU write address signal, and inputs the AND signal to the OR gate 46. The AND gate 44 performs an AND process on the inverted signal output from the inverter 42 and the video R / W address signal, and inputs the AND signal to the OR gate 46. The OR gate 46 performs an OR process on the AND signal output from the AND gate 40 and the AND signal output from the AND gate 44, and outputs the OR signal as an ADRS signal.

  The AND gate 48 performs an AND process on the CPU write enable signal and the CPU write data, and inputs the AND signal to the OR gate 60. The AND gate 58 performs an AND process on the inverted signal output from the inverter 50, the combined data output from the multiplexing circuit MP1 described later, and the inverted signal output from the inverter 56, and inputs the AND signal to the OR gate 60. . The OR gate 60 performs an OR process on the AND signal output from the AND gate 48 and the AND signal output from the AND gate 58, and outputs the OR signal as LM write data.

  The AND gate 70 performs an AND process on the data output from the separation circuit SP1 described later, the inverted signal output from the inverter 68, and the video read select signal, and outputs the AND signal as video read data.

  The multiplexing circuit MP1 is formed by the write buffer 54 and the coupler 52. The write buffer 54 takes in video light data input from the H zoom circuit 12a or 12b every other pixel. The combiner 52 combines the video light data input from the H zoom circuit 12a or 12b and the video light data stored in the write buffer 54 every other pixel. The capturing process of the write buffer 54 and the combining process of the combiner 52 are alternatively performed, whereby two consecutive pixels are allocated to 2 bytes.

  The separation circuit SP1 is formed by a divider 62, a read buffer 64, and a selector 66. The divider 62 divides the LM read data read from the line memory 16a or 16b into two, and inputs the first half 8-bit data directly to the selector 66, while the latter half 8-bit data is sent to the selector via the read buffer 64. 66. The selector 66 is also directly input with the LM read data read from the line memory 16a or 16b.

  The selector 66 alternately selects the first half 8-bit data output from the divider 62 and the second half 8-bit data output from the read buffer 64 when the camera image mode is set. In the camera image mode, the LM read data is read from the line memory 16a or 16b every other pixel period. The LM read data read in this way corresponds to data in which 2 pixels are assigned to 2 bytes (= 16 bits). Therefore, when the selector 66 operates as described above, data in which one pixel is assigned to one byte (= 8 bits) is continuously output from the selector 66.

  The selector 66 also continuously selects the LM read data read from the line memory 16a or 16b when the OSD mode is set. As a result, data in which one color is assigned to 1 byte (= 8 bits) is continuously output from the selector 66.

  Referring to FIGS. 5A to 5I, each of LM controllers 14a and 14b operates as follows in the camera image mode. In the camera image mode, the CPU light enable signal continuously indicates the L level.

  When the video clock changes as shown in FIG. 5A, the video read select signal changes as shown in FIG. 5B, and the video R / W address signal changes as shown in FIG. 5C. To do. One cycle of the video clock corresponds to one pixel period, the video read select signal changes between H level and L level every time one pixel period elapses, and the numerical value indicated by the video R / W address signal is video. Updated in response to the rise of the read select signal.

  Since the CPU write enable signal continuously indicates L level, the video read select signal is output from the OR circuit 38 as an R / W signal, and the video R / W address signal is output from the OR circuit 46 as an ADRS signal.

  Therefore, the LM read data is read from the line memory 16a or 16b in the manner shown in FIG. 5D during the period when the video read select signal is at the H level. Further, the lower 8 bits of the LM read data are output from the read buffer 64 as shown in FIG. As a result, the video read data is output from the AND circuit 70 in the manner shown in FIG.

  Further, the video light data is input in the manner shown in FIG. 5G, and a part thereof is output from the write buffer 54 in the manner shown in FIG. As a result, the LM write data is output from the OR circuit 60 in the manner shown in FIG.

  Referring to FIGS. 6A to 6E, when 256 color data is written to line memory 16a or 16b under OSD mode, each of LM controllers 14a and 14b operates as follows. To do.

  When the CPU clock changes as shown in FIG. 6A, the CPU write enable signal changes as shown in FIG. 6B, and the CPU write select signal changes as shown in FIG. 6C. Both the CPU write enable signal and the CPU write select signal indicate the H level over the 256 clock period from the rising edge of the CPU clock.

  As can be seen from FIG. 6D, the numerical value indicated by the CPU write address signal ranges from “0” to “255” each time the CPU clock rises during the period when the CPU write enable signal and the CPU write select signal are at the H level. Incremented. Further, as can be seen from FIG. 6E, the color indicated by the CPU write data is from the 0th color to the 255th every time the CPU clock rises during the period when the CPU write enable signal and the CPU write select signal are at the H level. Updated to the color of. As a result, 256 color data are written to 256 addresses of the line memory 16a or 16b, respectively.

  Referring to FIGS. 7A to 7D, when color data of a specified color is read from line memory 16a or 16b under the OSD mode, each of LM controllers 14a and 14b operates as follows. To do. When reading out the color data, the CPU write enable signal continuously indicates the L level.

  The video clock changes as shown in FIG. As described above, one cycle of the video clock corresponds to one pixel period. When the color data indicating the 38th color is read out over a period of 10 pixels, the video read select signal indicates the H level over the 10 clock period from the rising edge of the video clock, and the video R / W address signal is “38” over the same 10 clock period. Indicates. The color data indicating the 38th color is output as LM read data or video read data as shown in FIG.

  The CPU 28 executes processing according to the flowchart shown in FIG. 8 corresponding to each of the processing circuits PRC1 and PRC2.

  First, in step S1, it is determined which of the camera image mode and the OSD mode is selected. When the camera image mode is selected, the process is finished through steps S3 to S5, and when the OSD mode is selected, the process is finished through steps S7 to S11.

  In step S3, the horizontal zoom magnification and the vertical zoom magnification are set to designated magnifications, and in step S5, data writing to and data reading from the line memory 16a or 16b is started. As a result, the operations shown in FIGS. 5A to 5I are continuously performed.

  In step S7, 256 color data is written into the line memory 16a or 16b. The write operation is executed as shown in FIGS. 6 (A) to 6 (E). In step S9, the zoom magnification is set to “1.0”, and in step S11, an operation of reading out color data of the designated color is started. The color data of the designated color is read from the line memory 16a or 16b in the manner shown in FIGS. 7 (A) to 7 (D).

  As can be seen from the above description, when the camera image mode is selected, the H zoom circuit 12a captures video data including pixel data of a plurality of pixels in a raster scanning manner. The LM controller 14a accesses the line memory 16a to write and read video data output from the H zoom circuit 12a. The multipliers 18a and 20a and the adder 24a combine the video data of the current line output from the H zoom circuit 12a with the video data of the previous line read by the LM controller 14a. When the ODS mode is selected instead of the camera image mode, the LM controller 14a writes 256 color data corresponding to 256 color numbers to the line memory 16a. The LM controller 14a reads color data corresponding to the designated color number from the line memory 16a among the color data thus written.

  When the camera image mode is selected, an image having a desired magnification is created based on the captured video data. On the other hand, when the OSD mode is selected, an image having a desired color or pattern is created by controlling the designation of the color number. This increases the diversity of the output image.

  In this embodiment, 1024 addresses are provided in each of the line memories 16a and 16b. However, the number of addresses is not limited to "1024". Further, the data processing apparatus 10 of this embodiment can be applied to any electronic device that reproduces video data and OSD data.

DESCRIPTION OF SYMBOLS 10 ... Data processor 12a, 12b ... H zoom circuit 14a, 14b ... LM controller 16a, 16b ... Line memory 18a, 18b, 20a, 20b ... Multiplier 24a, 24b ... Adder 26 ... Mixer 28 ... CPU

Claims (6)

Capture means for capturing pixel data of a plurality of pixels corresponding to the first mode;
Access means for accessing a memory for writing and reading pixel data captured by the capturing means;
Combining means for combining the pixel data captured by the capturing means and the pixel data read from the memory by the access means;
Write means for writing color data corresponding to a plurality of predetermined colors into the memory corresponding to a second mode replacing the first mode, and reading out color data corresponding to a specified color from the memory A data processing apparatus comprising reading means.   The writing means outputs write address output means for outputting a plurality of write addresses corresponding to the plurality of colors, and color data output means for outputting the color data of the plurality of colors in parallel with the output of the write address output means. The data processing apparatus according to claim 1, comprising:   The data processing apparatus according to claim 2, wherein the reading unit includes a reading address output unit that outputs a reading address corresponding to the designated color. The pixel data of one pixel is expressed by a first number of bits, while the color data of one color is expressed by a second number of bits that is N times the first number (N: an integer equal to or greater than 2).
4. The access unit according to claim 1, further comprising a combining unit that combines pixel data of N pixels in association with data writing, and a dividing unit that divides pixel data of the N pixels in association with data reading. A data processing device according to any one of the above.   5. The apparatus according to claim 1, further comprising a mixing unit that mixes the pixel data output from the adding unit corresponding to the first mode and the color data output from the reading unit corresponding to the second mode. A data processing apparatus according to any one of the above.   6. The data processing apparatus according to claim 1, wherein pixel data of a plurality of pixels captured by the capturing unit corresponds to data forming an object scene image.

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