JP2012089702A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the design flexibility when forward voltage Vf is adjusted while suppressing a leakage current in the reverse direction without changing the on resistance of a field effect transistor, so as to allow fine adjustment of the forward voltage Vf and the leakage current without increasing the chip area or drastically narrowing the current path.SOLUTION: A semiconductor device 1 includes: a semiconductor substrate 11 of a first conductivity type; a semiconductor layer 12 of the first conductivity type; a field effect transistor (MOS) 200; and a Schottky barrier diode (SBD) 100. The semiconductor layer 12 is formed on the semiconductor substrate 11. The MOS 200 is formed using the semiconductor layer 12 and includes a trench gate electrode 22. The SBD 100 is formed using the semiconductor layer 12 and includes a metal electrode 33 and a low-concentration impurity layer 5. The metal electrode 33 is formed on the semiconductor layer 12. The low-concentration impurity layer 5 is formed on at least a part of a surface layer of the semiconductor layer 12 that overlaps with the metal electrode 33, and has a lower impurity concentration than the semiconductor layer 12.

Description

  The present invention relates to a semiconductor device in which an insulated gate field effect transistor and a Schottky barrier diode are formed on one chip, and a method for manufacturing the same.

  In a semiconductor chip having a synchronous rectification type DC / DC converter used in an electronic device such as a personal computer, a shot is applied to a power MOSFET (insulated gate field effect transistor, hereinafter abbreviated as MOS) for the purpose of suppressing power loss. A key barrier diode (hereinafter abbreviated as SBD) is integrated.

  For example, Patent Document 1 discloses a configuration in which Schottky regions and MOS regions are alternately arranged with a trench gate as a boundary. Patent Document 2 discloses that an epitaxial layer formed on a semiconductor substrate has a two-layer structure of a high-concentration epitaxial layer and a low-concentration epitaxial layer, and the boundary between the two layers is shallower than the trench gate. Is disclosed.

  In Patent Document 3, a drift layer shallower than the trench gate is formed to have a uniform width in order to achieve both low forward voltage (Vf) and low reverse leakage current (hereinafter abbreviated as leakage current). Is disclosed.

  Patent Document 4 describes that an impurity region located around the trench gate is formed at the boundary between the substrate and the epitaxial layer for the purpose of reducing the on-resistance of the vertical MOSFET.

JP 2006-210392A JP 2009-253139 A JP 2010-10583 A JP 2008-103378 A

  In the SBD formed on the same substrate as the power MOSFET, a low forward voltage (Vf) and a low reverse leakage current (hereinafter abbreviated as leakage current) in a trade-off relationship, taking into account the relationship with the on-resistance of the MOS. ) Is required. For this reason, when adjusting the forward voltage Vf while suppressing the leakage current in the reverse direction without affecting the on-resistance of the MOS, both of them are subtly without increasing the chip area and greatly narrowing the current path. It was necessary to devise a design degree of freedom so that it could be adjusted.

According to the present invention, a first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer formed on the semiconductor substrate;
A field effect transistor formed using the semiconductor layer;
A Schottky barrier diode formed using the semiconductor layer;
With
The field effect transistor is
A trench gate electrode formed in the semiconductor layer;
A source region formed in the semiconductor layer;
A first electrode formed on the source region;
A second electrode formed on a surface of the semiconductor substrate opposite to the semiconductor layer;
With
The Schottky barrier diode is
A metal electrode formed on the semiconductor layer;
A low-concentration impurity layer of a first conductivity type formed in at least a part of the semiconductor layer overlapping the metal electrode in plan view and having an impurity concentration lower than that of the semiconductor layer;
A semiconductor device is provided.

  According to the present invention, two regions having different forward voltages Vf are formed at the Schottky junction between the metal electrode and the semiconductor layer. The ratio of these two regions can be adjusted by adjusting the size and arrangement position of the low-concentration impurity layer. For this reason, it becomes easy to design the magnitude of the forward voltage Vf. Further, when the trench gate electrode is turned off, the depletion layer greatly extends downward in the portion of the low concentration impurity layer, so that the leakage current can be reduced. Furthermore, since the structure of the field effect transistor does not change, the on-resistance of the field effect transistor need not be affected.

According to the present invention,
Forming a first conductivity type semiconductor layer on a first conductivity type semiconductor substrate;
Forming a second conductivity type semiconductor region in a predetermined region of the semiconductor layer;
Forming a trench gate electrode in the semiconductor layer;
Forming a first conductivity type low-concentration impurity layer having a lower impurity concentration than the semiconductor layer by selectively introducing a second conductivity type impurity into the semiconductor layer;
Forming a source region in the semiconductor layer by selectively introducing a first conductivity type impurity into the semiconductor layer;
Forming a first electrode on the source region;
Forming a metal electrode in a region of the semiconductor layer overlapping the low-concentration impurity layer in plan view;
Forming a second electrode on a surface of the semiconductor substrate opposite to the semiconductor layer;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, when the forward voltage Vf is adjusted while suppressing the leakage current in the reverse direction without changing the on-resistance of the field effect transistor, it is possible to increase the degree of design freedom for fine adjustment of both.

(A) is sectional drawing of the semiconductor device which concerns on 1st Embodiment, (b) is a principal part perspective view of SBD. It is a figure explaining the manufacturing method of the semiconductor device shown in FIG. It is a figure explaining the manufacturing method of the semiconductor device shown in FIG. It is a figure explaining operation | movement of the semiconductor device shown in FIG. It is a figure explaining operation | movement of the semiconductor device shown in FIG. It is a principal part perspective view which shows the modification of FIG. (A) is sectional drawing of the semiconductor device which concerns on 2nd Embodiment, (b) is a principal part perspective view of SBD. (A) is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. 7, (b) is a figure which shows an impurity concentration profile, (c) is sectional drawing explaining operation | movement of a semiconductor device. . (A) is sectional drawing of the semiconductor device which concerns on 3rd Embodiment, (b) is a principal part perspective view of SBD. (A) is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. 9, (b) is sectional drawing explaining operation | movement of a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1A is a cross-sectional view showing the configuration of the semiconductor device 1 according to the first embodiment. FIG. 1B is a schematic perspective view for explaining the main part of FIG. The semiconductor device 1 includes a first conductivity type (for example, N type) semiconductor substrate 11, a first conductivity type semiconductor layer 12, a field effect transistor (hereinafter referred to as MOS) 200, and a Schottky barrier diode (hereinafter referred to as SBD). ) 100. The semiconductor layer 12 is formed on the semiconductor substrate 11. The MOS 200 is formed using the semiconductor layer 12 and has a trench gate electrode 22. The SBD 100 is formed using the semiconductor layer 12 and includes a metal electrode 33 and a low concentration impurity layer 5. The metal electrode 33 is formed on the semiconductor layer 12. The low concentration impurity layer 5 is formed on at least a part of the surface layer of the semiconductor layer 12 overlapping the metal electrode 33, and has an impurity concentration lower than that of the semiconductor layer 12. Details will be described below.

  In the semiconductor device 1, a plurality of MOSs 200 and a plurality of SBDs 100 are formed on the same semiconductor substrate 11 (for example, a silicon substrate). The MOSs 200 and the SBDs 100 are alternately arranged and share the semiconductor layer 12 (drift region). Specifically, the plurality of trench gate electrodes 22 extend parallel to each other. A MOS 200 is formed between the first trench gate electrode 22 and the second trench gate electrode 22, and an SBD 100 is formed between the second trench gate electrode 22 and the third trench gate electrode 22. . A MOS 200 is formed between the third trench gate electrode 22 and the fourth trench gate electrode 22. The first to fourth trench gate electrodes 22 are trench gate electrodes arranged adjacent to each other in this order. By repeating this, the MOS 200 and the SBD 100 are alternately arranged.

  The MOS 200 includes a gate insulating film 24, a trench gate electrode 22, a source region 31, a source electrode 35, and a drain electrode 39. The trench gate electrode 22 is embedded in the trench 21. The trench 21 is formed shallower than the semiconductor layer 12. The gate insulating film 24 is formed on the bottom and side surfaces of the trench 21.

  In the semiconductor layer 12 in which the MOS 200 is formed, a low-concentration second conductivity type (for example, P−) body region 41 is formed. The depth of the body region 41 is slightly shallower than the trench 21. A source region 31 and a contact region 32 are formed on the surface layer of the body region 41. The source region 31 is a first conductivity type (for example, N +), and the contact region 32 is a second conductivity type (for example, P +). The source electrode 35 is in contact with both the source region 31 and the contact region 32.

  The drain electrode 39 is formed on the surface of the semiconductor substrate 11 opposite to the semiconductor layer 12.

A low concentration impurity layer 5 is formed in the surface layer of the region where the SBD 100 is formed in the semiconductor layer 12. The low concentration impurity layer 5 is the same first conductivity type (for example, N type) as the semiconductor layer 12 and has an impurity concentration (N ⁻⁻ ) lower than that of the semiconductor layer 12. As shown in FIG. 1B, the low-concentration impurity layer 5 is selectively formed so as to divide the Schottky junction (that is, the junction surface between the metal electrode 33 and the semiconductor layer 12) in a direction perpendicular to the substrate surface. It is provided and extends parallel to the trench 21.

  Specifically, as shown in FIG. 1B, the low-concentration impurity layer 5 is formed in a stripe shape having a substantially semicircular cross section along the trench 21 at a substantially central position between the adjacent trenches 21 and 21. Is provided. The metal electrode 33 is also provided in a stripe shape along the trench 21. The low concentration impurity layer 5 has, for example, a diameter that is about half of the distance between the trenches 21 and 21. That is, the metal electrode 33 is in Schottky junction with the two semiconductor layers 12 and the low-concentration impurity layers 5 having different N-type impurity concentrations. Here, since the forward voltage Vf depends on the N-type impurity concentration of the semiconductor to which the Schottky junction is connected, the forward voltage Vf1 of the Schottky junction between the metal electrode 33 and the semiconductor layer 12 is the metal electrode 33 and the low concentration impurity layer. 5 is lower than the forward voltage Vf2 of the Schottky junction.

  In the example shown in FIG. 1A, the SBDs 100 and the MOSs 200 are alternately arranged, but the arrangement relationship between them is not limited to this. A thick silicon oxide film (not shown) may be provided at the bottom of the trench 21.

  2 and 3 are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1. First, as shown in FIG. 2A, a semiconductor layer 12 is formed on a semiconductor substrate 11 by epitaxial growth. Here, the semiconductor layer 12 is preferably formed by one-time epitaxial growth. Next, after a resist mask M1 having a predetermined pattern is formed, a second conductivity type impurity (for example, a P-type impurity such as boron) is introduced. Thereafter, a predetermined heat treatment is performed. Thereby, the body region 41 is formed. Here, in consideration of a process margin such as misalignment, the resist mask M1 is opened slightly larger.

  Next, after removing the resist mask M1, as shown in FIG. 2B, after forming a hard mask M2 and a resist mask M3 for forming a trench, a trench 21 is formed by dry etching.

  Next, after removing the resist masks M2 and M3, as shown in FIG. 2C, a gate insulating film 24 is formed using a thermal oxidation method. Thereafter, a polysilicon film containing impurities is deposited by the CVD method, and then etched back to form a trench gate electrode 22 inside the trench 21.

Next, as shown in FIG. 3D, after a predetermined resist mask M4 is formed, a P-type impurity (boron) is ion-implanted into the surface layer of the semiconductor layer 12. Thereafter, activation annealing is performed. As a result, an N ⁻⁻ type low concentration impurity layer 5 having an impurity concentration lower than that of the semiconductor layer 12 is formed. Here, the predetermined resist mask M4 is a mask having an opening pattern for forming the low-concentration impurity layer 5 having a desired size. The dose amount of the P-type impurity (boron) to be implanted is a dose amount that forms an N ⁻⁻ type low concentration impurity layer 5 by offsetting the N type impurity in the N ⁻ semiconductor layer 12.

  Next, after removing the resist mask M4, as shown in FIG. 3E, a predetermined resist mask (not shown) is formed, and then ion implantation and heat treatment are performed on the body region 41 to form the source region 31 and the contact. Regions 32 are formed respectively.

  Thereafter, an interlayer insulating film (not shown) or the like is formed, and finally, a source electrode 35, a metal electrode 33, and a drain electrode 39 are formed, whereby the semiconductor device 1 shown in FIG.

  The above manufacturing method is an example, and the present invention is not limited to this. Needless to say, various modifications may be made without departing from the gist of the present invention.

  Next, operation of the semiconductor device illustrated in FIG. 1 will be described with reference to FIGS. As shown in FIG. 4A, when a turn-on voltage is applied to the trench gate electrode 22 in a state where a predetermined voltage is applied between the drain electrode 39 and the source electrode 35, the channel generated in the body region 41 is drained in the MOS 200. A current flows (indicated by a broken line arrow in FIG. 4A).

  On the other hand, in the SBD 100, a voltage is applied between the metal electrode 33 and the drain electrode 39, but a current flows through an accumulation region formed in a region of the semiconductor layer 12 facing the metal electrode 33. In the surface layer of the SBD 100, more current flows on both low-resistance sides where the low-concentration impurity layer 5 does not exist (indicated by broken-line arrows in FIG. 4A).

  Also, as shown in FIG. 4B, the back electromotive current that flows during the dead time after gate-off flows through the SBD 100 having lower forward voltages Vf1 and Vf2 than the body diode (MOS PN junction). Further, the SBD 100 flows through a Schottky junction portion (a junction portion between the metal electrode 33 and the semiconductor layer 12) having a lower forward voltage Vf1 (<Vf2). (Indicated by a broken line arrow in FIG. 4B).

  Here, since the semiconductor layer 12 responsible for the main current path (excluding the low-concentration impurity layer 5) is composed of a single epitaxial layer, it has excellent uniformity of impurity concentration in the depth direction and crystal defects. Low resistance and low leakage current.

  Further, in a state where a predetermined voltage is applied between the drain electrode 39 and the source electrode 35 and the trench gate electrode 22 is turned off, in the comparative example shown in FIG. 5B (the low concentration impurity layer 5 is not provided). The depletion layer (indicated by a broken line in the figure) extends relatively uniformly and flatly from the Schottky junction, but in this embodiment, the depletion occurs in the low-concentration impurity layer 5 as shown in FIG. The layer greatly extends downward, and the breakdown voltage is improved correspondingly, and the leakage current can be reduced.

  Next, the operation and effect of this embodiment will be described. In this embodiment, the low concentration impurity layer 5 is selectively provided in the semiconductor layer 12 functioning as the SBD 100. For this reason, two regions having different forward voltages Vf are formed in the Schottky junction between the metal electrode 33 and the semiconductor layer 12. The ratio of these two regions can be adjusted by adjusting the size and arrangement position of the low concentration impurity layer 5. For this reason, it becomes easy to design the magnitude of the forward voltage Vf. In other words, by changing the area ratio of the low-concentration impurity layer 5 to the semiconductor layer 12, the design can be adjusted to a desired forward voltage Vf and leakage current. Accordingly, the degree of freedom in designing fine adjustment between the low forward voltage Vf and the low leakage current, which are in a trade-off relationship, is increased, and it is easy to achieve both. Further, since the structure of the MOS 200 does not change, the on-resistance of the MOS 200 need not be affected.

  Further, since the low concentration impurity layer 5 has the same conductivity type as the semiconductor layer 12, the current path is not narrowed. The low-concentration impurity layer 5 and the semiconductor layer 12 are both of low resistance and low leakage current because they are made of an epitaxial layer having excellent impurity concentration uniformity and few crystal defects. Further, since a region having a conductivity type opposite to that of the semiconductor layer 12 is not provided in the semiconductor layer 12, the current path is not reduced. For this reason, it can suppress that a semiconductor chip enlarges.

  Further, the epitaxial growth requiring a high temperature and a long time is only once, which is advantageous in terms of production efficiency. Further, since the low-concentration impurity layer 5 formed by ion implantation is partial, a decrease in impurity concentration uniformity and an increase in crystal defects are suppressed.

  In the example shown in FIG. 1, the configuration example in which only one low concentration impurity layer 5 and one metal electrode 33 are provided in a stripe shape between the trenches 21 and 21 has been described. However, the present invention is not limited to this. For example, in one Schottky barrier diode, a plurality of low concentration impurity layers 5 may be provided apart from each other. Specifically, as shown in FIG. 6A, a plurality (two in the figure) may be provided between the trenches 21 and 21. Further, as shown in FIG. 6B, the low concentration impurity layer 5 may be provided intermittently in an island shape. This makes it easier to adjust the ratio of Schottky junctions having different forward voltages Vf1, Vf2.

(Second Embodiment)
7 and 8 are diagrams illustrating the configuration of the semiconductor device 2 according to the second embodiment. Specifically, FIG. 7A is a cross-sectional view of the semiconductor device 2, and FIG. 7B is a perspective view of a main part of the SBD 100. FIG. 8A is a cross-sectional view illustrating a method for manufacturing the semiconductor device 2, and FIG. 8B is a diagram illustrating an impurity concentration profile. FIG. 8C is a cross-sectional view for explaining the operation of the semiconductor device 2. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 2 according to the present embodiment is the same as the semiconductor device 1 according to the first embodiment except for the following points. As shown in FIGS. 7A and 7B, the low-concentration impurity layer 5 is provided at a certain deep position (depth d) from the surface of the semiconductor layer 12. The low-concentration impurity layer 5 is provided shallower than the trench 21, for example, at a position about half the depth of the trench 21.

  As shown in FIG. 8A, in the method of manufacturing the semiconductor device 2, in the step of forming the low-concentration impurity layer 5 described in the first embodiment with reference to FIG. ) Is deeply implanted at a high acceleration energy from the substrate surface, and is the same as in the first embodiment except that activation annealing is performed at a predetermined temperature.

  Since the semiconductor layer 12 made of an epitaxial layer has a uniform first conductivity type impurity concentration in the depth direction, the second conductivity type impurity concentration (for example, boron concentration) cancels out the first conductivity type impurity. As shown in FIG. 8 (b), the profile is gradually increased from the surface of the semiconductor layer 12 so that the profile has a peak concentration at a predetermined depth d, so that the peak position (depth d) is the highest. The first conductivity type impurities are offset. For convenience, in FIG. 7A, the low-concentration impurity layer 5 is positioned away from the surface of the semiconductor layer 12, but the second conductivity type impurity is also implanted into a shallow region near the surface of the semiconductor layer 12 during ion implantation. The However, the amount of offset at the peak position (depth d) is larger than the amount of offset near the surface of the semiconductor layer 12, and apparently the low-concentration impurity layer 5 is provided at a certain deep position d from the surface of the semiconductor layer 12. It will be.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, as shown in FIG. 8C, the depletion layer (indicated by a broken line in the figure) extending from the Schottky junction on the surface of the semiconductor layer 12 has a low concentration impurity layer 5 having a peak position at the depth d. Since the elongation is promoted in this portion, the breakdown voltage of the semiconductor device is improved and the leakage current can be reduced. The depth of the depletion layer can also be adjusted by adjusting the depth of the low-concentration impurity layer 5.

(Third embodiment)
9 and 10 are diagrams illustrating the configuration of the semiconductor device 3 according to the third embodiment. Specifically, FIG. 9A is a cross-sectional view of the semiconductor device 3, and FIG. 9B is a perspective view of a main part of the SBD 100. FIG. 10A is a cross-sectional view illustrating a method for manufacturing the semiconductor device 3, and FIG. 10B is a cross-sectional view illustrating the operation of the semiconductor device 3. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 3 according to the present embodiment is the same as the semiconductor device 2 according to the second embodiment except for the following points. As shown in FIGS. 9A and 9B, the low-concentration impurity layer 5 is disposed opposite to a deep position in contact with the side wall of the trench 21.

  In such a semiconductor device 3, as shown in FIG. 10A, the opening pattern of the implantation mask M4 used in the step of FIG. It is only necessary to change to the mask M5 having a mask pattern provided at a position in contact with the side wall of the trench 21 after implementation.

  According to this embodiment, the same effect as that of the second embodiment can be obtained. Further, as shown in FIG. 10B, since the depletion layer at the corner TC at the bottom of the trench 21 where electric field is likely to concentrate can be easily extended, the occurrence of dielectric breakdown at the corner TC of the trench 21 can be suppressed. The depth position of the low-concentration impurity layer 5 is more desirable for dielectric breakdown as it is closer to the trench corner TC, but may be provided near the surface layer of the semiconductor layer 12 from the viewpoint of easy ion implantation.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 3 Semiconductor device 5 Low concentration impurity layer 11 Semiconductor substrate 12 Semiconductor layer 21 Trench 22 Trench gate electrode 24 Gate insulating film 31 Source region 32 Contact region 33 Metal electrode 35 Source electrode 39 Drain electrode 41 Body region 100 Shot Key barrier diode (SBD)
200 Field Effect Transistor (MOS)

Claims (9)

A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer formed on the semiconductor substrate;
A field effect transistor formed using the semiconductor layer;
A Schottky barrier diode formed using the semiconductor layer;
With
The field effect transistor is
A trench gate electrode formed in the semiconductor layer;
A source region formed in the semiconductor layer;
A first electrode formed on the source region;
A second electrode formed on a surface of the semiconductor substrate opposite to the semiconductor layer;
With
The Schottky barrier diode is
A metal electrode formed on the semiconductor layer;
A low-concentration impurity layer of a first conductivity type formed in at least a part of the semiconductor layer overlapping the metal electrode in plan view and having an impurity concentration lower than that of the semiconductor layer;
A semiconductor device comprising: The semiconductor device according to claim 1,
The low concentration impurity layer is a semiconductor device formed in a surface layer of the semiconductor layer. The semiconductor device according to claim 1,
The low-concentration impurity layer is a semiconductor device formed at a position away from the surface of the semiconductor layer in the depth direction. The semiconductor device according to claim 1,
The semiconductor device in which the low concentration impurity layer is in contact with a side surface of a trench in which the trench gate electrode is embedded. In the semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which a plurality of the low-concentration impurity layers are provided apart from each other in one Schottky barrier diode. In the semiconductor device according to any one of claims 1 to 5,
A semiconductor device in which the field effect transistor and the Schottky barrier diode are alternately arranged. Forming a first conductivity type semiconductor layer on a first conductivity type semiconductor substrate;
Forming a second conductivity type semiconductor region in a predetermined region of the semiconductor layer;
Forming a trench gate electrode in the semiconductor layer;
Forming a first conductivity type low-concentration impurity layer having a lower impurity concentration than the semiconductor layer by selectively introducing a second conductivity type impurity into the semiconductor layer;
Forming a source region in the semiconductor layer by selectively introducing a first conductivity type impurity into the semiconductor layer;
Forming a first electrode on the source region;
Forming a metal electrode in a region of the semiconductor layer overlapping the low-concentration impurity layer in plan view;
Forming a second electrode on a surface of the semiconductor substrate opposite to the semiconductor layer;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 7,
The semiconductor layer, the semiconductor region, the trench gate electrode, the source region, the first electrode, and the second electrode constitute a vertical insulated gate field effect transistor, and the semiconductor layer and the metal electrode are shot. A method of manufacturing a semiconductor device constituting a key barrier diode. In the manufacturing method of the semiconductor device according to claim 7 or 8,
A method of manufacturing a semiconductor device, wherein the semiconductor layer is formed by only one epitaxial growth.

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