JP2012088996A - Memory control method, memory control device and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control method for efficiently executing serial-parallel conversion and parallel-serial conversion.SOLUTION: A line memory for storing line data before image processing and a line memory for storing line data after image processing are comprised of the same cells and controlled by four kinds of timing consisted of pre-processing memory input timing to store line data inputted in a serial data format into the line memory, pre-processing memory output timing to read out the stored line data before processing in a parallel data format, post-processing memory input timing to store line data in the parallel data format after processing into the line memory, and post-processing memory output timing to read out the stored line data after processing in the serial data format. Within the same line term, the post-processing memory input timing is executed just after the pre-processing memory output timing, and within the same line term, the pre-processing memory input timing is executed just after the post-processing memory output timing.

Description

  The present invention relates to a memory control method, a memory control device, and an image forming apparatus, and more particularly to an improvement in processing between serial data and parallel data.

  Various circuits exist in an electronic device, and digital data is transmitted between the circuits as a serial data format, that is, as a one-dimensional bit stream. In each circuit, various signal processing may be performed by converting digital data into a two-dimensional array. For this reason, a circuit that converts serial data into parallel data or a circuit that converts parallel data into serial data may be used.

  Further, in an image processing apparatus and an image forming apparatus that handle a two-dimensional image, image reading (scanning) and image output (printing) handle a two-dimensional image by repeating one-dimensional processing. Further, serial data is transmitted between the processing circuits.

  On the other hand, in image processing and image storage, it is often convenient to handle as two-dimensional data. For this reason, a circuit for converting serial data into parallel data and a circuit for converting parallel data into serial data are required.

  For example, when image processing is performed on two-dimensional image data, line data input as serial data is blocked for each predetermined number of lines for the image processing apparatus 200 to form a “data line block”. The pre-processing memory control device 100A that executes control to be input to the image processing device and the data line block that is processed and output by the image processing device are decomposed into line data for each line, converted back to serial data, and output The post-processing memory control device 100B that executes the control to perform the control is separately controlled (see FIG. 5).

  In this case, a pre-processing memory control device 100A as a data line block generation (serial-parallel conversion) circuit using the line memories 111A to 113A is arranged on the input side of the image processing device 200, and the output side of the image processing device 200 is used. The post-processing memory control device 100B as a data line block decomposition (parallel-serial conversion) circuit using the line memories 111B to 113B is arranged.

  Note that the data line block generation (serial-parallel conversion) circuit and the data line block decomposition (parallel-serial conversion) circuit described above overlap even though they have the same type of circuit configuration using the same number of line memories. Since different processing is necessary for the timing, the memory capacity could not be reduced without performing control separately.

  A technique for reducing the memory capacity is described in Patent Document 1 below.

JP 2003-288268 A

  The above-described data line block generation circuit and data line block decomposition circuit have the same type of circuit configuration using the same number of line memories, and it is necessary to reduce the memory capacity when integrating the circuits. As a result, the memory capacity could not be reduced.

  Further, in the above-described Patent Document 1, the memory is managed as a plurality of surfaces, and efficient memory control is executed by managing the addresses of the vacant surfaces. However, in a circuit configuration in which a data line block generation circuit using a line memory is arranged on the input side of the image processing apparatus and a data line block decomposition circuit using a line memory is arranged on the output side of the image processing apparatus. In the operation state where various timings overlap, there is a problem that the control of Patent Document 1 cannot be applied as it is.

  The present invention has been made in view of the above problems, and a memory control method and a memory capable of efficiently using a line memory in a serial-parallel conversion circuit and a parallel-serial conversion circuit using a line memory. An object is to provide a control device and an image forming apparatus.

  The present invention for solving the above-described problems is as follows.

  (1) According to the first aspect of the present invention, line data for a plurality of lines input in a serial data format is stored in a plurality of line memories, and a plurality of lines are simultaneously read out to be converted into a data line block in a parallel data format. The line data in the parallel data format processed as data line blocks by the image processing device is stored in a plurality of line memories and sequentially read out to the line data for a plurality of lines in the serial data format. A memory control method for converting and outputting, wherein the line memory for storing line data before processing by the image processing apparatus and the line memory for storing line data after processing by the image processing apparatus are the same line The line data configured by a memory and inputted in the serial data format is Pre-processing / memory input timing stored in the memory, pre-processing line data stored in the line memory in pre-processing / memory output timing, parallel data format after processing in the image processing apparatus Four timings are processed in the line memory: after processing to store the line data in the line memory / memory input timing, and after processing to read out the processed line data stored in the line memory in the serial data format / memory output timing When the control is performed, control is performed so that the pre-processing / memory input timing is executed immediately after the memory output timing within the same line cycle, and the post-processing / memory output timing is controlled within the same line cycle. Immediately after that, pre-processing / memory input timing is executed. To a memory control method characterized by.

  (2) The invention of claim 2 controls to execute the pre-processing / memory input timing within the same line cycle immediately before the processing / memory output timing based on different timing signals within the same line cycle, A write cycle is determined after a read cycle within the same line cycle, and control is performed so that the pre-processing / memory input timing is executed within the same line cycle immediately after processing / memory output timing. The memory control method according to Item 1.

  (3) According to the invention of claim 3, line data for a plurality of lines inputted in a serial data format is stored in a plurality of line memories, and the data for a plurality of lines is read out simultaneously to be converted into a data line block in a parallel data format. The line data in the parallel data format processed as data line blocks by the image processing device is stored in a plurality of line memories and sequentially read out to the line data for a plurality of lines in the serial data format. A memory control device for converting and outputting, wherein the line memory for storing line data before processing by the image processing device and the line memory for storing line data after processing by the image processing device are the same line The line data configured by a memory and inputted in the serial data format is Pre-processing / memory input timing stored in the memory, pre-processing line data stored in the line memory in pre-processing / memory output timing, parallel data format after processing in the image processing apparatus Four timings are processed in the line memory: after processing to store the line data in the line memory / memory input timing, and after processing to read out the processed line data stored in the line memory in the serial data format / memory output timing A control unit for controlling, the control unit controls to execute the post-processing and memory input timing immediately before the processing and memory output timing within the same line cycle, and within the same line cycle, After processing / immediately after memory output timing, before processing / memory input timing Performs control to execute the grayed, it is a memory control device according to claim.

  (4) In the invention according to claim 4, the control section executes the pre-processing / immediately after the memory output timing and the post-processing / memory input timing within the same line period based on different timing signals within the same line period. In addition, the write cycle is determined after the read cycle within the same line cycle, and the control is performed so that the pre-processing / memory input timing is executed within the same line cycle immediately after the processing / memory output timing. The memory control device according to claim 3.

  (5) The invention of claim 5 is an image forming apparatus comprising the memory control device of claim 3 or claim 4.

  In the above invention, line data for a plurality of lines input in a serial data format is stored in a plurality of line memories, and simultaneously read out for a plurality of lines, thereby converting the data into a data line block in a parallel data format and transferring it to the image processing apparatus. At the same time, the line data in the parallel data format processed as the data line block by the image processing apparatus is stored in a plurality of line memories and sequentially read out to be converted into line data for a plurality of lines in the serial data format and output. In memory control, a line memory that stores line data before processing by the image processing apparatus and a line memory that stores line data after processing by the image processing apparatus are configured by the same line memory, and are input in a serial data format. Stores line data in line memory Before processing to read line data before processing stored in line memory in parallel data format, memory output timing, after processing to store line data in parallel data format after processing by image processing device in line memory, memory input When controlling 4 timings of the timing and the processed line data stored in the line memory in the serial data format, and the memory output timing, the pre-processing and memory within the same line cycle. Control is performed to execute the post-processing / memory input timing immediately after the output timing, and control is performed to execute the pre-processing / memory input timing immediately after the processing / memory output timing within the same line period.

  For this reason, the above-described data line block generation (serial-parallel conversion) circuit and data line block decomposition (parallel-serial conversion) circuit can be processed differently at the same timing using the same line memory. That is, the line memory can be efficiently arranged and used in the serial-parallel conversion circuit and the parallel-serial conversion circuit using the line memory.

  In addition, such an efficient arrangement of the line memories can reduce the memory capacity as compared with the prior art, and is suitable for integration.

It is a block diagram which shows schematic structure of embodiment of this invention. It is a block diagram which shows the principal part of embodiment of this invention. It is a time chart which shows operation | movement of embodiment of this invention. It is a time chart which shows operation | movement of embodiment of this invention. It is a block diagram which shows the conventional schematic structure.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments (embodiments) for carrying out a memory control method, a memory control device, and an image forming apparatus of the present invention will be described below in detail with reference to the drawings. Here, the embodiment will be described by taking a memory control device cooperating with the image processing device, an image forming device including the memory control device, and an operation (memory control method) of the memory control device as specific examples.

[Configuration of memory controller]
Here, the configuration of the memory control device 100 of the first embodiment will be described in detail with reference to FIG. The memory control apparatus 100 is used together with the image processing apparatus 200 and can be applied to an image forming apparatus. Note that the memory control apparatus 100 according to the present embodiment is applicable to each unit related to image processing in the image forming apparatus, and thus a specific configuration on the image forming apparatus side is omitted.

  A memory control device 100 shown in FIG. 1 includes a memory control unit 101 that controls each unit, and a line memory group 110 that can store line data for a plurality of lines input in a serial data format. The line memory group 110 includes a line memory 111 capable of storing line data for one line, a line memory 112 capable of storing line data for one line, and a line memory 113 capable of storing line data for one line. , And is configured. Although a line memory for three lines is used here, the number is not limited to this.

  Here, under the control of the memory control unit 101, the memory control device 100 stores the data in the line memory group 110 and simultaneously reads a plurality of lines, thereby converting the data into a data line block in a parallel data format and sending it to the image processing device 200. At the same time, the line data in the parallel data format processed as the data line block by the image processing apparatus 200 is stored for a plurality of lines, and then each line is sequentially read to convert the line data for a plurality of lines in the serial data format. The memory control to output is possible.

  The line memories 111 to 113 used in this embodiment have, for example, a 32-bit 2048 word, one address bus A, and a negative logic write enable WEN as shown in FIG. When the write enable WEN is invalid, the data of the address specified by the address bus A is output to the output data bus Q. When the write enable WEN is valid, the address specified by the address bus A is specified by the input data bus D. This is a single-port SDRAM (Synchronous Dynamic Random Access Memory) to which data is written. Note that the present invention is not limited to the SDRAM as long as the same operation is possible.

  In this embodiment, the write cycle and the read cycle are determined once every four clocks, and further, the four clocks are time-divided every two clocks, the first half is assigned to the read cycle, and the second half is assigned to the write cycle.

  In addition, before the line memory 111 to 113 stores the line data input in the serial data format as the horizontal synchronization signal (H-Valid) used when writing or reading the data for one line in the line memory. -Pre-processing input horizontal synchronization signal HVI (H-Valid_Input: Fig. 4 (a)) and pre-processing line data stored in the line memories 111 to 113 are read as parallel data format data line blocks. Pre-memory output timing pre-processing output horizontal synchronization signal GHVO (Graphic_H-Valid_Output: FIG. 4B), post-processing to store line data in parallel data format after processing by the image processing apparatus 200 in the line memories 111 to 113・ After processing memory input timing, input horizontal sync signal GHVI (Graphic_H-Valid_Input: FIG. 4C), line memo After the processing of reading out the processed line data stored in 111 to 113 in the serial data format and after the processing of the memory output timing, the output horizontal synchronization signal HVO (H-Valid_Output: FIG. 4 (d)) is the four timing horizontal synchronization. A signal is present.

  Then, as shown in FIG. 4, the memory control unit 101 makes the rise timings different in the order of HVI, GHVO, GHVI, and HVO within the same line period (within a period for processing data for one line). Is set.

  In this embodiment, line data before image processing by the image processing apparatus 200 is referred to as “pre-processing line data”, and line data after image processing by the image processing apparatus 200 is “post-processing line data”. I will call it.

  That is, the pre-process line data input in the serial data format is stored in the line memories 111 to 113 in synchronization with the pre-process input horizontal synchronization signal HVI at the pre-process / memory input timing. The pre-processing line data stored in the data is adjusted to the pre-processing output horizontal synchronization signal GHVO at the pre-processing / memory output timing to be read and output from the line memories 111 to 113 as data line blocks in a parallel data format. The processed line data in the parallel data format processed by the image processing device 200 is stored in the line memories 111 to 113 in synchronization with the processed input horizontal synchronization signal GHVI at the processed / memory input timing. The post-processing line data stored in 111 to 113 is adjusted to the post-processing output horizontal synchronization signal HVO at the post-processing / memory output timing and output in a serial data format.

  Further, the memory control unit 101 controls each of the three line memories 111 to 113 as a FIFO (First In, First Out) type line memory. A predetermined number of continuous data strings included in the line data for one line is written to or read from a continuous address of the SDRAM, thereby controlling as a line memory.

[Operation of memory controller]
The operation of the present embodiment will be described below with reference to the time chart of FIG. The time chart of FIG. 3 shows an outline of a control method for the three line memories 111 to 113 of the present embodiment. The following control is based on the control of the memory control unit 101. However, in order to avoid redundant expressions, the description of “by control of the memory control unit 101” may be omitted.

  FIG. 3A shows an index signal for each horizontal period, and FIG. 3B shows line data numbers starting from zero.

  First, the 0th pre-process line data is written to the line memory 111 in synchronization with the pre-process input horizontal synchronization signal HVI (FIG. 3 (d) 0), and the next first pre-process line data is pre-process input horizontal synchronization. Writing to the line memory 112 in synchronization with the signal HVI (FIG. 3 (e) 1), and further writing the next second pre-processing line data to the line memory 113 in synchronization with the pre-processing input horizontal synchronization signal HVI (FIG. 3). (F) 2).

  Then, in synchronization with the pre-processing input horizontal synchronization signal HVI (FIG. 3 (j) 3) of the next third line data, the 0th pre-processing line data is transferred from the line memory 111 (FIG. 3 (g) 0). The first pre-process line data is read from the line memory 112 (FIG. 3 (h) 1), the second pre-process line data is read from the line memory 113 (FIG. 3 (i) 2), and the 4-parallel data format is read. The data line block is formed, adjusted to the pre-processing output horizontal synchronization signal GHVO, and output from the memory control device 100 to the image processing device 200.

  Here, predetermined image processing is executed by the image processing apparatus 200, and data line blocks corresponding to four processed line data are output from the image processing apparatus 200 within the same line cycle, and the processed input horizontal synchronization signal GHVI is output. Synchronously input to the memory control device 100.

  Here, the first 0th processed line data is output to the outside in synchronization with the processed output horizontal synchronization signal HVO within the same line period (FIG. 3 (c) 0).

  The first processed line data is stored in the line memory 111 (FIG. 3 (d) 1), the second processed line data is stored in the line memory 112 (FIG. 3 (e) 2), and the third processed process is performed. The subsequent line data is written in the line memory 113 (FIG. 3 (f) 3) within the same line period.

  Here, in the line memory 111, the 0th line data is read and the 1st line data is written immediately after the same line period (FIG. 3 (g) 0, (d) 1). Similarly, in the line memory 112, the first line data is read, and the second line data is written immediately after the same line period (FIG. 3 (h) 1, (e) 2). Similarly, the line memory 113 reads the second line data and writes the third line data immediately after the same line period (FIGS. 3 (i), (f) 3).

  A read cycle for reading the data line blocks of the four pre-processing line data from No. 0 to No. 3 from the respective line memories 111 to 113 is activated by the pre-processing input horizontal synchronization signal HVI. The write cycle for writing the data line blocks of the four processed line data from No. 0 to No. 3 to the respective line memories 111 to 113 is started by the processed horizontal sync signal GHVI. Here, since the post-processing input horizontal synchronization signal GHVI is provided with a predetermined amount of delay with respect to the pre-processing input horizontal synchronization signal HVI (see FIG. 4), the line data of the same line memory within the same line period. Can be read and written.

  The first post-processing line data written in the line memory 111 is read out within the next line cycle and output to the outside as serial data (FIG. 3 (g) 1). Then, the fourth pre-processing line data is written in the same line cycle (FIG. 3 (d) 4). Here, in the line memory 111, the first post-processing line data is read, and immediately after that, the fourth pre-processing line data is written. Here, the write cycle in which the fourth pre-process line data is written to the line memory 111 is activated by the pre-process input horizontal synchronization signal HVI. Therefore, the read cycle for reading the first post-processing line data from the line memory 111 must be started before the write cycle to the line memory 111 starts. Therefore, a read cycle for reading the first post-process line data from the line memory 111 is activated by the pre-process input horizontal synchronization signal HVI. In the same line cycle, the read cycle is set to be executed before the write cycle. Then, the first processed line data read from the line memory 111 is adjusted to the processed output horizontal synchronization signal HVO and output. By reading the first post-process line data in the read cycle activated by the pre-process input horizontal synchronization signal HVI, and then writing the fourth pre-process line data in the write cycle activated by the pre-process input horizontal synchronization signal HVI It becomes possible to read and write line data in the same line memory within the same line period.

  The second post-processing line data written in the line memory 112 is read out within the next line cycle and output to the outside as serial data (FIG. 3 (h) 2). Then, the fifth pre-process line data is written in the same line cycle (FIG. 3 (e) 5). Here, in the line memory 112, the second post-process line data is read, and immediately after that, the fifth pre-process line data is written. Here, the fifth write cycle for writing the pre-process line data to the line memory 112 is activated by the pre-process input horizontal synchronization signal HVI. Therefore, the read cycle for reading the second post-processing line data from the line memory 112 must be started before the write cycle to the line memory 112 starts. Therefore, a read cycle for reading the second post-process line data from the line memory 112 is activated by the pre-process input horizontal synchronization signal HVI. In the same line cycle, the read cycle is set to be executed before the write cycle. Then, the second processed line data read out from the line memory 112 is adjusted to the processed output horizontal synchronization signal HVO and output. By reading the second post-process line data in the read cycle activated by the pre-process input horizontal synchronization signal HVI, and then writing the fifth pre-process line data in the write cycle activated by the pre-process input horizontal synchronization signal HVI It becomes possible to read and write line data in the same line memory within the same line period.

  The third post-processing line data written in the line memory 113 is read out within the next line cycle and output to the outside as serial data (FIG. 3 (i) 3). Then, the sixth pre-processing line data is written in the same line cycle (FIG. 3 (f) 6). Here, in the line memory 113, the third post-processing line data is read, and immediately after that, the sixth pre-processing line data is written. Here, the write cycle for writing the sixth pre-process line data to the line memory 113 is started by the pre-process input horizontal synchronization signal HVI. Therefore, the read cycle for reading the third post-processing line data from the line memory 113 must be started before the write cycle to the line memory 113 starts. Therefore, a read cycle for reading the third post-process line data from the line memory 113 is activated by the pre-process input horizontal synchronization signal HVI. In the same line cycle, the read cycle is set to be executed before the write cycle. Then, the third post-processing line data read from the line memory 113 is adjusted to the post-processing output horizontal synchronization signal HVO and output. By reading the third post-process line data in the read cycle activated by the pre-process input horizontal synchronization signal HVI, and then writing the sixth pre-process line data in the write cycle activated by the pre-process input horizontal synchronization signal HVI It becomes possible to read and write line data in the same line memory within the same line period.

  Thereafter, control is performed so that the post-processing / memory input timing is executed before processing / immediately after the memory output timing within the same line cycle, and the processing is performed after processing / immediately after memory output timing within the same line cycle. The procedure of controlling to execute the previous / memory input timing is repeated for all the line data.

  Note that the memory control device 100 described above integrally controls the control of the line memory on the input side and the control of the line memory on the output side for the various signal processing devices such as the image processing device 200. It is a device to do.

  In line memory control on the input side (before processing), line data input in a serial data format is converted into a data line block in a parallel data format and output. In the line memory control on the output side (after processing), the data line block in the parallel data format is disassembled, converted into line data in the serial data format, and output.

  The pre-processing line data is input in synchronization with the pre-processing input horizontal synchronization signal HVI, and the parallel data format data line block is adjusted to the pre-processing output horizontal synchronization signal GHVO and output. On the other hand, the processed line data is input as a data line block in synchronization with the processed input horizontal synchronization signal GHVI, and the data line block is disassembled and the line data changed to the serial data format is adjusted to the processed horizontal synchronization signal HVO. And output.

  Further, the specific description of FIG. 3 described above is replaced with constants as follows. Here, the number of line memories is n (n is a positive integer), the number of line data is k (k is a positive integer), and the number of data line blocks is n + 1.

  The read cycle for reading the data line blocks of the k + 1 to k + nth n + 1 preprocessed line data from the respective line memories is activated by the preprocessed input horizontal synchronization signal HVI. Further, the write cycle for writing the data line block of the k + 1 to k + nth n + 1 post-processing line data to each line memory is started by the post-processing input horizontal synchronization signal GHVI. Here, since the post-processing input horizontal synchronization signal GHVI is provided with a predetermined amount of delay with respect to the pre-processing input horizontal synchronization signal HVI (see FIG. 4), the line data of the same line memory within the same line period. Can be read and written.

  The k-th processed line data written in the line memory is read out within the next line cycle and output to the outside as serial data. Then, the k + n-th pre-process line data is written in the same line cycle. Here, in the line memory, the k-th post-processing line data is read, and immediately after that, the k + n-th pre-processing line data is written. Here, the write cycle for writing the (n + 1) th pre-process line data to the line memory is activated by the pre-process input horizontal synchronization signal HVI. Therefore, the read cycle for reading the first post-processing line data from the line memory 111 must be started before the write cycle to the line memory 111 starts. Therefore, a read cycle for reading the kth post-process line data from the line memory is activated by the pre-process input horizontal synchronization signal HVI. In the same line cycle, the read cycle is set to be executed before the write cycle. Then, the k-th processed line data read from the line memory is adjusted to the processed output horizontal synchronization signal HVO and output. By reading the kth post-process line data in the read cycle activated by the pre-process input horizontal synchronization signal HVI, and then writing the k + nth pre-process line data in the write cycle activated by the pre-process input horizontal synchronization signal HVI It becomes possible to read and write line data in the same line memory within the same line period.

  According to the embodiment described above, different processing can be performed at overlapping timings using the same line memory for data line block generation (serial-parallel conversion) and data line block decomposition (parallel-serial conversion). Become. That is, the line memory can be efficiently arranged and used in the serial-parallel conversion circuit and the parallel-serial conversion circuit using the line memory. In addition, such an efficient arrangement of the line memories can reduce the memory capacity as compared with the prior art, and is suitable for integration.

[Other Embodiments]
Various modifications can be made to the specific examples used in the description of the above embodiment, and the present invention is not limited to the specific examples used in the description.

  Further, the above embodiment can be applied to various image processing apparatuses and image forming apparatuses.

DESCRIPTION OF SYMBOLS 100 Memory control apparatus 101 Memory control part 110 Line memory group 111-113 Line memory 200 Image processing apparatus

Claims (5)

A plurality of lines of line data input in a serial data format are stored in a plurality of line memories, and a plurality of lines are simultaneously read out to be converted into parallel data format data line blocks and sent to an image processing apparatus. A memory control method in which parallel data format line data processed as data line blocks by a processing device is stored in a plurality of line memories and sequentially read out to be converted into serial data format line data and output. And
The line memory for storing line data before processing by the image processing apparatus and the line memory for storing line data after processing by the image processing apparatus are configured by the same line memory,
Pre-processing / memory input timing for storing the line data input in the serial data format in the line memory, pre-processing / memory output timing for reading the pre-processing line data stored in the line memory in the parallel data format The line data in the parallel data format after being processed by the image processing apparatus is stored in the line memory after processing, the memory input timing, and the line data after processing stored in the line memory is read in the serial data format When controlling the 4 timings after processing and memory output timing for the line memory,
In the same line cycle, control is performed so that the pre-processing / immediately after memory output timing and post-processing / memory input timing are executed, and within the same line cycle, post-processing / immediately after memory output timing, before processing / memory input Control to execute timing,
And a memory control method. Based on the different timing signals within the same line period, control to execute the memory input timing before processing and immediately after the memory output timing within the same line period,
A write cycle is determined after a read cycle within the same line cycle, and control is performed so that the pre-processing / memory input timing is executed within the same line cycle immediately after processing / memory output timing.
The memory control method according to claim 1. A plurality of lines of line data input in a serial data format are stored in a plurality of line memories, and a plurality of lines are simultaneously read out to be converted into parallel data format data line blocks and sent to an image processing apparatus. A memory control device that converts line data of parallel data format processed as data line blocks by a processing device into a plurality of line memories and sequentially reads the data into line data of a plurality of lines in a serial data format and outputs the data. And
The line memory for storing line data before processing by the image processing apparatus and the line memory for storing line data after processing by the image processing apparatus are configured by the same line memory,
Pre-processing / memory input timing for storing the line data input in the serial data format in the line memory, pre-processing / memory output timing for reading the pre-processing line data stored in the line memory in the parallel data format The line data in the parallel data format after being processed by the image processing apparatus is stored in the line memory after processing, the memory input timing, and the line data after processing stored in the line memory is read in the serial data format It has a control unit that controls the 4 timings after processing and memory output timing for the line memory,
The control unit controls to execute the post-processing / memory input timing before processing / immediately after the memory output timing within the same line cycle, and after the processing / immediately after memory output timing within the same line cycle. Control to execute pre-processing / memory input timing,
A memory control device. The control unit performs control so that the post-processing / memory input timing is executed within the same line cycle immediately before the processing / memory output timing based on timing signals that are different within the same line cycle, and within the same line cycle. Then, a write cycle is determined after the read cycle, and control is performed so that the pre-processing / memory input timing is executed within the same line cycle immediately after the processing / memory output timing.
The memory control device according to claim 3.   An image forming apparatus comprising the memory control device according to claim 3.

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