JP2012074764A - A/d conversion circuit and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion circuit that is capable of reducing a fluctuation of GND voltage caused by operation of an A/D conversion part at each column so that the output fluctuation at each A/D conversion part is prevented even if an A/D conversion part is disposed at each column.SOLUTION: The A/D conversion circuit includes a plurality of A/D conversion parts 40 connected between a power supply and the GND. Each of a plurality of the A/D conversion parts 40 includes a constant current source 16 which provides a reference current Iref, a current distribution circuit 17 that receives an analog signal Vin and the reference current Iref to output a first current Iin according to the analog signal Vin and to output a second current Ig according to the difference between the reference current Iref and the first current Ig, and a plurality of delay elements each of which receives a pulse signal φPL to delay the pulse signal φPL according to either the first current Iin or the second current Ig. A plurality of the delay elements are mutually connected.

Description

  The present invention relates to an A / D conversion circuit and an imaging device.

  In recent years, imaging devices represented by digital still cameras, camcorders, and endoscopes include CCD (Charge Coupled Device) image sensors (hereinafter referred to as CCDs) and CMOS (Complementary Metal Oxide Semiconductor) image sensors (hereinafter referred to as CMOSs). A solid-state imaging device represented by the above is mounted. These imaging devices are widely used in Japan and overseas, and there is an increasing demand for further downsizing and lower power consumption.

  In addition, there is a solid-state imaging device equipped with a plurality of time-to-digital converter (hereinafter referred to as TDC) type A / D converters. The TDC type A / D converter (hereinafter referred to as an A / D converter) outputs a pulse having a frequency corresponding to a voltage (hereinafter referred to as a pixel signal) output from a pixel, and the counter outputs the pulse. The pixel signal can be A / D converted by counting. By disposing this A / D conversion unit in a region where pixels are arranged in a two-dimensional matrix (hereinafter referred to as a pixel block), the A / D conversion unit converts the pixel signal to high S / N. A solid-state imaging device to be converted is shown (for example, see Patent Document 1).

JP 2006-287879 A

  However, when an A / D conversion unit is disposed for each of a plurality of pixels (for example, an A / D conversion unit is disposed for each pixel column), several hundreds to thousands of A / D conversion units with a width of several μm are provided. Will be placed. In this case, if GND is wired separately for each A / D conversion unit, the wiring space increases. Therefore, like the solid-state imaging device 200 shown in FIG. 5, all A / D conversion units are connected to a common GND. Need to be wired.

  FIG. 5 is a block diagram showing a schematic configuration of a conventionally known solid-state imaging device. In the illustrated example, the solid-state imaging device 200 includes a pixel unit 201 in which a plurality of pixels 202 are arranged in a matrix, an analog signal processing unit 203, an A / D conversion circuit 204, a vertical drive unit 205, and a horizontal drive. The A / D conversion circuit 204 includes A / D conversion units 2401 to 2404 for each column of the pixels 202 included in the pixel unit 201. Each of the A / D conversion units 2401 to 2404 includes a delay circuit unit 241 and a counter / latch unit 242. The A / D converters 2401 to 2404 are connected to a common GND.

  FIG. 6 is a block diagram illustrating a schematic configuration of conventionally known A / D conversion units 2401 to 2404. In FIG. 6, the A / D converters 2401 to 2404 include a delay circuit 511, a counter 512, a latch circuit 513, a latch & encoder circuit 514, and a signal processing circuit 515. The counter 512, the latch circuit 513, the latch & encoder circuit 514, and the signal processing circuit 515 are collectively referred to as a pulse passage stage number detection circuit.

  The delay circuit 511 includes a plurality of delay elements (one delay element AND1 and a plurality of delay elements DU1) connected in a ring shape. A pixel signal output from the analog signal processing unit 203 is supplied to each delay element in the delay circuit 511 as an input signal Vin. Each delay element in the delay circuit 511 delays the input pulse φPL with a delay time corresponding to a voltage difference between the signal level and GND, using the supplied input signal Vin as a power supply voltage. The delay circuit 511 generates a pulse signal φCK having a frequency corresponding to the delay time of each delay element.

  The counter 512 counts the number of rounds of the pulse signal φCK generated by the delay circuit 511, that is, the input pulse φPL, and outputs the count result as a digital signal φD1. The latch circuit 513 holds the digital signal φD1 output from the counter 512, and outputs the held digital signal as a digital signal φD2. The latch & encoder circuit 514 takes in the output of each delay element in the delay circuit 511, detects position information of the pulse signal φCK that is the number of passing stages of the delay element through which the input pulse φPL has passed, and the detection result is used as the digital signal φD3. Output as.

  The signal processing circuit 515 processes the digital signal φD2 that is the output of the latch circuit 513 and the digital signal φD3 that is the output of the latch & encoder circuit 514, and the signal level of the input signal Vin, that is, the analog signal processing unit 203 A digital signal φD4 corresponding to the output pixel signal is generated. The digital signal φD4 generated by the signal processing circuit 515 is an output digital signal (digital value) that is analog-digital converted by the A / D converters 2401 to 2404.

  As described above, the operating currents of the A / D converters 2401 to 2404 vary depending on the level of the input signal. Therefore, depending on the level of the input signal input from the pixel, the current It1 that flows through the GND of the delay circuit 511 included in the A / D conversion unit 2401, and the current It2 that flows through the GND of the delay circuit 511 included in the A / D conversion unit 2402 The current It3 flowing through the GND of the delay circuit 511 included in the A / D conversion unit 2403 and the current It4 flowing through the GND of the delay circuit 511 included in the A / D conversion unit 2404 are changed. Therefore, the current flowing through the GND wired in common also changes depending on the pixel signal level for each row. With this current change, the voltage drop voltage at the resistance component of the GND wiring changes, and the GND voltage level of each delay circuit section changes.

  Since the A / D converters 2401 to 2404 convert the input signal Vin, which is an analog signal, into a digital signal according to the voltage difference between the input signal Vin and GND, the same input signal Vin is changed by the voltage fluctuation of the GND. Even in the case of A / D conversion, the output digital value after A / D conversion changes depending on the output value of other pixels in the same row. Therefore, as shown in FIG. 7, there is a problem that the value of the output digital signal for each row varies depending on the area of the bright / dark part in the pixel unit 1 (streaking phenomenon).

  FIG. 7 is a schematic diagram showing an example of the streaking phenomenon. The diagram illustrated in FIG. 7A is a diagram illustrating the amount of light incident on the pixel 202 included in the pixel unit 201. This figure shows the amount of light incident on the pixels 202-1 to 202-16 arranged in 4 rows and 4 columns, and shows that the amount of incident light increases as it changes from black to white. Yes. That is, black indicates that the amount of incident light is small, and white indicates that the amount of incident light is large.

  In the illustrated example, the amount of light incident on the pixels 202-1 to 202-3 arranged in the first to third columns from the left in the first row from the top is large, and the first in the first row from the top. The amount of light incident on the pixel 202-4 arranged in the right column is small. The second to fourth lines from the top are as illustrated.

  The diagram shown in FIG. 7 (2) shows the value of the output digital signal obtained by converting the pixel signals of the pixels 202-1 to 202-16 into digital signals by the A / D converters 2401 to 2404 when the streaking phenomenon occurs. FIG. This figure shows values of output digital signals obtained by converting the pixel signals of the pixels 202-1 to 202-16 arranged in 4 rows and 4 columns into digital signals by the A / D converters 2401 to 2404. In addition, the value of the output digital signal increases as the color changes from black to white. In the illustrated example, the amount of light incident on the pixels 202-4, 5, 8 to 10, and 12 to 16 is the same, but since the streaking phenomenon has occurred, the A / D conversion units 2401 to 2404 convert them into digital signals. The value of the output digital signal is different.

  As described above, in the conventionally known solid-state imaging device 200, even when the amount of incident light is the same, the A / R is determined depending on the output values of the other pixels 202 arranged in the same row of the pixel unit 201. There is a problem that the value of the output digital signal after A / D conversion by the D conversion units 2401 to 2404 is different.

  Conventionally, there has been no example of a configuration suitable for a solid-state imaging device that prevents the influence of GND fluctuations when a plurality of A / D conversion units are mounted.

  The present invention has been made in view of the above points, and even when an A / D conversion unit is mounted for each column, the variation in GND due to the operation of the A / D conversion unit in each column is reduced. An object of the present invention is to provide an A / D conversion circuit and an imaging apparatus that can prevent fluctuations in the output value of the / D conversion unit.

  The present invention is connected between a wiring having a first potential, a wiring having a second potential, a wiring having the first potential, and a wiring having the second potential. A plurality of A / D converters, and each of the plurality of A / D converters receives a constant current source that outputs a reference current, an analog signal, and the reference current, and the analog signal A current distribution circuit that outputs a first current according to the reference current, and outputs a second current according to a difference between the reference current and the first current, and a pulse signal is input, and the first current or the A plurality of delay elements that delay transmission of the pulse signal in accordance with a second current, and the plurality of delay elements are connected to each other.

  In the A / D conversion circuit of the present invention, the current distribution circuit includes a variable resistor that receives the analog signal and outputs the first current corresponding to the analog signal.

  In the A / D conversion circuit of the present invention, the current distribution circuit includes a variable resistor that receives the analog signal and outputs the first current and the second current according to the analog signal. It is characterized by that.

  In addition, the present invention includes an A / D conversion circuit and a pixel unit having a plurality of pixels arranged in a matrix, and a predetermined plurality of pixels among the plurality of pixels is the A / D conversion. An imaging device is characterized in that an analog signal is output to one of A / D conversion units included in a circuit.

  In the imaging device of the present invention, the predetermined plurality of pixels are arranged in the same column of the pixel portion.

  According to the present invention, the current distribution circuit outputs a first current corresponding to the analog signal, and outputs a second current according to a difference between the reference current output from the constant current source and the first current. The plurality of delay elements delay the transmission of the input pulse signal according to the first current or the second current.

  Therefore, regardless of the level of the input analog signal, the power of the delay circuit section of each A / D conversion circuit and the current flowing through the GND can be made constant, so even when the A / D conversion section is mounted for each column, It is possible to reduce the variation in GND due to the operation of the A / D conversion unit in each column and prevent the variation in the output value of each A / D conversion unit.

It is a block diagram which shows schematic structure of the solid-state imaging device in the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the A / D conversion part in the 1st Embodiment of this invention. It is a block diagram which shows the example of schematic structure of the A / D conversion part in the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the A / D conversion part in the 2nd Embodiment of this invention. It is a block diagram which shows schematic structure of the solid-state imaging device known conventionally. It is the block diagram which showed schematic structure of the A / D conversion part known conventionally. It is the schematic which showed the example of the streaking phenomenon.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device according to the present embodiment. In the illustrated example, the solid-state imaging device 100 includes a pixel unit 1 in which a plurality of pixels 2 are arranged in a matrix, an analog signal processing unit 3, an A / D conversion circuit 4, a vertical drive unit 5, and a horizontal drive. The A / D conversion circuit 4 includes an A / D conversion unit 40 for each column of pixels included in the pixel unit 1. Each A / D conversion unit 40 includes a delay circuit unit 41 and a counter / latch unit 42. Each A / D converter 40 is connected to a common power source (wiring having a first potential) and a common GND (wiring having a second potential).

  The pixel 2 outputs an optical signal corresponding to the amount of incident light. The analog signal processing unit 3 calculates a difference between a reset signal output from each pixel 2 and an optical signal corresponding to the amount of incident light, thereby generating a pixel signal in which noise at the time of reset is suppressed. The analog signal processing unit 3 outputs the generated pixel signal as the input signal Vin. The input signal Vin is an analog signal.

  The A / D conversion circuit 4 includes a plurality of A / D conversion units 40, converts the input signal Vin into a digital signal, and outputs the digital signal as an output digital signal φD. The vertical drive unit 5 selects, for each row, the pixels 2 that output signals from the pixels 2 arranged in a matrix. The horizontal drive unit 7 controls the A / D conversion circuit 4 to sequentially output the output digital signal φD.

  Next, the configuration of the A / D conversion unit 40 will be described. The A / D conversion unit 40 is a time-to-digital converter A / D (analog-digital) converter (TAD), which converts an input analog signal into a digital signal and outputs the digital signal.

  FIG. 2 is a block diagram showing a schematic configuration of the A / D conversion unit 40 in the present embodiment. In the illustrated example, the A / D conversion unit 40 includes a delay circuit unit 41 and a counter / latch unit 42 (pulse passing stage number detection circuit). The A / D converter 40 is connected to the power supply and GND. The delay circuit unit 41 includes a constant current source 16, a current distribution circuit 17, and a delay circuit 401. The counter / latch unit 42 includes a counter 12, a latch circuit 13, a latch & encoder circuit 14, and a signal processing circuit 15.

  The constant current source 16 outputs a reference current Iref that is a constant current. The current distribution circuit 17 is configured by a variable resistor 18 to which the reference current Iref output from the constant current source 16 is input and whose resistance value changes according to the input signal Vin. Further, the pixel signal output from the analog signal processing unit 3 is supplied to the variable resistor 18 as the input signal Vin. With this configuration, the resistance value of the variable resistor 18 changes according to the input signal Vin, and the current distribution circuit 17 outputs the first current Ig according to the magnitude of the resistance value of the variable resistor 18. The current distribution circuit 17 outputs a second current Iin corresponding to the difference between the reference current Iref and the first current Ig. A method for distributing the reference current Iref by the current distribution circuit 17 will be described later.

  The delay circuit 401 includes a plurality of delay elements (one delay element AND1 and a plurality of delay elements DU1) connected in a ring shape. The second current Iin output from the current distribution circuit 17 is supplied to each delay element in the delay circuit 401 as the input current Iin. Each delay element in the delay circuit 401 delays the input pulse φPL by a delay time corresponding to the magnitude of the supplied input current Iin. Then, the delay circuit 401 generates a pulse signal φCK having a frequency corresponding to the delay time of each delay element.

  The counter 12 counts the number of rounds of the pulse signal φCK generated by the delay circuit 401, that is, the input pulse φPL, and outputs the count result as a digital signal φD1. The latch circuit 13 holds the digital signal φD1 output from the counter 12, and outputs the held digital signal as a digital signal φD2. The latch & encoder circuit 14 takes in the output of each delay element in the delay circuit 401, detects position information of the pulse signal φCK that is the number of passing stages of the delay element through which the input pulse φPL has passed, and detects the detection result as a digital signal φD3. Output as.

  The signal processing circuit 15 processes the digital signal φD2 that is the output of the latch circuit 13 and the digital signal φD3 that is the output of the latch & encoder circuit 14, and the signal level of the input signal Vin, that is, the analog signal processing unit 3 A digital signal φD4 corresponding to the output pixel signal is generated. The digital signal φD4 generated by the signal processing circuit 15 is an output digital signal (digital value) that is analog-digital converted by the A / D converter 40.

  Next, the operation of the solid-state imaging device 100 according to the first embodiment of the present invention will be described. First, the vertical drive unit 5 sets the pixel selection signal φSL to the “High” level to select the pixel 2 in the first row of the pixel unit 1, and the pixel signal of each pixel 2 in the selected first row is Each is output to the analog signal processing unit 3. Each selected pixel 2 outputs two signals, a reset signal output when the photoelectric conversion element in the pixel 2 is reset and an optical signal corresponding to the amount of incident light. Then, the analog signal processing unit 3 generates a pixel signal in which noise at the time of reset is suppressed by calculating a difference between the signal at the time of reset output from each pixel 2 and an optical signal corresponding to the amount of incident light, The generated pixel signal is output as an input signal Vin to each A / D converter 40 provided for each column of pixels 2.

  Since the resistance value of the variable resistor 18 included in the current distribution circuit 17 of each A / D converter 40 changes according to the input signal Vin, the variable resistor 18 outputs the first current Ig according to the resistance value. As a result, the current distribution circuit 17 outputs a second current Iin corresponding to the difference between the reference current Iref and the first current Ig. The second current Iin is supplied to the delay circuit 401 as the input current Iin.

  Subsequently, the input pulse φPL output to the A / D converter 40 is set to the “High” level. As a result, each delay element in the delay circuit 401 in each A / D converter 40 delays the input pulse φPL by a delay time corresponding to the supplied input current Iin, and according to the delay time of each delay element. A pulse signal φCK having a predetermined frequency is generated. Then, the counter 12 counts the pulses φCK output from the delay circuit 401.

  Then, after a predetermined period has elapsed, the latch & encoder circuit 14 detects position information of the pulse signal φCK in the delay circuit 401. At the same time, the latch circuit 13 latches the count result of the counter 12. After that, by setting the input pulse φPL to the “Low” level, the delay of the input pulse φPL in the delay circuit 401 is stopped, and the generation of the pulse signal φCK is ended.

  Thereafter, the signal processing circuit 15 processes the digital signal φD2 output from the latch circuit 13 and the digital signal φD3 output from the latch & encoder circuit 14, and converts the digital signal φD4 corresponding to the input current Iin to an A / D converter. It is output as 40 output digital signals. Note that the magnitude of the input current Iin changes according to the signal level of the input signal Vin, that is, the pixel signal of each pixel 2. Therefore, the digital signal φD4 that changes depending on the magnitude of the input current Iin is a signal indicating the magnitude of the pixel signal of each pixel 2.

  Subsequently, the horizontal driving unit 7 sequentially selects the output digital signal output from each A / D conversion unit 40 by sequentially setting the read control signal φH to the “High” level, and externally outputs it as an imaging signal of the imaging device. Output. Subsequently, the vertical drive unit 5 sets the pixel selection signal φSL to the “Low” level, thereby completing the reading of the pixels 2 in the first row.

  The solid-state imaging device 100 repeatedly executes the readout operation of the pixels 2 described above, and sequentially reads out the pixels 2 in the second and subsequent rows, thereby reading out all the pixels 2 of the pixel unit 1 included in the solid-state imaging device 110. To implement.

  Next, the current flowing through the power supply, GND, and current distribution circuit of the A / D converter 40 will be described. The current flowing from the power source of the A / D converter 40 to the current distribution circuit 17 is constant current regardless of the input voltage Vin to the A / D converter 40 because each delay circuit 41 includes the constant current source 16. It becomes the reference current Iref of the source 16.

  This reference current Iref is input to the current distribution circuit 17. The current distribution circuit 17 is connected to the delay circuit 401 and GND, and distributes the reference current Iref to the delay circuit 401 and GND according to the magnitude of the input voltage Vin. In the present embodiment, the current supplied to GND is a first current Ig, and the current supplied to the delay circuit 401 is a second current Iin.

  Here, the current distribution circuit 17 includes a variable resistor 18 whose resistance value varies according to the magnitude of the input voltage Vin on the side connected to the GND. The resistance value of the variable resistor 18 increases when the input voltage Vin is high and decreases when the input voltage Vin is low. Therefore, the second current Iin supplied to the delay circuit 401 increases when the input voltage Vin is high and decreases when the input voltage Vin is low.

  Further, the first current Ig flows to GND through the variable resistor 18. Further, the second current Iin supplied to the delay circuit 401 flows to GND through the delay element in the delay circuit 401. Therefore, the current flowing through the GND of the A / D converter 40 is the same as the current obtained by adding the first current Ig and the second current Iin, that is, the reference current Iref, and does not change with the voltage Vin.

  As described above, in the plurality of A / D conversion units 40 included in the A / D conversion circuit 4 of the present embodiment, the current flowing through the GND is constant regardless of the magnitude of the input voltage Vin. Therefore, even when the A / D conversion circuit includes the A / D conversion unit 40 for each column of the pixels 2 and each A / D conversion unit 40 is connected to the same GND, the wiring resistance of the GND Voltage fluctuation does not occur. Therefore, it is possible to reduce the variation in GND due to the operation of the A / D conversion unit 40 in each column, and to prevent the variation in the output value of each A / D conversion unit 40. As a result, the streaking phenomenon that occurs during the A / D conversion process can be suppressed, and deterioration in image quality can be avoided.

  The schematic configuration of the A / D conversion unit 40 is not limited to the example illustrated in FIG. 2 and may be the configuration illustrated in FIG. FIG. 3 is a block diagram illustrating a schematic configuration example of the A / D conversion unit 50 in the present embodiment. The difference between the A / D converter 40 shown in FIG. 2 and the A / D converter 50 shown in FIG. 3 is that the A / D converter 50 shown in FIG. This current is supplied from the GND side of the delay circuit 401.

  The current flowing through the GND of the A / D conversion unit 50 configured as described above becomes the reference current Iref output from the constant current source 16, and does not change depending on the voltage Vin. This reference current Iref is input to the current distribution circuit 17. The current distribution circuit 17 is connected to the delay circuit 401 and the power supply, and distributes the reference current Iref to the delay circuit 401 and the power supply in accordance with the magnitude of the input voltage Vin.

  Here, the current distribution circuit 17 includes a variable resistor 18 whose resistance value varies according to the magnitude of the input voltage Vin on the side connected to the power source. The resistance value of the variable resistor 18 increases when the input voltage Vin is high and decreases when the input voltage Vin is low. Therefore, the second current Iin supplied to the delay circuit 401 increases when the input voltage Vin is high and decreases when the input voltage Vin is low.

  Further, the first current Ig flows from the constant current source 16 to the power source through the variable resistor 18. The second current Iin supplied to the delay circuit 401 flows to the power supply through the delay element in the delay circuit 401.

  Therefore, the current flowing through the power supply is the same as the current obtained by adding the first current Ig and the second current Iin, that is, the reference current Iref, and does not change with the voltage Vin. Therefore, the A / D conversion unit 50 shown in FIG. 3 can obtain the same effect as the A / D conversion unit 40 shown in FIG.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a schematic configuration of the A / D converter 60 in the present embodiment. In the illustrated example, the A / D conversion unit 60 includes a delay circuit unit 61 and a counter / latch unit 42. The delay circuit unit 61 includes a constant current source 16, a current distribution circuit 67, and a delay circuit 401. The counter / latch unit 42 includes a counter 12, a latch circuit 13, a latch & encoder circuit 14, and a signal processing circuit 15. The constant current source 16, the delay circuit 401, the counter 12, the latch circuit 13, the latch & encoder circuit 14, and the signal processing circuit 15 have the same configuration as each part of the first embodiment.

  The current distribution circuit 67 receives the reference current Iref output from the constant current source 16. The current distribution circuit 67 includes a MOS transistor 19 having an input signal Vin connected to the gate, a MOS transistor 20 having a constant voltage Vref connected to the gate, an output terminal of the constant current source 16, and a source of the MOS transistor 19. The resistor 21 is connected between them, and the resistor 22 is connected between the output terminal of the constant current source 16 and the source of the MOS transistor 20.

  The pixel signal output from the analog signal processing unit 3 is supplied to the gate of the MOS transistor 19 as the input signal Vin, and the constant voltage Vref is supplied to the gate of the MOS transistor 20. Thereby, the output current Iref of the constant current source 16 is distributed to the current Iin flowing through the MOS transistor 19 and the current Ig flowing through the MOS transistor 20 in accordance with the difference voltage between the input signal Vin and the constant voltage Vref. The current Iin flowing through the MOS transistor 19 is supplied to the delay circuit 401, and the current Ig flowing through the MOS transistor 20 is supplied to GND. Specifically, the second current Iin supplied to the delay circuit 401 increases when the input voltage Vin is high and decreases when the input voltage Vin is low. With this configuration, the current distribution circuit 67 outputs the first current Ig and the second current Iin according to the input signal Vin.

  Note that the configuration of the current distribution circuit 67 is not limited to that shown in FIG. 4, and the output current Iref of the constant current source 16 is expressed by the first current Ig and the second current Iin according to the magnitude of the input signal Vin. Any configuration may be used as long as it can be distributed and output. For example, instead of the MOS transistor 20 having the constant voltage Vref connected to the gate, a fixed value resistor may be provided.

  Next, the operation of the solid-state imaging device 110 of this embodiment will be described. The configuration and operation of the solid-state imaging device 110 according to the present embodiment are the same as those of the first embodiment except that the configuration of the current distribution circuit 67 of each A / D conversion unit 60 provided in the A / D conversion circuit 6 is different. It is.

  Next, the current flowing through the power supply, GND, and current distribution circuit of the A / D conversion unit 60 will be described. The current flowing from the power supply of the A / D conversion unit 60 to the current distribution circuit 67 is constant current regardless of the input voltage Vin to the A / D conversion unit 60 because each delay circuit unit 61 includes the constant current source 16. It becomes the reference current Iref of the source 16.

  This reference current Iref is input to the current distribution circuit 67. The current distribution circuit 67 is connected to the delay circuit 401 and GND, and distributes the reference current Iref to the delay circuit 401 and GND according to the magnitude of the input voltage Vin. In the present embodiment, the current supplied to GND is a first current Ig, and the current supplied to the delay circuit 401 is a second current Iin.

  Here, the second current Iin flowing in the MOS transistor 19 is supplied to the delay circuit 401 through the resistor 21 and the MOS transistor 19, and flows to GND through the delay element in the delay circuit 401. Further, the first current Ig flowing through the resistor 22 and the MOS transistor 20 flows to GND. Therefore, the current flowing through the GND is the same as the current obtained by adding the first current Ig and the second current Iin, that is, the reference current Iref, and does not change with the voltage Vin.

  As described above, in the plurality of A / D conversion units 60 included in the A / D conversion circuit 6 of the present embodiment, the current flowing through the GND is constant regardless of the magnitude of the input voltage Vin. Therefore, even when the A / D conversion circuit 6 includes the A / D conversion unit 60 for each column of the pixels 2 and each A / D conversion unit 60 is connected to the same GND, the wiring resistance of the GND No voltage fluctuation occurs. Therefore, the solid-state imaging device 110 according to the present embodiment reduces the variation in GND due to the operation of the A / D conversion unit 60 in each column, similarly to the solid-state imaging device 100 according to the first embodiment, and each A / D conversion unit. The fluctuation of 60 output values can be prevented.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

  1, 201... Pixel unit, 2, 202, 202-1 to 16... Pixel, 3,203... Analog signal processing unit, 4, 204... A / D conversion circuit, 5, 205. ..Vertical drive unit, 7,207 ... Horizontal drive unit, 12,512 ... Counter, 13,513 ... Latch circuit, 14,514 ... Latch & encoder circuit, 15,515 ... Signal processing circuit, 16 ... constant current source, 17, 67 ... current distribution circuit, 18 ... variable resistor, 19, 20 ... MOS transistor, 21, 22 ... resistor, 40, 50, 60, 2401 to 2404 ... A / D converter, 41, 51, 61, 241 ... delay circuit, 42, 242 ... counter / latch, 100, 110, 200 ... solid-state imaging device , 401, 511... Delay circuit

Claims (5)

A wiring having a first potential;
A wiring having a second potential;
A plurality of A / D converters connected between the wiring having the first potential and the wiring having the second potential;
Have
Each of the plurality of A / D conversion units includes:
A constant current source for outputting a reference current;
A current distribution circuit that receives an analog signal and the reference current, outputs a first current according to the analog signal, and outputs a second current according to a difference between the reference current and the first current; ,
A plurality of delay elements that receive a pulse signal and delay transmission of the pulse signal according to the first current or the second current;
Have
The A / D conversion circuit, wherein the plurality of delay elements are connected to each other. The current distribution circuit includes:
The A / D converter circuit according to claim 1, further comprising: a variable resistor that receives the analog signal and outputs the first current corresponding to the analog signal. The current distribution circuit includes:
The A / D conversion circuit according to claim 1, further comprising: a variable resistor that receives the analog signal and outputs the first current and the second current according to the analog signal. An A / D conversion circuit according to any one of claims 1 to 3,
A pixel portion having a plurality of pixels arranged in a matrix;
Have
A predetermined plurality of pixels among the plurality of pixels output an analog signal to one of the A / D conversion units included in the A / D conversion circuit. The imaging apparatus according to claim 4, wherein the predetermined plurality of pixels are arranged in the same column of the pixel unit.

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