JP2012074723A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage which ensures a transfer and process margin without deforming a gate shape intricately when forming gate wiring of SRAM.SOLUTION: A semiconductor storage comprises: a memory cell array in which memory cells each including a first group and a second group of a driver transistor 11, a load transistor 12 and an access transistor 13 are arranged on a semiconductor substrate in a two-dimensional matrix; a plurality of word lines; a plurality of bit lines; rectangular first gate wiring 3a having linear sides and connecting the driver transistor 11 and the load transistor 12 in the first group; rectangular second gate wiring 3c having linear sides and connected with the access transistor 13; a first connector 5a connecting the first gate wiring 3a with the driver transistor 11 and the load transistor 12 in the second group; and a second connector 5c connecting the second gate wiring 3c with the word lines.

Description

  The present invention relates to a semiconductor memory device, particularly an SRAM.

  An SRAM does not require a refresh operation when the power is turned on and is easy to use. However, since the number of elements constituting one memory cell is large and the occupied area is large, the cell area is required to be reduced. . For example, in Japanese Patent Laid-Open No. 9-270468 (US Pat. No. 5,744,844) and Japanese Patent Laid-Open No. 10-178110 (US Pat. No. 5,930,163), one cell is configured to be longer in the word line direction than in the bit line direction. An example cell layout is shown. Among these, FIG. 16 and FIG. 117 show the planar configuration of the SRAM described in JP-A-10-178110. FIG. 16 is a plan view of one memory cell of this SRAM. FIG. 17 is an equivalent circuit diagram corresponding to one memory cell of FIG. In this manner, the length in the bit line direction is shortened to increase the speed, and the layout of the active layer and the gate wiring is basically a simple shape close to a straight line, and the cell area is reduced.

  In terms of miniaturization, a phenomenon (optical proximity effect) that the resist pattern on the wafer is distorted due to light interference in the exposure apparatus becomes significant. Further, even after the etching process, pattern distortion after etching due to the microloading effect occurs. The microloading effect is a phenomenon in which the etching rate decreases with respect to the depth direction when matching patterns with large density differences. In recent years, in order to minimize these pattern distortions, an optical proximity effect correction (OPC) technique in which a mask pattern in a photolithography process is automatically corrected in advance by a CAD technique has been developed and used.

  Normally, when a contact hole is formed in a gate wiring to make a contact, it is necessary to provide a cover margin such as a transfer margin and a processing margin in consideration of blurring during photolithography. For this reason, it is necessary to change the portion of the gate wiring where the contact hole is to be formed by increasing the width by the cover margin. Further, when the width of the gate wiring itself is reduced, it is necessary to increase the width of a part of the gate wiring.

  Further, if an attempt is made to reduce the size by inserting an OPC pattern by the optical proximity effect correction (OPC) technique, if the gate wirings are arranged in a complicated manner, the optical proximity effect correction is performed in each of the vertical and horizontal directions. It was necessary to provide a margin. For this reason, since sufficient miniaturization cannot be performed, the memory cell area cannot be sufficiently reduced, which has been an obstacle to miniaturization.

  Therefore, an object of the present invention is to secure a transfer and processing margin without complicatedly changing the gate shape when forming a gate wiring of a semiconductor memory device, particularly, an SRAM.

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells each including a first set and a second set of driver transistors, a load transistor, and an access transistor are two-dimensionally arranged on a semiconductor substrate;
A plurality of word lines connected to the two-dimensionally arranged memory cells and arranged parallel to each other along a first direction;
A plurality of bit lines connected to each of the memory cells and arranged in parallel to each other along a second direction orthogonal to the first direction;
A rectangular first gate line connecting the first set of the driver transistor and the load transistor and having a straight side;
A rectangular second gate line connected to the access transistor and having a straight side;
A first connector connecting the first gate line, a second set of the driver transistor and the load transistor;
A second connector for connecting the second gate line and the word line is provided.

  The semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second gate wirings are arranged so that a longitudinal direction extends in a gate width direction of the access transistor. It is characterized by.

  Furthermore, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second gate electrodes are arranged in parallel with each other in the longitudinal direction along the first direction. Features.

  Still further, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein a distance between the first gate wiring and the second gate wiring adjacent to each other in the first direction is substantially the same. It is characterized by being.

  The semiconductor memory device according to the present invention is the semiconductor memory device, wherein a distance between the first gate line and the second gate line adjacent in the second direction is substantially the same. It is characterized by that.

  Further, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second gate electrodes have short sides having substantially the same length.

  Furthermore, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first gate wiring and the second gate wiring have substantially the same projected shape on a plane parallel to the substrate. It is characterized by being.

  The semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second gate lines are configured to be point-symmetric with respect to a predetermined symmetry point.

  Furthermore, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second gate wirings have a long side / short side value of 5 or more.

  Still further, the semiconductor memory device according to the present invention is the semiconductor memory device, wherein a length of a short side of the first and second gate wirings is 0.15 μm or less.

  The semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first and second connectors are made of tungsten damascene.

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells each including a first set and a second set of driver transistors, a load transistor, and an access transistor are two-dimensionally arranged on a semiconductor substrate;
A plurality of word lines connected to the two-dimensionally arranged memory cells and arranged parallel to each other along a first direction;
A plurality of bit lines connected to each of the memory cells and arranged in parallel to each other along a second direction orthogonal to the first direction;
A first gate line connecting the first set of the driver transistor and the load transistor;
A second gate line connected to the access transistor;
With
The first and second gate electrodes may be arranged in parallel with each other in the longitudinal direction.

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells each including a first set and a second set of driver transistors, a load transistor, and an access transistor are two-dimensionally arranged on a semiconductor substrate;
A plurality of word lines connected to the two-dimensionally arranged memory cells and arranged parallel to each other along a first direction;
A plurality of bit lines connected to each of the memory cells and arranged in parallel to each other along a second direction orthogonal to the first direction;
A first gate line connecting the first set of the driver transistor and the load transistor;
A second gate line connected to the access transistor;
With
An interval between the first gate line and the second gate line adjacent to each other in at least one of the first direction and the second direction is substantially the same.

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells each including a first set and a second set of driver transistors, a load transistor, and an access transistor are two-dimensionally arranged on a semiconductor substrate;
A plurality of word lines connected to the two-dimensionally arranged memory cells and arranged parallel to each other along a first direction;
A plurality of bit lines connected to each of the memory cells and arranged in parallel to each other along a second direction orthogonal to the first direction;
A first gate line connecting the first set of the driver transistor and the load transistor;
A second gate line connected to the access transistor;
With
The first gate line and the second gate line may have substantially the same projected shape on a plane parallel to the substrate.

The semiconductor memory device according to the present invention is the semiconductor memory device, wherein the first gate line, a first connector for connecting the second set of the driver transistor and the load transistor,
And a second connector connecting the second gate line and the word line.

A method for manufacturing a semiconductor memory device according to the present invention includes a semiconductor substrate preparation step of preparing a semiconductor substrate,
An element isolation oxide film forming step of forming an element isolation oxide film at a predetermined position of the semiconductor substrate;
A well region forming step of forming each of the well regions by ion-implanting into a predetermined portion of the semiconductor substrate and sequentially arranging a P well region, an N well region, and a P well region in a first direction;
A polysilicon wiring layer forming step of depositing a polysilicon wiring layer for gate wiring after depositing a gate oxide film on the semiconductor substrate;
A transistor forming step of ion-implanting into the semiconductor substrate through the polysilicon wiring layer to create a driver transistor, a load transistor and an access transistor;
A gate wiring forming step of patterning the polysilicon wiring layer to form a first gate wiring connecting the driver transistor and the load transistor and a second gate wiring connected to the access transistor;
A connector groove forming step of depositing a planarization insulating film and etching the planarization insulation film with a connector mask;
A tungsten damascene process in which tungsten is deposited in the connector groove and planarized to leave the tungsten in the groove to form first and second connectors;
A stack via hole forming step of depositing a planarization insulating film, opening a hole for a stack via hole, filling tungsten, removing tungsten other than the stack via hole to form a stack via hole;
A first metal wiring forming step of depositing a first metal layer on the entire surface, removing the first metal layer except for a predetermined portion with a first metal wiring mask, and forming a first metal wiring;
A first via hole forming step of depositing an interlayer insulating film, opening a hole of a first via hole, embedding tungsten, and removing the other tungsten by etching to form a first via hole;
A second metal wiring step of depositing a second metal layer and removing the second metal layer except for a predetermined portion to form a second metal wiring. The first and second gate wirings include the first metal wiring A rectangular shape having a longitudinal direction parallel to the direction and having straight side edges.

  According to the semiconductor memory device of the present invention, the first gate wiring and the second gate wiring have a rectangular shape having a straight side with no notch or protrusion, and are laid out in a straight line. . As a result, the first and second gate wirings can be formed with high accuracy, and the characteristics of the transistors constituting the memory cell can be stabilized. Therefore, stable characteristics can be obtained as a semiconductor memory device. In this semiconductor memory device, a contact with each gate wiring is made using a local interconnector (LIC). That is, the contact with each gate wiring is not made through a via hole directly formed on the gate wiring but by a local interconnector (LIC) formed by tungsten damascene. By using LIC in this way, it is not necessary to provide a contact cover margin when forming each gate wiring, and a regular rectangular gate wiring can be laid out. In addition, since the first gate wiring and the second gate wiring are laid out in parallel with each other, pattern distortion due to interference can be suppressed in the step of forming the gate wiring by photolithography. Therefore, the optical proximity effect in photolithography can be suppressed.

  According to the semiconductor memory device of the present invention, since the longitudinal directions of the first and second gate wirings are arranged so as to extend over the gate width direction of the access transistor, the longitudinal direction of each gate wiring is determined. It can coincide with the long side of the memory cell.

  Furthermore, according to the semiconductor memory device of the present invention, since the first and second gate electrodes are arranged in parallel with each other along the first direction, the longitudinal direction of each gate wiring Can coincide with the long side of the memory cell.

  Furthermore, according to the semiconductor memory device of the present invention, the distance (pitch) in the longitudinal direction (first direction) between the first gate wiring and the second gate wiring is made substantially equal. Thus, the occurrence of the optical proximity effect can be suppressed during photolithography, so that it is not necessary to change the shape of the gate wiring for the optical proximity effect correction (OPC). Therefore, it is possible to prevent a decrease in yield resulting from a transfer margin shortage. Further, the transfer resolution can be improved. Furthermore, since the characteristics of the transistors obtained thereby can be made uniform and stable, stable characteristics can be obtained as a semiconductor memory device.

  In addition, according to the semiconductor memory device of the present invention, since the distance between the first gate line and the second gate line adjacent in the second direction is substantially the same, the optical proximity effect is further increased in photolithography. Can be suppressed. Therefore, it is possible to prevent a decrease in yield resulting from a transfer margin shortage. Further, the transfer resolution can be improved. Furthermore, since the characteristics of the transistors obtained thereby can be made uniform and stable, stable characteristics can be obtained as a semiconductor memory device.

  Furthermore, according to the semiconductor memory device of the present invention, since the first and second gate electrodes have short sides having substantially the same length, the optical proximity effect can be further suppressed in photolithography. Therefore, it is possible to prevent a decrease in yield resulting from a transfer margin shortage. Further, the transfer resolution can be improved.

  Still further, according to the semiconductor memory device of the present invention, the first gate wiring and the second gate wiring have the same projection shape onto the plane parallel to the substrate, so that the gap between the layers is embedded. Can be kept uniform. Therefore, as the interlayer insulating film, not only a BPSG film having good sagging properties but also a material having relatively poor sagging properties such as an NSG film and a PSG film can be used. This provides a degree of freedom in material selection and can reduce costs. Furthermore, the material of the interlayer insulating film can be selected according to conditions such as the difficulty of CMP processing, the dielectric constant to be set, the difficulty of generating voids, and soft errors.

  In addition, according to the semiconductor memory device of the present invention, the first and second gate wirings are configured to be point-symmetric with respect to a predetermined symmetry point, so that the mask is rotated around the predetermined symmetry point for use. can do.

  Furthermore, according to the semiconductor memory device of the present invention, the aspect ratio x of the long side (L) / short side (W) of the first and second gate wirings is 5 or more. Thus, by setting the aspect ratio of the gate wiring to 5 or more, it is possible to greatly reduce the number of defects such as pattern skipping during transfer.

  Furthermore, according to the semiconductor memory device of the present invention, each of the memory cells can be miniaturized because the length of the short side of the first and second gate lines is 0.15 μm or less.

  Further, according to the semiconductor memory device of the present invention, the first and second local interconnectors are made of tungsten damascene, so that no contact margin is required for making contact with the gate wiring. Thus, it is not necessary to change the shape of the gate wiring for the contact margin when forming the gate wiring.

  According to the semiconductor memory device of the present invention, since the longitudinal directions of the first and second gate electrodes are arranged in parallel with each other, the formation of the gate wiring can be simplified. Thereby, a manufacturing process can be simplified.

  According to the semiconductor memory device of the present invention, the distance between the first gate line and the second gate line adjacent in at least one of the first direction and the second direction is substantially the same. Therefore, the optical proximity effect can be suppressed in photolithography. Therefore, it is possible to prevent a decrease in yield resulting from a transfer margin shortage. Further, the transfer resolution can be improved. Furthermore, since the characteristics of the transistors obtained thereby can be made uniform and stable, stable characteristics can be obtained as a semiconductor memory device.

  According to the semiconductor memory device of the present invention, the first gate wiring and the second gate wiring have the same projected shape onto the plane parallel to the substrate, so that the spacing between the embedded layers is uniform. I can keep it. Therefore, as the interlayer insulating film, not only a BPSG film having good sagging properties but also a material having relatively poor sagging properties such as an NSG film and a PSG film can be used. This provides a degree of freedom in material selection and can reduce costs. Furthermore, the material of the interlayer insulating film can be selected according to conditions such as the difficulty of CMP processing, the dielectric constant to be set, the difficulty of generating voids, and soft errors.

  According to the semiconductor memory device of the present invention, the first and second connectors are contacted without directly providing contact holes in the first and second gate lines. Therefore, a contact margin for making contact with each gate wiring is not required. Accordingly, it is not necessary to change the shape of the gate wiring for the contact margin when forming the gate wiring.

  According to the method for manufacturing a semiconductor memory device of the present invention, the first and second gate wirings having a rectangular shape having a straight side having no notch or protrusion can be formed. Further, the first and second gate lines can be regularly laid out along the longitudinal direction of the word line. Thereby, transistor characteristics such as driver transistors and access transistors constituting the semiconductor memory device can be stabilized and made uniform. Therefore, stable characteristics as a semiconductor memory device can be obtained.

1 is a circuit diagram showing an equivalent circuit corresponding to one memory cell of a semiconductor memory device according to a first embodiment of the present invention. 1 is a plan view showing a configuration centering on a gate wiring of a semiconductor memory device according to a first embodiment of the present invention; FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2. FIG. 3 is a cross-sectional view taken along line C-C ′ of FIG. 2. FIG. 3 is a sectional view taken along line D-D ′ in FIG. 2. FIG. 3 is a conceptual plan view from the top showing a portion related to wiring of the memory cell of the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a plan view showing a step of forming a gate wiring in the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a plan view showing a step of forming a stacked via hole for connecting the formed LIC in the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a plan view showing a process of filling tungsten in the first via hole and removing other tungsten by etching in the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention; FIG. 10 is a plan view showing a step of depositing and etching a third metal layer in the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention. It is a top view which shows the process of forming the gate wiring in four memory cells of the semiconductor memory device based on Embodiment 2 of this invention. FIG. 6 is a plan view showing a configuration centering on gate wirings in four memory cells of a semiconductor memory device according to a second embodiment of the present invention; It is a top view which shows the structure centering on the gate wiring in the four memory cells in another case of the semiconductor memory device concerning Embodiment 2 of this invention. 10 is a graph showing the relationship between the aspect ratio of the gate wiring and the number of defects generated in the semiconductor memory device according to the fourth embodiment of the present invention. It is a top view which shows the structure centering on the gate wiring in the conventional semiconductor memory device. FIG. 17 is a circuit diagram showing an equivalent circuit corresponding to one memory cell of the semiconductor memory device of FIG. 16.

  A semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, substantially the same members are denoted by the same reference numerals.

Embodiment 1 FIG.
A semiconductor memory device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described with reference to FIGS. First, a semiconductor memory device will be described with reference to FIGS. As shown in the circuit diagram of FIG. 1, the semiconductor memory device includes a memory cell array in which memory cells 10 including two sets of driver transistors 11, load transistors 12, and access transistors 13 are two-dimensionally arranged. This semiconductor memory device is a type of SRAM having six transistors. The wiring of one of the memory cells 10 will be described with reference to FIG. This memory cell 10 has two types of gate wiring. That is, first gate wirings 3a and 3b for connecting the driver transistor 11 and the load transistor 12 and second gate wirings 3c and 3d for connecting the access transistor 13 and the word line WL are provided. As shown in the plan view of FIG. 2, the first gate wirings 3a and 3b and the second gate wirings 3c and 3d have a rectangular shape having straight sides without notches or protrusions, and have a longitudinal direction. Are laid out parallel to each other across the gate width direction of the access transistor 13. More specifically, each gate wiring 3 is laid out parallel to the longitudinal direction of the word line. As a result, the first and second gate wirings 3a, 3b, 3c, and 3d can be formed with high accuracy, and the characteristics of each transistor can be stabilized. Therefore, stable characteristics can be obtained as a semiconductor memory device. The longitudinal direction of the word line is the first direction. The direction orthogonal to the first direction is the second direction.

  Note that Japanese Patent Application Laid-Open Nos. 2000-124332, 2000-208643, and 2000-31298 describe SRAMs having gate wirings arranged linearly. However, in all of the SRAMs described in these publications, a contact hole is directly formed in the gate wiring to make a contact, and a cover margin for actually contacting the gate wiring is required. Is deformed or provided with extra width. For this reason, a rectangular gate wiring having a straight side with no notch or protrusion as in the present invention cannot be obtained. Here, the “notch portion” means a notch or a recess. Therefore, “linear” means that a substantially straight line is formed.

  Further, in this semiconductor memory device, a contact is made with each gate wiring using a local interconnector (LIC) described in US Pat. No. 5,541,427. That is, the contact with each gate wiring is not made through a via hole directly formed on the gate wiring but by a local interconnector (LIC) formed by tungsten damascene. By using the LIC in this way, it is not necessary to provide a cover margin for contact when forming each gate wiring, and it is possible to lay out a rectangular gate wiring having a straight side without a notch or a protrusion. it can. In addition, since the first gate wirings 3a and 3b and the second gate wirings 3c and 3d are laid out in parallel with each other, pattern distortion due to interference can be suppressed in the step of forming the gate wiring by photolithography. Therefore, the optical proximity effect in photolithography can be suppressed. Thereby, the gate wiring can be miniaturized.

  Further, the configuration of this semiconductor memory device will be described. As shown in the equivalent circuit diagram of FIG. 1, this semiconductor memory device is an SRAM that includes a first set and a second set of driver transistors 11, a load transistor 12, and an access transistor 13 in one memory cell 10. Further, as shown in FIGS. 1 and 2, each memory cell 10 has a configuration in which the longitudinal direction of the word line WL is longer than the longitudinal direction of the bit line BIT. FIG. 2 is a plan view showing the connection between the gate wirings 3a, 3b, 3c and 3d and the local interconnectors (LIC) 5a, 5b, 5c and 5d. The first gate wirings 3a and 3b connecting the driver transistor 11 and the load transistor 12 are connected to each other in the same memory cell by the first local interconnectors (LIC) 5a and 5b of tungsten (W) by the damascene process, respectively. A set of driver transistor 11 and load transistor 12 is in contact. The second gate lines 3c and 3d connected to the access transistor 13 are in contact with the word lines by the second LICs 5c and 5d, respectively. Note that the cross-couple wiring of the inverter in the memory cell is formed using LIC, the bit line is formed of the second metal wiring, the VDD line is formed of the second metal wiring, and the GND line is formed of the second metal wiring.

  Further, the configuration in the direction perpendicular to the substrate surface of the semiconductor substrate 1 of this semiconductor memory device will be described with reference to FIGS. Among these, FIGS. 3 to 6 are cross-sectional views taken along the cutting lines of FIG. First, as shown in the cross-sectional view along the longitudinal direction (first direction) of the word line in FIG. 3, the semiconductor substrate 1 of this semiconductor memory device has a first P well region, an N well region, and a P well region. It is formed in order along the direction. Further, an access transistor 13, a load transistor 12, and a driver transistor 11 are formed separated from each other by an element isolation oxide film (STI). On the semiconductor substrate 1, a first gate wiring 3b made of polysilicon for connecting the driver transistor 11 and the load transistor 12 extends along the first direction. The second gate wiring 3c made of polysilicon extends on the access transistor 13 in a straight line along the first direction. As shown in FIG. 3, the first and second gate wirings 3b and 3c are formed of tungsten embedded in a trench for a local interconnector provided in an interlayer insulating film deposited thereon. Contacts are made by the second local interconnectors 5b and 5c. Furthermore, as shown in FIG. 4, the LIC is connected to the first metal wiring layer by a stack via hole. Further, as shown in FIG. 5, first LICs 5b and 5a made of tungsten are embedded. Further, as shown in FIG. 6, in the connection between the gate wiring 3 and the LIC 5, even when a mask shift occurs, a shift corresponding to the sidewall width can be allowed. Further, the configuration relating to the wiring of this semiconductor memory device is shown in the plan view of FIG. In FIG. 7, only the configuration related to the wiring is shown by removing the interlayer insulating film from the upper surface.

Next, a method for manufacturing this semiconductor memory device will be described with reference to FIGS. This semiconductor memory device is manufactured by the following steps.
(1) The semiconductor substrate 1 is prepared.
(2) An element isolation oxide film (STI: Shallow Trench Isolation) 2 is formed at a predetermined location of the semiconductor substrate 1.
(3) Ion implantation is performed at a predetermined location to form a well region. In this case, as shown in FIG. 8, each well region is formed in order so that a P well region, an N well region, and a P well region are arranged in order on the semiconductor substrate 1. This arrangement direction is defined as a first direction. The first direction is the long side direction of one memory cell 10.
(4) After depositing a gate oxide film, a polysilicon wiring layer 3 to be a gate wiring is deposited.
(5) Next, ions are implanted to form transistors 11, 12, and 13.
(6) Thereafter, patterning is performed (FIG. 8). Thereby, the first gate wirings 3a and 3b and the second gate wirings 3c and 3d are formed. As shown in FIG. 8, the first gate wirings 3a and 3b connect the driver transistor 11 and the load transistor 12, and are arranged in a straight line along the first direction. The second gate wirings 3c and 3d are connected to the access transistor 13 and arranged in a straight line along the first direction. Each of the gate wirings 3 has a rectangular shape having a straight side with no notches and protrusions and is regularly arranged. For this reason, in patterning, the precision of miniaturization can be improved.

(7) The side wall 4 is formed.
(8) Source S and drain D are formed by ion implantation.
(9) A CoSi2 layer is formed.
(10) Deposit an etching stopper film.
(11) Deposit the planarization insulating film 6a.
(12) The planarization insulating film 6a is etched with a mask for a local interconnector (LIC). At this time, etching is stopped by an etching stopper.
(13) The etching stopper film exposed by etching the planarization insulating film 6a is removed to form a groove for LIC.
(14) Tungsten (W) is deposited in the groove for LIC and then flattened, leaving tungsten only in the groove (W damascene method) to form tungsten LIC5. The first LICs 5a and 5b and the second LICs 5c and 5d can be formed. Since the contact with the gate wiring can be made through the LICs 5a, 5b, 5c and 5d, it is not necessary to change the shape of the gate wiring in order to provide a margin for contact. The damascene method for the first LICs 5a and 5b can be a single damascene method in which only wiring is formed.
(15) Deposit the planarization insulating film 6b.
(16) Open a hole for the stacked via hole 7.
(17) Tungsten other than the tungsten LIC 5 portion and the stacked via hole 7 is removed (FIG. 9). As a result, the stack via hole 7 for connection from the second gate wiring 3c, 3d to the word line WL via the second LIC 5c, 5d can be formed.

(18) The first metal layer 8 is deposited on the entire surface.
(19) The first metal layer 8 other than the predetermined portion is removed by the first metal wiring mask. As a result, as shown in FIG. 10, a word line WL made of the first metal wiring 8 can be formed.
(20) Deposit an interlayer insulating film 6c.
(21) Open the first via hole 14.
(22) Tungsten is buried in the first via hole 14, and the other tungsten is removed by etching (FIG. 10). Thereby, an electrical connection from the first metal wiring 8 to the upper layer can be formed.

(23) The second metal layer 9 is deposited, and the second metal layer 9 other than the predetermined portion is removed. Thereby, a bit line, a VDD line, and a GND line made of the second metal wiring 9 can be formed.
(24) An interlayer insulating film 6d is deposited.
(25) Opening the second via hole by etching.
(26) Tungsten is buried in the second via hole, and other tungsten is removed by etching.
(27) The third metal wiring layer 15 is deposited, and the third metal wiring layer 15 other than the predetermined portion is removed (FIG. 11).

  Through the above steps, the semiconductor memory device can be obtained. In this method of manufacturing a semiconductor memory device, it is possible to manufacture a semiconductor memory device including the first and second gate wirings 3 having a rectangular shape having straight sides with no notches and protrusions. Furthermore, the first and second gate lines 3 can be regularly laid out along the longitudinal direction of the word lines. Thereby, transistor characteristics such as the driver transistor 11, the load transistor 12, and the access transistor 13 constituting the semiconductor memory device can be stabilized and made uniform. Therefore, stable characteristics as a semiconductor memory device can be obtained.

Embodiment 2. FIG.
A semiconductor memory device according to the second embodiment of the present invention will be described with reference to plan views showing configurations of four memory cells in FIGS. Compared with the semiconductor memory device according to the first embodiment, this semiconductor memory device has a distance in the longitudinal direction between the first gate wirings 3a and 3b and the second gate wirings 3c and 3d, as shown in the plan view of FIG. The difference is that (pitch) d1 is substantially equal. Accordingly, since the occurrence of the optical proximity effect can be suppressed in the photolithography process, it is not necessary to change the shape of the gate wiring for the optical proximity effect correction (OPC). Therefore, it is possible to prevent a decrease in yield caused by a transfer margin shortage. Further, the transfer resolution can be improved.

  In this semiconductor memory device, as shown in the plan view of FIG. 13, four memory cells are configured as one repeating unit. That is, the memory cell 10a and the memory cell 10b have mirror symmetry with respect to the configuration of the gate wiring. Also, the memory cell 10a and the memory cell 10c have mirror symmetry with respect to each other. Therefore, the memory cell 10a and the memory cell 10d have the same gate wiring configuration, and the memory cell 10b and the memory cell 10c have the same gate wiring configuration. Note that the repeating unit is not limited to the above case, and a repeating unit including a plurality of memory cells may be configured by appropriately selecting the configuration of the gate wiring.

  As another case of this semiconductor device, as shown in the plan view of FIG. 14, a memory cell array may be configured by using the gate wiring configuration of one memory cell 10a as it is as a repeating unit. In this case, each of the memory cells 10b, 10c, and 10d has the same gate wiring configuration as that of the memory cell 10a.

Embodiment 3 FIG.
A semiconductor memory device according to the third embodiment of the present invention will be described. Compared with the semiconductor memory device according to the second embodiment, this semiconductor memory device has substantially the same length and interval between the first gate wirings 3a and 3b and the second gate wirings 3c and 3d in the longitudinal direction. In addition to being equal to each other, the gate wiring in the direction perpendicular to the longitudinal direction (second direction) is substantially equal in width and interval. Thereby, the optical proximity effect can be suppressed in the photolithography process, so that it is not necessary to change the shape of the gate wiring for the optical proximity effect correction (OPC). Therefore, it is possible to prevent a decrease in yield caused by a transfer margin shortage. Further, by using a regular layout pattern, it is possible to transfer with high accuracy using a super-resolution technique.

  Further, by making the length and width of the first and second gate wirings substantially the same and by making the spacings between the gate wirings the same, the spacing between the layers can be kept uniform. Therefore, as the interlayer insulating film, not only a BPSG film having good sagging properties but also a material having relatively poor sagging properties such as an NSG film and a PSG film can be used. This provides a degree of freedom in material selection and can reduce costs. Furthermore, the material of the interlayer insulating film can be selected according to conditions such as the difficulty of CMP processing, the dielectric constant to be set, the difficulty of generating voids, and soft errors.

Embodiment 4 FIG.
A semiconductor memory device according to Embodiment 4 of the present invention will be described with reference to the graph of FIG. FIG. 15 shows an experimentally obtained relationship between the aspect ratio x of the gate wiring and the number of defects generated when the width (short side W) of the gate wiring is 0.15 μm. In this semiconductor memory device, the aspect ratio x of the long side (L) / short side (W) of the first and second gate wirings is 5 or more. In this way, by setting the aspect ratio of the gate wiring to 5 or more, as shown in FIG. 15, the number of defects such as pattern skipping during transfer can be greatly reduced.

1 semiconductor substrate, 2 element isolation oxide film, 3a, 3b, 3c, 3d polysilicon wiring layer (gate wiring layer), 4 side wall, 5a, 5b, 5c, 5d tungsten wiring layer (LIC wiring layer), 6a, 6b 6c Interlayer insulating film 7 Stack via hole (tungsten buried) 8 First metal wiring layer 9 Second metal wiring layer 10 Memory cell 11 Driver transistor 12 Load transistor 13 Access transistor 14 First via hole 15 Third metal wiring layer, 55a, 55b, 55c, 55d Gate wiring, 57 via hole, 60 memory cell, 61 driver transistor, 62 load transistor, 63 access transistor

Claims (1)

A memory cell array in which memory cells each including a first set and a second set of driver transistors, load transistors, and access transistors are two-dimensionally arranged on a semiconductor substrate;
A plurality of word lines connected to the two-dimensionally arranged memory cells and arranged parallel to each other along a first direction;
A plurality of bit lines connected to each of the memory cells and arranged in parallel to each other along a second direction orthogonal to the first direction;
A rectangular first gate line connecting the first set of the driver transistor and the load transistor and having a straight side;
A rectangular second gate line connected to the access transistor and having a straight side;
A first connector connecting the first gate line, a second set of the driver transistor and the load transistor;
A semiconductor memory device comprising: a second connector for connecting the second gate line and the word line.

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