JP2012074687A - Manufacturing method of wiring board and manufacturing method of mounting structure thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board and a manufacturing method of a mounting structure thereof capable of satisfying requirements of electrical reliability improvement.SOLUTION: A manufacturing method of a wiring board according to an embodiment comprises: a step of forming, on a ground layer 13, a plurality of electrolytic plating layers 14 which are separated from each other in a planar view and include a first layer 15a formed on the ground layer 13 using a DC electrolytic plating method, a second layer 15b formed on the first layer 15a using a reverse electrolytic plating method, and a third layer 15c which is formed on the second layer 15b using the DC electrolytic plating method and serves as the outermost layer; a step of etching a part of the ground layer 13 disposed between the electrolytic plating layers 14 in the planar view; a step of forming an insulation layer 10 on the third layer 15c; a step of forming a through hole P in the insulation layer 10 so as to expose a part of the third layer 15c on the bottom of the through hole P; and a step of forming a sputtered layer 16 on the inner wall surface and the bottom of the through hole P.

Description

  The present invention relates to a method for manufacturing a wiring board used for electronic devices (for example, various audiovisual devices, home appliances, communication devices, computer devices and peripheral devices thereof), and a method for manufacturing a mounting structure thereof.

  2. Description of the Related Art Conventionally, as a mounting structure in an electronic device, an electronic component mounted on a wiring board is used.

  In Patent Document 1, a step of forming a pad by a semi-additive method, a step of forming an insulating layer on the pad, an opening is formed in the insulating layer, and an upper surface of the pad is exposed in the opening. And a step of forming an adhesion layer on the surface of the insulating layer constituting the opening and the upper surface of the pad by a sputtering method.

  By the way, when the pad is formed by the semi-additive method, the metal crystal grain boundary constituting the upper surface of the pad is easily etched by the etching solution used for etching the base layer, and therefore, a recess is easily formed in the crystal grain boundary. In this case, when the adhesion layer is formed on the upper surface of the pad by the sputtering method, the particles scattered from the target toward the upper surface of the pad do not easily reach the recess of the crystal grain boundary, so the inner wall of the recess is covered with the adhesion layer. Hateful. For this reason, peeling is likely to occur between the pad and the adhesion layer, so that disconnection is likely to occur between the pad and the through conductor, and as a result, the electrical reliability of the wiring board is likely to be reduced.

JP 2009-188324 A

  The present invention provides a method for manufacturing a wiring board and a method for manufacturing a mounting structure in response to a demand for improving electrical reliability.

  A method of manufacturing a wiring board according to an aspect of the present invention includes a first layer formed on a base layer using a direct current electrolytic plating method, and a first layer formed on the first layer using a reverse electrolytic plating method. A plurality of electrolytic plating layers separated from each other in a plan view are formed on the underlayer having two layers and a third layer forming the outermost layer formed on the second layer using a direct current electrolytic plating method A step of etching, a step of etching a part of the base layer disposed between the electrolytic plating layers in a plan view, a step of forming an insulating layer on the third layer, and the bottom surface of the through hole In order to expose a part of the third layer, the method includes a step of forming the through hole in the insulating layer and a step of forming the sputter layer on the inner wall surface and the bottom surface of the through hole. .

  A manufacturing method of a mounting structure according to an embodiment of the present invention includes a step of electrically connecting an electronic component to a wiring board obtained by the above-described wiring board manufacturing method.

According to the method for manufacturing a wiring board and the method for manufacturing a mounting structure according to an aspect of the present invention, the third layer can improve the flatness of one main surface of the conductive layer exposed on the bottom surface of the through hole. The bottom surface of the through hole can be more uniformly covered with the sputter layer. As a result, since the adhesive strength between the conductive layer and the sputtered layer can be increased, disconnection between the conductive layer and the through conductor can be reduced, and thus a wiring board excellent in electrical reliability can be obtained.

1A is a cross-sectional view of a mounting structure according to an embodiment of the present invention cut in the thickness direction, and FIG. 1B is an R1 portion of the mounting structure shown in FIG. It is sectional drawing which expanded and showed. FIG. 2 is an enlarged cross-sectional view of the R2 portion of the mounting structure shown in FIG. 3 (a), 3 (b), 3 (c) and 3 (d) are cross-sectional views cut in the thickness direction for explaining the manufacturing process of the mounting structure shown in FIG. 1 (a). . 4 (a), 4 (b), and 4 (c) illustrate the manufacturing process of the mounting structure shown in FIG. 1 (a), and enlarges the portion corresponding to the R3 portion of FIG. 3 (c). It is sectional drawing shown. FIG. 5A is a timing chart of the DC electrolytic plating method in the manufacturing process of the mounting structure shown in FIG. 1A, and FIG. 5B is the manufacturing of the mounting structure shown in FIG. It is a timing chart of the inversion electrolytic plating method in a process. FIGS. 6A and 6B are cross-sectional views cut in the thickness direction for explaining the manufacturing process of the mounting structure shown in FIG. 7 (a) and 7 (b) are enlarged cross-sectional views illustrating a manufacturing process of the mounting structure shown in FIG. 1 (a), showing a portion corresponding to the R4 portion in FIG. 6 (b). It is. FIG. 8A and FIG. 8B are cross-sectional views cut in the thickness direction for explaining the manufacturing process of the mounting structure shown in FIG.

  Below, the manufacturing method of the mounting structure using the manufacturing method of the wiring board which concerns on one Embodiment of this invention is demonstrated in detail based on drawing.

  A mounting structure 1 shown in FIG. 1A is manufactured using the manufacturing method of the mounting structure according to the present embodiment. For example, various audiovisual devices, home appliances, communication devices, computer devices, It is used for electronic devices such as peripheral devices. The mounting structure 1 includes an electronic component 2 and a wiring board 4 on which the electronic component 2 is flip-chip mounted via bumps 3.

  The electronic component 2 is a semiconductor element such as an IC or LSI, for example, and a base material is formed of a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphorus, gallium nitride, or silicon carbide. The thickness of the electronic component 2 is set to 0.1 mm or more and 1 mm or less, for example. The coefficient of thermal expansion in each direction of the electronic component 2 is set to, for example, 3 ppm / ° C. or more and 5 ppm / ° C. or less. In addition, the thermal expansion coefficient of the electronic component 2 is measured by a measuring method according to JISK7197-1991 using a commercially available TMA apparatus. Hereinafter, the coefficient of thermal expansion of each member is measured in the same manner as the electronic component 2.

  The bump 3 is formed of a conductive material such as solder including, for example, lead, tin, silver, gold, copper, zinc, bismuth, indium, or aluminum.

  The wiring substrate 4 includes a core substrate 5 and a pair of wiring layers 6 formed above and below the core substrate 5.

  The core substrate 5 increases the strength of the wiring substrate 4, and includes a base body 7 in which a through hole T is formed along the thickness direction, a cylindrical through hole conductor 8 formed in the through hole T, and the core substrate 5. And a columnar insulator 9 formed in a region surrounded by the through-hole conductor 8.

  The base body 7 is a main part of the core substrate 5 to increase the rigidity, and includes a resin part, a base material covered with the resin part, and an inorganic insulating filler covered with the resin part. . The thickness of the base body 7 is set to, for example, 0.1 mm or more and 1 mm or less. The coefficient of thermal expansion in the plane direction of the substrate 7 is set to, for example, 5 ppm / ° C. or more and 30 ppm / ° C. or less, and the coefficient of thermal expansion in the thickness direction of the substrate 7 is set to, for example, 15 ppm / ° C. or more and 50 ppm / ° C. or less. Yes. In addition, the base | substrate 7 does not need to contain a base material and does not need to contain an inorganic insulating filler.

  The resin portion of the substrate 7 is formed of a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin, a cyanate resin, a polyphenylene ether resin, a wholly aromatic polyamide resin, or a polyimide resin. The resin portion may be formed of a thermoplastic resin such as a fluorine resin, an aromatic liquid crystal polyester resin, a polyether ketone resin, a polyphenylene ether resin, or a polyimide resin.

  As a base material of the base | substrate 7, the woven fabric or nonwoven fabric comprised with the fiber, or what arranged the fiber in one direction can be used. Moreover, as a fiber which comprises a base material, glass fiber, a resin fiber, carbon fiber, a metal fiber etc. can be used, for example.

  The inorganic insulating filler of the base 7 is to make the base 7 highly rigid and low in thermal expansion, and is composed of a plurality of particles formed of an inorganic insulating material such as silicon oxide.

  The through-hole conductor 8 electrically connects the upper and lower wiring layers 6 of the core substrate 5, and has the same configuration as the first conductive layer 11 a described later on the inner wall of the through-hole T.

  The insulator 9 supports a through conductor 12 described later, and is formed of a resin material such as polyimide resin, acrylic resin, epoxy resin, cyanate resin, fluorine resin, silicon resin, polyphenylene ether resin, or bismaleimide triazine resin. Has been.

  On the other hand, a pair of wiring layers 6 are formed above and below the core substrate 5 as described above. The wiring layer 6 includes an insulating layer 10 in which a through hole P is formed along the thickness direction, a conductive layer 11 formed on the substrate 7 or the insulating layer 10, and a conductive layer 11 formed in the through hole P. And a through conductor 12 connected to the.

  The insulating layer 10 functions as an insulating member that prevents a short circuit between the conductive layers 11, and includes a first resin layer 10 a and a second resin layer 10 b disposed closer to the core substrate 5 than the first resin layer 10 a. And. The thickness of the insulating layer 10 is set to, for example, 5 μm or more and 40 μm or less.

The first resin layer 10a increases the rigidity of the insulating layer 10 and reduces the coefficient of thermal expansion in the planar direction, and includes a resin portion and an inorganic insulating filler coated on the resin portion. The thickness of the 1st resin layer 10a is set to 20 micrometers or less above 2 micrometers, for example. The thermal expansion coefficient in the planar direction of the first resin layer 10a is set to, for example, 0 ppm / ° C. or more and 30 ppm / ° C. or less, and the thermal expansion coefficient in the thickness direction of the first resin layer 10a is, for example, 20 ppm / ° C. or more. It is set to 50 ppm / ° C. or less. In addition, the 1st resin layer 10a does not need to contain an inorganic insulating filler.

  The resin portion of the first resin layer 10a is formed of a thermoplastic resin such as a polyimide resin, for example. By using such a thermoplastic resin, the first resin layer 10a can have high rigidity and a low coefficient of thermal expansion. In addition, the resin part included in the first resin layer 10a is preferably a film having a structure in which the longitudinal directions of the resin molecular chains are the same. As a result, the coefficient of thermal expansion in the planar direction can be reduced.

  The inorganic insulating filler of the first resin layer 10a makes the first resin layer 10a highly rigid and low in thermal expansion, and is formed of, for example, the same material as the inorganic insulating filler of the base 7 described above.

  The second resin layer 10b adheres the first resin layers 10a adjacent to each other in the thickness direction, or the base body 7 and the first resin layer 10a, and adheres to the side surface and one main surface of the conductive layer 11 to form the conductive layer 11. And includes a resin portion and an inorganic insulating filler coated on the resin portion. The thickness of the second resin layer 10b is set to, for example, 2 μm or more and 20 μm or less. The coefficient of thermal expansion in each direction of the second resin layer 10b is set to, for example, 10 ppm / ° C. or more and 40 ppm / ° C. or less. In addition, the 2nd resin layer 10b does not need to contain an inorganic insulating filler.

  The resin part of the second resin layer 10b is formed of a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin, a cyanate resin, or an amide resin. By using such a thermosetting resin, the 1st resin layers 10a adjacent to the thickness direction, or the base | substrate 7 and the 1st resin layer 10a can be adhere | attached firmly.

  The inorganic insulating filler of the second resin layer 10b is to make the second resin layer 10b highly rigid and low in thermal expansion. For example, from the plurality of particles formed of the same material as the inorganic insulating filler of the base 7 described above. Become.

  The conductive layer 11 functions as a ground wiring, a power supply wiring, or a signal wiring. The side surface and one main surface are bonded to the second resin layer 10b, and the other main surface is the base 7 or the first resin layer. It adheres to 10a. In addition, the conductive layer 11 has one main surface and a part of the other main surface connected to the through conductor 12. The conductive layer 11 includes a first conductive layer 11a formed on the base 7 and a second conductive layer 11b formed on the first resin layer 10a.

  As shown in FIG. 1B, the first conductive layer 11a includes an electroless plating layer 13 formed on the substrate 7 using an electroless plating method, and an electroless plating layer 13 using an electroplating method. And an electroplating layer 14 formed on the substrate. The thickness of the first conductive layer 11a is set to, for example, 8.5 μm or more and 10.5 μm or less. The arithmetic mean roughness (Ra) of one principal surface S1 of the first conductive layer 11a (one principal surface bonded to the second resin layer 10b) is set to, for example, 0.1 μm or more and 0.5 μm or less. The arithmetic average roughness of the other main surface S2 of the conductive layer 11a (the other main surface bonded to the base 7) is set to, for example, 0.5 μm or more and 2 μm or less. The arithmetic average roughness conforms to ISO 4287: 1997.

  The arithmetic average roughness (Ra) of the one main surface S1 of the first conductive layer 11a is preferably smaller than the arithmetic average roughness of the other main surface S2 of the first conductive layer 11a. As a result, by reducing the arithmetic average roughness of the one principal surface S1 of the first conductive layer 11a, the first conductive layer 11a is improved while increasing the adhesive strength between the first conductive layer 11a and the sputtered layer 16 as described later. By reducing the arithmetic average roughness of the other main surface S2, the anchor effect can be enhanced and the adhesive strength between the first conductive layer 11a and the substrate 7 can be increased.

  The electroless plating layer 13 of the first conductive layer 11 a is interposed between the base 7 and the electrolytic plating layer 14 and functions as a base layer for the electrolytic plating layer 14. The electroless plating layer 13 is made of copper, for example. The electroless plating layer 13 may contain phosphorus, palladium, tin or the like in addition to copper. The thickness of the electroless plating layer 13 is set to, for example, 0.3 μm or more and 0.5 μm or less.

  The electrolytic plating layer 14 of the first conductive layer 11a is a main part of the first conductive layer 11a, and is formed of copper, which is a material with high conductivity. The electrolytic plating layer 14 includes a first layer 15a formed on the electroless plating layer 13 using a direct current electrolytic plating method, and a second layer 15b formed on the first layer 15a using a reverse electrolytic plating method. And a third layer 15c, which is the outermost layer, formed on the second layer 15b using a direct current electrolytic plating method. The thickness of the electrolytic plating layer 14 is set to 7.5 μm or more and 13 μm or less, for example. In the electrolytic plating layer 14, the first layer 15a, the second layer 15b, and the third layer 15c are obtained by observing the crystal state with a scanning ion microscope of a cross section obtained by cutting the electrolytic plating layer 14 along the thickness direction. Can be distinguished.

  The first layer 15a of the electroplating layer 14 is interposed between the electroless plating layer 13 and the second layer 15b. Since the first layer 15a is densely deposited on the surface of the base layer as compared with the second layer 15b, the adhesive strength with the electroless plating layer 13 is high. Moreover, since the 1st layer and the 2nd layer 15b are continuously formed by the electroplating method so that it may mention later, adhesive strength is high. Therefore, since the adhesive strength between the electroless plating layer 13 and the second layer 15b can be increased by the first layer 15a, the peeling between the electroless plating layer 13 and the electrolytic plating layer 14 is reduced, and consequently the conductive layer. 11 disconnection can be reduced. The thickness of the first layer 15a is set to, for example, 0.8 μm or more and 1.2 μm or less.

  The second layer 15 b of the electrolytic plating layer 14 is a main part of the electrolytic plating layer 14. As will be described later, the second layer 15b is easily formed with a uniform thickness as compared with the direct current electrolytic plating layer. Therefore, the thickness of the conductive layer 11 can be made more uniform by the second layer 15 b, and thus disconnection of the conductive layer 11 due to the variation in the thickness of the conductive layer 11 can be reduced. The thickness of the second layer 15b is set to, for example, 5.5 μm or more and 6.5 μm or less.

  The third layer 15c of the electrolytic plating layer 14 is a member that constitutes one main surface S2 of the first conductive layer 11a and to which the through conductor 12 is connected. Since the third layer 15c has a larger crystal grain size and fewer crystal grain boundaries than the second layer 15b, the third layer 15c has high ductility and thus is less susceptible to cracking. Therefore, when a stress is applied to one main surface of the conductive layer 11, the third layer 15 c can reduce cracks in the conductive layer 11, and thus reduce disconnection of the conductive layer 11. The thickness of the third layer 15c is set to, for example, 1.5 μm or more and 2.5 μm or less.

  The second conductive layer 11b includes a sputter layer 16 formed on the first resin layer 10a using a sputtering method, and an electrolytic plating layer 14 formed on the sputter layer 16 using an electrolytic plating method. Yes. The thickness of the second conductive layer 11b is set to, for example, not less than 4.5 μm and not more than 6.5 μm. The arithmetic average roughness of one main surface S3 of the second conductive layer 11b (one main surface bonded to the second resin layer 10b) is set to, for example, 0.1 μm or more and 2 μm or less, and other than the second conductive layer 11b. The arithmetic average roughness of the main surface S4 (the other main surface bonded to the first resin layer 10a) is set to, for example, 0.01 μm or more and 1 μm or less.

The sputter layer 16 of the second conductive layer 11b is interposed between the first resin layer 10a and the electrolytic plating layer 14, and functions as a base layer of the electrolytic plating layer 14. Thus, by making the base layer into the sputter layer 16, it is possible to bond the first resin layer 10a to the first resin layer 10a without roughening the first resin layer 10a as compared with the case where the base layer is the electroless plating layer 13. A foundation layer having high strength can be formed. Therefore, the second conductive layer 11b can be made finer in the wiring layer 6 by not roughening the first resin layer 10a. As shown in FIG. 2, the sputter layer 16 is formed on the first sputter layer 16a using the sputtering method and the first sputter layer 16a formed on the first resin layer 10a using the sputtering method. And a second sputter layer 16b. Further, the thickness of the sputter layer 16 is set to, for example, 0.55 μm or more and 0.6 μm or less.

  The first sputter layer 16a adheres to the first resin layer 10a and is formed of a conductive material such as nickel chrome alloy or titanium. Since the first sputtered layer 16a is formed of such a conductive material, the adhesive strength between the first sputtered layer 16a and the first resin layer 10a made of a thermoplastic resin is high. Therefore, the adhesive strength between the first resin layer 10a and the sputter layer 16 can be increased by the first sputter layer 16a. The thickness of the first sputter layer 16a is set to, for example, 0.07 μm or more and 0.08 μm or less.

  The second sputter layer 16b is interposed between the first sputter layer 16a and the electrolytic plating layer 14, and is formed of copper. As described above, since the second sputtered layer 16b is formed of copper, which is the same material as the electrolytic plated layer 14, the adhesive strength between the second sputtered layer 16b and the electrolytic plated layer 14 is high. Moreover, since the 1st sputter layer 16a and the 2nd sputter layer 16b are continuously formed by the sputtering method so that it may mention later, adhesive strength is high. Therefore, the adhesive strength between the sputtered layer 16 and the electrolytic plating layer 14 can be increased by the second sputtered layer 16b. The thickness of the second sputter layer 16b is set to be 0.48 μm or more and 0.52 μm or less, for example.

  The electrolytic plating layer 14 of the second conductive layer 11b includes a first layer 15a, a second layer 15b, and a third layer 15c, similarly to the electrolytic plating layer 14 of the first conductive layer 14a described above.

  The thickness of the second layer 15b in the second conductive layer 11b is smaller than the thickness of the second layer 15b in the first conductive layer 11a. As a result, by increasing the thickness of the second layer 15b in the first conductive layer 11a, the thickness of the through-hole conductor 8 formed at the same time as the first conductive layer 11a is increased and the reliability is improved while increasing the reliability. By increasing the thickness of the second layer 15b in 11b, the thickness of the second conductive layer 11b can be reduced and the wiring density can be increased in the wiring portion 6. The thickness of the second layer 15b in the second conductive layer 11b is set to, for example, 1.5 μm or more and 2.5 μm or less, for example, 30% or more and 40% or less of the thickness of the second layer 15b in the first conductive layer 11a. Is set.

  Other configurations of the electrolytic plating layer 14 of the second conductive layer 11b are the same as the configurations of the electrolytic plating layer 14 of the second conductive layer 11b.

  The through conductor 12 connects the conductive layers 11 separated in the thickness direction, and is formed in a tapered shape that becomes narrower toward the core substrate 5, and the conductive layer 11 is formed at the bottom surface of the through hole P. Connected with. The through conductor 12 includes a sputter layer 16 formed on the inner wall and the bottom surface of the through hole P, and an electrolytic plating layer 14 formed on the sputter layer 16 layer. The sputter layer 16 and the electrolytic plating layer 14 of the through conductor 12 have the same configuration as the sputter layer 16 and the electrolytic plating layer 14 of the second conductive layer 11b.

  By the way, when heat is applied to the wiring board, thermal stress is likely to be applied to the connection portion between the conductive layer 11 and the through conductor 12.

On the other hand, in the wiring board 3 of the present embodiment, the through conductor 12 is the third layer 15 of the conductive layer 11.
connected on c. As a result, since the third layer 15c has a high spreadability as described above, when the thermal stress is applied to the connection portion between the conductive layer 11 and the through conductor 12, the conductive layer 11 caused by the thermal stress. Cracks can be reduced. Therefore, it is possible to reduce the disconnection of the conductive layer 11 and to obtain a wiring board having excellent electrical reliability.

  The thickness of the third layer 15c is preferably larger than the thickness of the first layer 15a. As a result, by increasing the thickness of the third layer 15c, the strength of the upper surface of the conductive layer 11 can be further increased, so that cracks in the conductive layer 11 due to thermal stress can be reduced, and consequently the conductive layer. 11 disconnection can be reduced. Further, by reducing the thickness of the first layer 15a, the variation in the thickness of the conductive layer 11 due to the direct current electrolytic plating layer can be reduced, and consequently the disconnection of the conductive layer 11 can be reduced. The thickness of the third layer 15c is set to be, for example, 1.5 times or more and 2.5 times or less of the thickness of the first layer 15a.

  Moreover, it is desirable that the thickness of the first layer 15a and the third layer 15c is smaller than the thickness of the second layer 15b. As a result, since the ratio (volume%) occupied by the second layer 15b in the conductive layer 11 can be increased, variation in the thickness of the conductive layer 11 can be reduced, and thus disconnection of the conductive layer 11 can be reduced. In the first conductive layer 11, the thickness of the first layer 15a is set to, for example, 10% or more and 20% or less of the thickness of the second layer 15b, and the thickness of the third layer 15c is the thickness of the second layer 15b. For example, the thickness is set to 35% or more and 45% or less. In the second conductive layer 11, the thickness of the first layer 15a is set to, for example, 45% or more and 55% or less of the thickness of the second layer 15b, and the thickness of the third layer 15c is equal to that of the second layer 15b. For example, the thickness is set to 75% or more and 125% or less.

  Thus, the mounting structure 1 described above exhibits a desired function by driving or controlling the electronic component 2 based on the power supply and signals supplied via the wiring board 4.

  Next, the manufacturing method of the mounting structure 1 mentioned above is demonstrated based on FIGS.

  (1) As shown in FIGS. 3A and 3B, a base body 7 is formed, and a through hole T is formed in the base body 7. Specifically, for example, the following is performed.

  First, a plurality of resin sheets containing an uncured thermosetting resin are laminated, the laminated body is heated and pressed, and the thermosetting resin is cured, whereby the substrate 7 is produced. The uncured state is an A-stage or B-stage according to ISO 472: 1999. Next, the through hole T penetrating the base body 7 in the thickness direction is formed by, for example, drilling or laser processing.

  (2) As shown in FIG. 3C, the through-hole conductor 8 is formed in the through-hole T and the first conductive layer 11a is formed on the substrate 7, and then as shown in FIG. The insulator 9 is formed by filling the inside of the through-hole conductor 8 with a resin material. Specifically, the through-hole conductor 8 and the first conductive layer 11a are formed as follows, for example.

  First, as shown in FIG. 4A, the electroless plating layer 13 is formed by depositing copper on both main surfaces of the substrate 7 and the inner wall of the through hole T using an electroless plating method. Next, as shown in FIG. 4B, an electrolytic plating layer 14 is partially formed on the electroless plating layer 13 that is the base layer on both main surfaces of the substrate 7. Next, in FIG. 4 (c), using an etching solution such as a mixed solution of hydrogen peroxide solution and sulfuric acid aqueous solution or a mixed solution of hydrochloric acid, nitric acid and iron chloride aqueous solution, The first conductive layer 11a and the through-hole conductor 8 can be formed by etching a part of the electrolytic plating layer 13 along the thickness direction.

  Hereinafter, the formation method of the electroplating layer 14 of this embodiment is demonstrated in detail.

First, copper is partially deposited on the electroless plating layer 13 by a direct current electroplating method using a direct current to form the first layer 15a. Next, the first layer 1 is formed by reverse electroplating (PR method) in which the direction of current flow is alternately reversed.
Copper is deposited on 5a to form the second layer 15b. Next, the third layer 15c is formed by depositing copper on the second layer 15b by DC electrolytic plating.

In the direct current electrolytic plating method, as shown in FIG. 5 (a), a substantially constant current is passed in the direction D1 in which the underlayer becomes the cathode. Therefore, in the first layer 15a and the third layer 15c, since the copper crystal grows continuously, the crystal grows larger than the second layer 15b in which the copper crystal grows intermittently. There are few crystal grain boundary formation regions. Therefore, the first layer 15a and the third layer 15c are less likely to cause cracks because cracks due to crystal grain boundaries are reduced when stress is applied compared to the second layer 15b. In the DC electrolytic plating method, the current density is set to, for example, 0.5 A / dm ² or more and 2 A / dm ² or less. Moreover, the time (henceforth t1) which flows an electric current when forming the 1st layer 15a is set to 2 minutes or more and 10 minutes or less, for example. In addition, the time (hereinafter referred to as t2) during which current is passed when forming the third layer 15c is set to, for example, 6 minutes to 27 minutes. Moreover, t1 is set longer than t2, and is set to be not less than 2 times and not more than 5 times t2, for example.

  In the reverse electrolytic plating method, as shown in FIG. 5B, the direction in which the direct current flows is periodically reversed alternately. Specifically, first, by flowing an electric current in the direction D1 in which the underlayer becomes the cathode, copper ions in the plating solution are reduced to deposit copper on the underlayer. Next, the direction in which the current flows is reversed, and the current is passed in the direction D2 in which the underlayer becomes the anode, so that the copper in the underlayer is oxidized and the copper ions are eluted from the underlayer into the plating solution. Next, the reversal of the direction of the current is periodically and alternately performed. At this time, by making the value of the product of the current density and the pulse width when the base layer is the cathode larger than the value of the product of the current density and the pulse width when the base layer is the anode, Since the deposition amount becomes larger than the elution amount of copper ions, the second layer 15b can be formed.

  Here, the current density when the base layer is used as an anode is set higher than the current density when the base layer is used as a cathode, and the pulse width when the base layer is used as an anode is set as the pulse width when the base layer is used as a cathode. Shorter than the pulse width. Thereby, when an underlayer is an anode, elution of copper ions at a portion where the copper thickness is large can be enhanced. Therefore, when the underlayer is a cathode, even if the current density is increased at the opening of the through hole or the like and the thickness of the copper deposited on the underlayer varies, the underlayer is an anode. By eluting a large amount of copper ions at a portion where the copper thickness is large, variation in the thickness of the copper deposited on the underlayer can be reduced. Therefore, the second layer 15b can be formed to have a uniform thickness as compared with the first layer 15a and the third layer 15c.

In the reverse electroplating method, the current density when the underlying layer is an anode is, for example, 1 A / d
The current density when the base layer is a cathode is set to 0.5 A / dm ² or more and 2 A / dm ² or less, for example, from m ^{2 to} 5 A / dm ² . In the reversal electrolytic plating method, the pulse width when the base layer is an anode is set to, for example, 0.5 ms to 3 ms, and the pulse width when the base layer is a cathode is set to, for example, 10 ms to 30 ms. Is done.

As described above, it is possible to form the electrolytic plating layer 14 including the first layer 15a, the second layer 15b, and the third layer 15c and having one main surface where the third layer 15c is exposed. The electrolytic plating layer 14 formed in this way increases the adhesive strength with the electroless plating layer 13 that is the base layer by the first layer 15a, and increases the flatness by making the thickness more uniform by the second layer 15b. The third layer 15c can reduce an exposed formation region of the crystal grain boundary on one main surface.

  By the way, when etching a part of the electroless plating layer 13 exposed from the electrolytic plating layer 14 along the thickness direction using an etching solution, one exposed main surface of the electrolytic plating layer 14 is immersed in the etching solution. Is done. As a result, the etching solution etches the crystal grain boundary more than other regions, so that a recess is easily formed in the crystal grain boundary.

  On the other hand, in the method of manufacturing the wiring board 4 of the present embodiment, as described above, the third layer 15c reduces the formation region of the crystal grain boundary on one main surface where the electrolytic plating layer 14 is exposed. The concave portions due to the etching solution can be reduced, and as a result, the first conductive layer 11a having high flatness with the concave portions of the exposed one main surface being reduced can be formed.

  (3) As shown in FIGS. 6A and 6B, the insulating layer 10 is formed on the first conductive layer 11 a, and the through hole P is formed in the insulating layer 10. Specifically, for example, it is performed as follows.

  First, after disposing the film-like first resin layer 10a on the third layer 15c of the first conductive layer 11a via the second resin layer 10b containing an uncured thermosetting resin, the core substrate 7, The insulating layer 10 is formed on the third layer 15c of the first conductive layer 11a by heating and pressing the second resin layer 10b and the first resin layer 10a to cure the thermosetting resin of the second resin layer 10b. Next, the through hole P is formed in the insulating layer 10 by, for example, a YAG laser device or a carbon dioxide laser device, and the third layer 15c of the first conductive layer 11a is exposed on the bottom surface of the through hole P. The exposed third layer 15c forms one main surface of the first conductive layer 11a exposed on the bottom surface of the through hole P, as shown in FIG.

  (4) As shown in FIG. 7B, the first sputter layer 16a and the second sputter layer 16b are sequentially formed on the first resin layer 10a and on the inner wall and bottom surface of the through hole P using a sputtering apparatus. A sputter layer 16 is formed by deposition.

  Here, in the manufacturing method of the wiring board 4 of the present embodiment, the concave portion due to the etching solution is reduced in the main surface of the first conductive layer 11a exposed on the bottom surface of the through hole P in the step (2). ing. As a result, a larger area can be covered with the sputter layer 16 on one main surface of the first conductive layer 11a exposed at the bottom surface of the through hole P. Therefore, adhesion between the first conductive layer 11a and the sputter layer 16 can be achieved. It is possible to increase the strength, reduce the disconnection between the first conductive layer 11a and the via conductor 12, and thus obtain the wiring substrate 4 excellent in electrical reliability.

  (5) As shown in FIG. 8A, the electrolytic plating layer 14 is partially formed on the sputter layer 16 which is the base layer, and a part of the sputter layer 16 exposed between the electrolytic plating layers 14 is formed into a thickness. By etching along the direction, the through conductor 12 is formed in the through hole P and the second conductive layer 11b is formed on the first resin layer 10a. Specifically, it can be performed in the same manner as the step (2).

  (6) As shown in FIG. 8B, by repeating the steps (3) to (5) described above, the wiring layer 6 can be formed and the wiring board 4 can be manufactured.

  (7) The mounting structure 1 shown in FIG. 1 can be manufactured by flip-chip mounting the electronic component 2 on the wiring board 4 via the bumps 3.

  The present invention is not limited to the above-described embodiments, and various modifications, improvements, combinations, and the like can be made without departing from the spirit of the present invention.

  For example, in the above-described embodiment of the present invention, the wiring layer is formed by three insulating layers, but the insulating layer may be one layer, two layers, or four layers or more.

  In the above-described embodiment, the insulating layer having both the first resin layer and the second resin layer is used. However, the insulating layer may be formed only by the second resin layer, or other resin. It may be formed of layers.

  In the above-described embodiment, the third layer is formed on both the first conductive layer and the second conductive layer. However, the third layer is formed only on either the first conductive layer or the second conductive layer. It doesn't matter.

  In the above-described embodiment, the through conductor is filled with the electrolytic plating layer. However, the through conductor may not be filled with the electrolytic plating layer, and the electrolytic plating layer may be formed in a film shape. I do not care.

  In the above-described embodiment, the electroless plating layer and the sputter layer are used as the base layer of the electrolytic plating layer. However, the base layer only needs to function as the base of the electrolytic plating layer, for example, other than the sputtering method. You may form by the vapor deposition method of this.

  In the above-described embodiment, the sputter layer has both the first sputter layer and the second sputter layer, but the sputter layer has only one of the first sputter layer and the second sputter layer. It does not matter.

DESCRIPTION OF SYMBOLS 1 Mounting structure 2 Electronic component 3 Wiring board 4 Bump 5 Core board 6 Wiring layer 7 Base body 8 Through-hole conductor
DESCRIPTION OF SYMBOLS 9 Insulator 10 Insulating layer 10a 1st resin layer 10b 2nd resin layer 11 Conductive layer 11a 1st conductive layer 11b 2nd conductive layer 12 Through conductor 13 Electroless plating layer 14 Electrolytic plating layer 15a 1st layer 15b 2nd layer 15c Third layer 16 Sputtered layer 16a First sputtered layer 16b Second sputtered layer T Through hole P Through hole

Claims (5)

A first layer formed on the underlayer using a direct current electrolytic plating method, a second layer formed on the first layer using a reverse electrolytic plating method, and the second layer formed using a direct current electrolytic plating method. Forming a plurality of electrolytic plating layers spaced apart from each other in a plan view, the third layer forming the outermost layer formed on the layer, and
Etching a part of the base layer disposed between the electrolytic plating layers in plan view;
Forming an insulating layer on the third layer;
Forming the through hole in the insulating layer in order to expose a part of the third layer on the bottom surface of the through hole;
Forming the sputter layer on the inner wall surface and the bottom surface of the through hole;
A method of manufacturing a wiring board, comprising: In the manufacturing method of the wiring board of Claim 1,
The method for manufacturing a wiring board, wherein the thickness of the third layer is larger than the thickness of the first layer. In the manufacturing method of the wiring board of Claim 1,
The thickness of the said 2nd layer is larger than the thickness of the said 1st layer and the said 3rd layer, The manufacturing method of the wiring board characterized by the above-mentioned. In the manufacturing method of the wiring board of Claim 1,
The method for manufacturing a wiring board, wherein the first layer, the second layer, and the third layer contain copper.   A method for manufacturing a mounting structure comprising a step of electrically connecting an electronic component to a wiring board obtained by the method for manufacturing a wiring board according to claim 1.

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