JP2012074675A - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of forming a semiconductor layer having excellent crystallinity on an insulating layer.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming an amorphous semiconductor layer 43 having a thickness of 4 nm to 1 μm above an insulating layer 41; and crystallizing the semiconductor layer 43 by irradiating the semiconductor layer 43 with an energy beam having a wavelength within a range from 350 to 500 nm.

Description

  The present invention relates to a method for manufacturing a semiconductor device including a crystallized silicon layer (thin film, thick film, etc.) and a semiconductor device that can be manufactured by this manufacturing method.

  In a flat panel display (FPD), a TFT (thin film transistor) is formed on a thin film formed on a glass substrate to drive a display element that displays an image.

Conventionally, a polysilicon TFT has been used as a high-performance TFT (thin film transistor) because of its high mobility and ease of film formation. Mobility, organic TFT is 0.5 cm ² / Vs or less, while the hydrogenated amorphous silicon TFT is 0.3~1cm ² / Vs, poly-silicon TFT is to be increased to 10~400cm ² / Vs Is possible.
This polysilicon TFT is the only configuration capable of forming a CMOS structure on a glass substrate.

As a typical example of such a polysilicon TFT, a schematic cross-sectional view of a top-gate thin film transistor is shown in FIG.
As shown in FIG. 22, a polysilicon thin film 53 of a thin film transistor is formed on a panel 51 such as a glass substrate via a buffer layer 52. A gate electrode 55 is formed on the central portion of the polysilicon thin film 53 via a gate insulating film 54. The polysilicon thin film 53 and the gate electrode 55 are covered with an interlayer insulating layer 56. An electrode layer 57 is connected to the left and right end portions of the polysilicon thin film 53 through contact holes formed in the interlayer insulating layer 56.

Further, in order to realize a high-functional flat panel display, it is required to form a functional circuit element such as a transistor on an arbitrary substrate made of not only a glass substrate but also a plastic substrate or a flexible substrate material.
For example, on a glass substrate or a plastic substrate, not only the pixel portion and peripheral circuit portion of the display, but also a functional sensor, memory, A / D (analog / digital) converter, D / A (digital / analog) converter, It is conceivable that various functional circuit elements such as a CPU are arranged.

Here, FIG. 23 shows a schematic plan view of a configuration in which a display pixel portion and a functional system are provided on an insulating substrate such as a glass substrate or a plastic substrate.
As shown in FIG. 23, a display pixel portion (display portion) 107 is formed on an insulating substrate 101 such as a glass substrate or a plastic substrate, and the insulating substrate 101 around the pixel portion (display portion) 107 is formed. On the top, various circuit element chips and the like are arranged to constitute a display device 100 made of a semiconductor device.

As circuit elements, a CPU (Central Processing Unit) 102, a ROM (Read Only Memory) 103, a RAM (Random Access Memory) 104, an A / D converter 105, and an A / D converter 105 are arranged on the left side in the figure. In addition, a driver IC 106 and the like for driving the pixel portion 107 are provided.
These circuit elements (102, 103, 104, 105, 106) are constituted by chips mounted on the insulating substrate 101.

  Research and development aimed at so-called SoG (System on Glass) and SoP (System on Panel) in which a functional system is configured on an insulating substrate such as a glass substrate or a plastic substrate as shown in FIG. (For example, refer nonpatent literature 1).

  In polysilicon TFTs, the mobility of conductive carriers is increased by increasing the crystal grains of polysilicon (polycrystalline silicon).

  In the FPD, in addition to the polysilicon TFT, a TFT made of an organic semiconductor thin film, an oxide semiconductor (IGZO) or the like is expected to drive the display element. Reliability and integration functionality are not yet fully realized.

In order to form a polysilicon TFT on a plastic substrate or the like, it is required to form polysilicon so that the influence of heat on the plastic substrate is reduced.
For that purpose, for example, it is conceivable to adopt a method of forming a polysilicon layer at a low temperature.

Naoto Matsuo, “Nanotechnology on Display”, Monthly Display, 2006, p. 1

  When forming a polysilicon thin film on an insulating substrate, it is better to crystallize the amorphous silicon thin film after forming the amorphous silicon thin film than to form the polysilicon thin film directly. A polysilicon thin film having good properties can be formed.

In the SPC method (FA method) conventionally employed as a method for crystallizing an amorphous silicon thin film formed on a glass substrate, it takes time to heat slowly in a furnace. Further, since silicon is crystallized without melting, defects tend to remain in the film.
Furthermore, since it is heated at a high temperature in the furnace, it cannot be used for crystallization of a silicon film formed on a plastic substrate.

  A method of crystallizing by irradiating an excimer laser that is a pulse of ultraviolet rays (ELA method) is also conceivable. However, since the absorption coefficient of silicon in the wavelength band is large, the depth direction perpendicular to the film surface Temperature distribution is likely to occur, and it is difficult to achieve good crystallization in a thick silicon layer having a thickness exceeding 100 nm.

  In order to solve the above-described problems, the present invention provides a method for manufacturing a semiconductor device, in which a semiconductor layer with good crystallinity can be formed on an insulating layer. Moreover, the semiconductor device obtained by this manufacturing method is provided.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming an amorphous semiconductor layer having a thickness of 4 nm to 1 μm on an insulating layer, and an energy beam having a wavelength in the range of 350 nm to 500 nm with respect to the semiconductor layer. The step of crystallizing the semiconductor layer by irradiating is performed.

In the semiconductor device manufacturing method of the present invention described above, the semiconductor layer can be configured to include one or more elements selected from Si, Ge, and C.
In the semiconductor device manufacturing method of the present invention described above, glass or plastic can be used as the insulating layer.
In the method for manufacturing a semiconductor device of the present invention, the step of forming an amorphous semiconductor layer may be performed by sputtering using Ne gas or a mixed gas containing Ne gas as a sputtering discharge inert gas. it can.
In the semiconductor device manufacturing method of the present invention described above, after the step of forming the amorphous semiconductor layer by the plasma CVD method, the step of crystallizing the semiconductor layer without performing the heat treatment step for dehydrogenation It can be set as the structure which performs.
The semiconductor device manufacturing method of the present invention may further include a step of introducing an impurity region of an active element into the semiconductor layer before or after the step of crystallizing the semiconductor layer.
In the semiconductor device manufacturing method of the present invention described above, the insulating layer may be formed of plastic, and one or more selected from polyimide resin, polyamideimide resin, and polysilsesquioxane may be used as the plastic.
In the semiconductor device manufacturing method of the present invention described above, a material having a thickness of 0.2 to 1.5 μm and containing 3 atomic% or more of each component of Zn, S, Si, and O on the insulating layer. In this case, a buffer layer may be formed, and then a semiconductor layer may be formed on the buffer layer.

  The semiconductor device of the present invention is a crystalline semiconductor obtained by crystallization by irradiating an amorphous semiconductor layer having a thickness of 4 nm to 1 μm with an energy beam having a wavelength in the range of 350 nm to 500 nm. And an active element including an impurity region formed in the crystalline semiconductor layer.

In the above semiconductor device of the present invention, the active element is a thin film transistor, the amorphous semiconductor layer has a thickness in the range of 4 nm to 100 nm, and the impurity regions are the source region and the drain region of the thin film transistor. be able to.
In the semiconductor device of the present invention described above, the active element is a PIN diode, the thickness of the amorphous semiconductor layer is in the range of 300 nm to 1 μm, and the impurity region is the p-type region and i-type of the PIN diode. A region and an n-type region can be employed. Further, an amorphous second semiconductor layer is formed on the crystalline semiconductor layer, and a second PIN diode is formed on the amorphous second semiconductor layer. be able to.
In the semiconductor device of the present invention described above, the amorphous semiconductor layer may include one or more elements selected from Si, Ge, and C.
In the above-described semiconductor device of the present invention, an insulating layer may be provided below the semiconductor layer, and the insulating layer may be formed of glass or plastic.
In the semiconductor device of the present invention described above, the insulating layer is formed of plastic, and one or more selected from polyimide resin, polyamideimide resin, and polysilsesquioxane may be used as the plastic.
In the semiconductor device of the present invention described above, the thickness is 0.2 to 1.5 μm between the insulating layer and the semiconductor layer, and each component of Zn, S, Si, and O is 3 atomic% or more. It can be set as the structure provided with the buffer layer which consists of the material which contains.

According to the semiconductor device manufacturing method of the present invention described above, since crystallization is performed by irradiating an energy beam in the wavelength range of 350 nm to 500 nm, crystallization can be performed in a relatively short time, and flatness is achieved. Thus, a crystalline semiconductor layer excellent in uniformity, crystallinity and stability can be obtained.
Furthermore, by changing the irradiation condition of the energy beam, it is possible to form a wide range of particles from small particles to large particles, and it is also possible to give crystal grains anisotropy.
According to the method for manufacturing a semiconductor device of the present invention, even when plastic is used for the insulating layer, it is possible to prevent the plastic from being affected during crystallization.

According to the above-described configuration of the semiconductor device of the present invention, the impurity region of the active element is formed in the semiconductor layer obtained by performing crystallization by irradiating the energy beam in the wavelength range of 350 nm to 500 nm. . Since the semiconductor layer obtained by crystallization is excellent in flatness, uniformity, crystallinity, and stability, a semiconductor device including an active element with favorable characteristics can be formed.
Therefore, it is possible to form a high-functional flat panel display, photosensor, or solar cell on an arbitrary substrate by using a semiconductor device including an active element such as a thin film transistor or a diode.

It is a schematic block diagram of the crystallization apparatus used in the 1st Embodiment of this invention. It is a figure explaining the method to crystallize an amorphous semiconductor layer. It is a cross-sectional TEM image of the silicon layer after performing crystallization. It is an analysis result of K-spectrum which is the absorptivity by the spectroscopic ellipsometry of the silicon layer obtained by crystallization. It is a result of the X-ray diffraction method of the silicon layer obtained by crystallization. It is an image by SEM of each sample of AC example. It is the image by TEM of each sample of AC Example. AC is an AFM image of each sample of Comparative Example. D, E It is an image by AFM of each sample of a comparative example. AC is an AFM image of each sample of Examples. It is a figure which shows the relationship between the output of a laser, and the sheet resistance after crystallization. It is a figure which shows the spectrum of N and k by the spectroscopic ellipsometry of the silicon layer after crystallization in the case of using A and B Ar gas and in the case of using Ne gas. It is a figure which shows the Raman spectrum of the silicon | silicone layer after crystallization when A and B output 4.9W and output 5.5W. It is the figure which compared the k spectrum by the spectroscopic ellipsometry of the silicon layer before and after crystallization with the output of 6W. It is the image by the TEM of the silicon layer after performing crystallization with the output 6W. It is the distribution of each element from the surface to the depth of the silicon layer after crystallization at an output of 6 W, measured by SIMS. It is the figure which compared the spectrum by the spectroscopic ellipsometry of the silicon layer before and behind crystallization at the time of using A and B polyimide substrates. It is a schematic block diagram (sectional drawing) of the semiconductor device of the 3rd Embodiment of this invention. It is a schematic block diagram (sectional drawing) of the semiconductor device of the 4th Embodiment of this invention. It is a schematic block diagram (sectional drawing) of the semiconductor device of the 5th Embodiment of this invention. It is a figure which shows a sunlight spectrum and the absorption spectrum of an amorphous silicon and a polycrystalline silicon. 1 is a schematic cross-sectional view of a top-gate thin film transistor. It is a schematic plan view of the structure which provided the pixel part and functional system of the display on the insulated substrate.

Embodiments of the present invention will be described in the following order.
1. 1. Outline of the present invention First Embodiment 3. FIG. Second embodiment 4. Third embodiment 5. Fourth Embodiment Fifth embodiment

<1. Summary of the present invention>
First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an amorphous semiconductor layer having a thickness of 4 nm to 1 μm on an insulating layer, and a wavelength of 350 nm to 500 nm with respect to the amorphous semiconductor layer. A step of crystallizing the semiconductor layer by irradiating the energy beam.

As the insulating layer, an insulating substrate (or insulating material) made of glass or plastic, an insulating layer (eg, a silicon oxide layer) formed on an arbitrary substrate (insulating substrate, metal plate, metal foil, semiconductor substrate, etc.) Oxide layers and nitride layers) can be used.
As the plastic for the insulating layer, it is preferable to use at least one polymer material having a highly crosslinked structure, for example, a polyimide resin, a polyamideimide resin, or a polysilsesquioxane.

As a semiconductor material of the amorphous semiconductor layer, a material containing Si, Ge, C, such as a silicon layer, a SiGe layer, a Ge layer, a SiC layer, or the like can be used. Further, if necessary, an n-type impurity (such as phosphorus) or a p-type impurity (such as boron) is implanted into the semiconductor layer to enhance conductivity.
When the semiconductor layer is configured to include two kinds of elements of Si, Ge, and C, such as a SiGe layer and a SiC layer, the band gap and the absorption coefficient are controlled by the ratio of each element, and the semiconductor layer It is possible to control the sensitivity to light.

Examples of the energy beam within the wavelength range of 350 nm to 500 nm include ultraviolet rays, blue-violet and blue visible light, and laser light emitted from a laser such as a semiconductor laser can be used.
The energy beam may be either a continuous beam (CW) or a pulsed beam (pulse beam).

The amorphous semiconductor layer is formed on the insulating layer by, for example, a sputtering method or a CVD method. As the CVD method, a normal thermal CVD method, for example, a low pressure CVD method or a plasma CVD method can be used. As the sputtering discharge inert gas of the sputtering method, Ar gas, He gas, Xe gas, Ne gas, and a mixed gas using one or more of these gases can be used.
The thickness of the semiconductor layer is 4 nm to 1 μm. According to the manufacturing method of the present invention, crystallization can be performed satisfactorily with respect to the semiconductor layer having a wide range of thickness.

  Note that the manufacturing method of the present invention is not limited to the case where an amorphous semiconductor layer is formed in direct contact with an insulating layer. For example, another layer (a conductor layer such as an electrode layer or another insulating layer) may be formed between the insulating layer and the amorphous semiconductor layer. In the case of manufacturing a bottom gate type TFT or a vertical PIN diode, a semiconductor layer is formed on the electrode layer and the wiring layer.

According to the manufacturing method of the present invention, a polycrystalline or single crystal semiconductor layer can be obtained by crystallizing the semiconductor layer.
Further, since crystallization is performed by irradiating an energy beam within a wavelength range of 350 nm to 500 nm, crystallization can be performed in a relatively short time, and the flatness, uniformity, crystallinity, and stability are excellent. A crystalline semiconductor layer is obtained.
Further, by changing the irradiation condition of the energy beam, a wide range of particles from small particles to large particles can be formed, and the crystal grains can be made anisotropic.

When crystallization is performed by irradiating an excimer laser (for example, wavelength 308 nm), crystallization can be performed in a relatively short time, and excellent crystallinity can be obtained. And flatness cannot be obtained sufficiently. Also, it is difficult to make small crystals (microcrystals, small grain crystals). In addition, since the excimer laser is absorbed at a relatively short distance after entering the semiconductor layer, the absorption is not uniform in the depth direction in the thick semiconductor layer, and sufficient flatness and crystallinity cannot be obtained. Therefore, it is not suitable for crystallization of a thick semiconductor layer.
When crystallization is performed by the SPC method (annealing in the furnace), crystallization takes time and the crystallinity is not good.

According to the literature (RF Wood, CW White and RT Young, “Semiconductor and semimetals”, 26, (1984), p.116), the excimer laser wavelength of 308 nm (energy: about 4.05 eV) The absorption coefficient is about 1.3 × 10 ⁶ cm ⁻¹ , and the absorption coefficient of crystalline silicon is about 1.5 × 10 ⁶ cm ⁻¹ , and the difference between the two is small. On the other hand, when the wavelength of the blue laser is 445 nm (energy is about 3.3 eV), the absorption coefficient of amorphous silicon is about 1 × 10 ⁶ cm ⁻¹ and the absorption coefficient of crystalline silicon is 3 × 10 ^5. It is about cm ⁻¹ , and amorphous silicon is three times or more of crystalline silicon.
For this reason, when a blue laser with a wavelength of 445 nm is irradiated, the absorption coefficient is large in the amorphous state, so that crystallization proceeds with a large amount of energy by absorption, but after the crystallization, the absorption coefficient is small. Therefore, it can be seen that the temperature rise is reduced.

Preferably, a step of forming an amorphous semiconductor layer by a plasma CVD method, which can form an amorphous semiconductor layer with a good film quality over a large area, is performed.
When an amorphous semiconductor layer is formed by the plasma CVD method, hydrogen is contained in the semiconductor layer. Therefore, for example, when crystallization is performed by irradiating an excimer laser as it is, a hole is formed on the surface of the semiconductor layer by the release of hydrogen. Unevenness occurs. In order to prevent this, it is necessary to perform a heat treatment step for dehydrogenation before the crystallization step.
In the manufacturing method of the present invention, the semiconductor layer is crystallized by irradiating with an energy beam having a wavelength in the range of 350 nm to 500 nm. Therefore, when the step of forming an amorphous semiconductor layer by plasma CVD is performed However, a step of crystallizing the semiconductor layer can be performed without performing a heat treatment step for dehydrogenation.
Actually, when the semiconductor layer was crystallized without performing a heat treatment step for dehydrogenation, crystallinity was good and crystal grains having a large grain size were obtained.
This eliminates the heat treatment process for dehydrogenation by irradiating an energy beam in the wavelength range of 350 nm to 500 nm to crystallize the amorphous semiconductor layer instead of the conventional excimer laser annealing. This shows that it is possible to shorten the process and improve the yield.
Therefore, by adopting the crystallization according to the present invention in the manufacturing process of the thin film transistor, the process can be shortened and the yield can be improved, and thereby the manufacturing cost of the thin film transistor can be reduced.

Moreover, when performing the process of forming an amorphous semiconductor layer by sputtering, Ne gas or a mixed gas containing Ne gas is preferably used as the sputtering discharge inert gas. Examples of the mixed gas containing Ne gas include a configuration in which Ne gas is diluted with another gas, and a configuration in which another gas such as Ar gas and Ne gas are mixed.
In the case of sputtering, Ar gas is usually used as an inert noble gas used for plasma discharge. In addition to Ar gas and Ne gas, He gas and Xe gas can also be used as the inert rare gas.
Since Ne has an atomic weight smaller than that of Ar (light mass and small atomic radius), when Ne gas is used, the gas that has entered the semiconductor layer during sputtering during the crystallization by irradiation with an energy beam is a semiconductor. It becomes easy to go out of the layer and the crystallinity is improved.
Since He has a small atomic weight like Ne, gas entering the semiconductor layer at the time of sputtering easily goes out of the semiconductor layer, and crystallinity is improved. Note that the sputtering efficiency (deposition rate) is higher for Ne gas than for He gas.
Since Xe has a considerably large atomic weight, it becomes difficult to enter the semiconductor layer at the time of sputtering, and gas is not generated from the semiconductor layer at the time of crystallization, so that the crystallinity is improved. Since Xe gas is expensive compared to Ne gas, the use of Ne gas provides the same effect as Xe gas at a lower cost.
Then, if Ne gas or a mixed gas containing Ne gas is used as the sputter discharge inert gas, the gas that has entered the semiconductor layer during the sputtering out of the semiconductor layer in the subsequent crystallization process by irradiation with an energy beam. Since it is easy, film roughening can be prevented even when irradiation with relatively high energy is performed. Therefore, quasi-single-crystal grain thin film with high mobility, which is irradiated with high energy in the crystallization process, has larger mobility and is anisotropic and electrically superior as in the case of using the CVD method. Since the selection range of crystal grains having an arbitrary size and shape is increased, a high-performance TFT element can be realized. Therefore, it is possible to realize a high-performance TFT element on a flexible substrate by annealing the sputtered thin film formed on the plastic substrate in a short-time pulsed light mode.

Preferably, the method further includes a step of introducing an impurity region of an active element (a transistor, a diode, or the like) into the semiconductor layer before or after the step of crystallizing the semiconductor layer. As the diode, any of a PIN diode, a so-called Schottky contact diode in which two or any of the electrode portions are metal / semiconductor contacts is possible.
Examples of impurity regions of active elements (transistors, diodes, etc.) include p-type or n-type source / drain regions, p-type regions and n-type regions of diodes.
As the method of introducing the impurity region of the active element, a method of introducing by ion implantation, coating of a film containing impurities such as SoG (Spin on Glass), or the inclusion of impurities in a CVD method gas or a sputtering method target And a method of introducing impurities simultaneously with film formation. Note that, when an impurity is introduced at the same time or immediately after the formation of the amorphous semiconductor layer, that is, before the crystallization step, the crystallization is performed by irradiating the energy beam after introducing the impurity. At the same time, it is possible to activate the impurities. In addition, when a relatively thick semiconductor layer is formed, such as when applied to a vertical structure solar cell or the like, a step of forming a lower impurity region (impurities introduced into an amorphous semiconductor layer or impurities caused by annealing) It is also possible to introduce impurities during or before the step of crystallizing the semiconductor layer, such as crystallization of the semiconductor layer after the activation of the first step.

When a plastic substrate is used as the insulating layer under the semiconductor layer, it is desirable to use a resin having a relatively high heat resistance as the substrate material. An example of such a resin is a polyimide resin having a thermal decomposition start temperature as high as about 500 ° C. Moreover, not only a polyimide resin but also a polymer material having a highly crosslinked structure such as a polyamideimide resin and polysilsesquioxane is preferable.
Further, it is desirable to provide a buffer layer between the plastic substrate and the silicon layer.
In addition, as a structure of a buffer layer at the time of using a polyimide resin for a board | substrate, it is desirable to set it as the following structures.
Thermal conductivity k of the buffer layer: k <0.014 W / cm ° C., preferably, the thermal conductivity k of the buffer layer is 0.01 W / cm ° C. or less. More preferably, the thermal conductivity k of the buffer layer is 0.008 W / cm ° C. or less.
Specific heat Cp of buffer layer: Cp <1.0 J / g · ° C.
Buffer layer thickness: 0.2-1.5 μm
As a material of the buffer layer, a material containing 3 atomic% or more of each component of Zn, S, Si, and O is preferable.
The buffer layer is preferably formed by sputtering.
Note that the crystallization energy beam irradiation in the case of using a plastic substrate can be crystallized by either a continuous beam (CW mode) or a pulse beam (pulse mode).

  In addition, in the manufacturing method of this invention, each structure mentioned above can be combined suitably.

The semiconductor device of the present invention has a configuration that can be manufactured using the above-described method for manufacturing a semiconductor device of the present invention.
That is, an impurity region of an active element such as a source region / drain region / channel region of a transistor or a p-type region / n-type region of a diode is formed in a crystalline semiconductor layer. As the diode, either a PIN diode or the Schottky contact diode described above can be used.
As a crystalline semiconductor layer, an energy beam having a wavelength of 350 nm to 500 nm is applied to an amorphous semiconductor layer having a thickness of 4 nm to 1 μm by using the method for manufacturing a semiconductor device of the present invention. A crystalline semiconductor layer obtained by crystallization by irradiating is used.

In the semiconductor device of the present invention described above, the following configuration can be further provided.
(1) A structure in which the active element is a thin film transistor, the thickness of the amorphous semiconductor layer is in the range of 4 nm to 100 nm, and the impurity regions are the source region and the drain region of the thin film transistor.
(2) Configuration in which the active element is a PIN diode, the thickness of the amorphous semiconductor layer is in the range of 300 nm to 1 μm, and the impurity regions are the p-type region, i-type region, and n-type region of the PIN diode. .
(3) In (2), an amorphous second semiconductor layer is further formed on the crystalline semiconductor layer, and a second PIN diode is formed on the amorphous second semiconductor layer. Configuration.
(4) A structure in which the amorphous semiconductor layer contains one or more elements selected from Si, Ge, and C.
(5) A configuration in which the insulating layer is formed of glass or plastic.
Note that these configurations can be combined as appropriate.

<2. First Embodiment>
Subsequently, specific embodiments of the present invention will be described.
First, as a first embodiment of the present invention, an embodiment of a semiconductor device manufacturing method of the present invention will be described.
In this embodiment, the semiconductor layer formed over the insulating layer is a thick film.

  In this embodiment, after forming a thick amorphous semiconductor layer (such as a silicon layer) directly on the insulating layer or via another layer (such as a conductor layer or an insulating layer), a wavelength of 350 nm is formed on the semiconductor layer. The amorphous semiconductor layer is crystallized by irradiating laser light within a range of ˜500 nm.

  As the insulating layer, an insulating substrate (or insulating material) made of glass or plastic, or an insulating layer (eg, an oxide such as a silicon oxide layer) formed on an arbitrary substrate (insulating substrate, metal plate, semiconductor substrate, etc.). Material layer or nitride layer).

In this embodiment mode, the thickness of the amorphous semiconductor layer is larger than that of a normal semiconductor layer for a thin film transistor, for example, in the range of 300 nm to 1 μm.
As the semiconductor material of the amorphous semiconductor layer, a material containing Si, Ge, C, such as a silicon layer, a SiGe layer, a Ge layer, or a SiC layer is used. Further, if necessary, an n-type impurity (such as phosphorus) or a p-type impurity (such as arsenic) is implanted into the semiconductor layer to enhance conductivity.

As a method for forming the amorphous semiconductor layer, either a sputtering method or a CVD method can be used.
When the sputtering method (RF sputtering method) is used, a thick layer can be formed in a relatively short time.
On the other hand, in order to obtain a semiconductor layer having large crystal grains by crystallization, it is advantageous to form an amorphous semiconductor layer by a CVD method.

Examples of laser light within a wavelength range of 350 nm to 500 nm include ultraviolet light, blue-violet and blue visible light, and laser light such as a semiconductor laser is used.
The laser beam may be either a continuous beam (CW) or a beam emitted in a pulsed manner (pulse beam).

Next, FIG. 1 shows a schematic configuration diagram of a crystallization apparatus used in the present embodiment.
The crystallization apparatus 40 shown in FIG. 1 includes a light source unit 31 and an optical head unit 34.

The light source unit 31 includes a large number of laser diodes 32 arranged in an array.
As the laser diode 32, a semiconductor laser diode that emits a laser beam having a wavelength of 350 nm to 500 nm, for example, a laser beam having a wavelength of 445 nm can be used. For example, the light source unit 31 can be configured by using 48 laser diodes 32 having an output of 500 mW.
Each laser diode 32 of the light source unit 31 is connected to one end of an optical fiber 33 that sends laser light emitted from the laser diode 32 to the optical head unit 34. In the figure, many optical fibers 33 are bundled. The other end of the optical fiber 33 is connected to the optical head unit 34.
The optical head unit 34 includes a beam homogenizer 35, an output monitor 36, and an AF detector 37.
The beam homogenizer 35 performs beam shaping of laser light supplied through the optical fiber 33 and the like. The output monitor 36 detects the output of the laser beam supplied through the optical fiber 33, and automatically controls the output of the laser diode 32 of the light source unit 31 as necessary. The AF detector 37 detects return light reflected by the semiconductor layer to be irradiated and performs autofocus control for moving the objective lens 38 as indicated by an arrow AF.
The objective lens 38 focuses the laser light that has passed through the beam homogenizer 35 to form a beam spot 39 on the irradiation target.

  In this crystallization apparatus 40, a laser beam emitted from a laser diode 32 whose output is controlled is used to convert a beam spot 39 obtained by focusing the laser beam with an objective lens 38 into an amorphous semiconductor layer (for example, a silicon layer). ) To crystallize the semiconductor layer.

Next, a method for crystallization by irradiating an amorphous silicon layer with laser light from the crystallization apparatus 40 of FIG. 1 will be described with reference to FIG.
As shown in FIG. 2, a base layer (buffer layer) 42 is formed on the surface of the glass substrate 41, and an amorphous silicon layer 43 is formed on the base layer (buffer layer) 42.
Then, using the crystallization apparatus 40 shown in FIG. 1, the beam spot is set as a CW beam (continuous beam) 45, and this CW beam 45 is scanned in the left direction indicated by an arrow Scan in FIG. The silicon layer 43 is irradiated.
Thereby, the amorphous silicon layer 43 can be crystallized to form the crystalline silicon layer 44.
In addition, a part of the belt is overlapped, and the scanning is reciprocated to the left and right to irradiate a wide area with a laser beam to crystallize the amorphous silicon layer 43 to form the crystalline silicon layer 44. Can be formed.

(Example)
Here, specifically, an amorphous semiconductor layer was crystallized and the characteristics were examined.

[Test 1]
First, an amorphous silicon layer having a thickness of 500 nm was formed on a glass substrate by RF sputtering using Ar gas as a sputtering discharge inert gas.
Then, the amorphous silicon layer was crystallized using the crystallization apparatus 40 shown in FIG. The wavelength of the light emitted from the laser diode 32 of the crystallization apparatus 40 was 445 nm, the output was 4.7 W, and the scan speed was 500 mm / s.

The cross section of the silicon layer after the crystallization was observed with a TEM (transmission electron microscope).
The obtained TEM image is shown in FIG.
In the case of a thick film having a thickness of 500 nm, a heat flow is generated in the vertical direction during crystallization because there is a temperature gradient in the vertical direction of the film. Thereby, as shown in FIG. 3, crystallization close to a columnar shape occurs.

Furthermore, about the obtained silicon layer, the analysis of the K-spectrum which is the absorptivity by spectroscopic ellipsometry, and the crystal orientation by the X-ray diffraction method were identified.
The K-spectrum is shown in FIG. 4, and the results of the X-ray diffraction method are shown in FIG.
FIG. 4 shows that a clear peak appears and the entire film is sufficiently crystallized.
Further, FIG. 5 clearly shows that the (111) plane peak clearly appears as a sharp peak and is sufficiently crystallized.

According to this embodiment described above, an amorphous semiconductor layer (silicon layer or the like) is irradiated with laser light having a wavelength in the range of 350 nm to 500 nm to crystallize the amorphous semiconductor layer. .
Thereby, since crystallization is performed by irradiation with laser light, crystallization can be performed in a relatively short time. In addition, since laser light with a wavelength in the range of 350 nm to 500 nm is irradiated, a crystalline semiconductor layer having excellent flatness, uniformity, crystallinity, and stability can be obtained.

  Further, according to the present embodiment, since a laser beam having a wavelength in the range of 350 nm to 500 nm is irradiated, a relatively thick semiconductor layer having a thickness of 300 nm to 1 μm, which is difficult to crystallize by excimer laser irradiation, is formed. In contrast, crystallization can be performed with good flatness.

<3. Second Embodiment>
Next, as a second embodiment of the present invention, another embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
In this embodiment, the semiconductor layer formed over the insulating layer is a thin film.

  In this embodiment mode, after a thin amorphous semiconductor layer (such as a silicon layer) is formed on an insulating layer directly or via another layer (such as a conductor layer or an insulating layer), a wavelength is applied to the semiconductor layer. Irradiation with a laser beam within a range of 350 nm to 500 nm is performed to crystallize the amorphous semiconductor layer.

  As the insulating layer, an insulating substrate (or insulating material) made of glass or plastic, or an insulating layer (eg, an oxide such as a silicon oxide layer) formed on an arbitrary substrate (insulating substrate, metal plate, semiconductor substrate, etc.). Material layer or nitride layer).

In this embodiment mode, the thickness of the amorphous semiconductor layer is approximately the same as that of a semiconductor layer for a normal thin film transistor, for example, in the range of 4 nm to 100 nm.
As the semiconductor material of the amorphous semiconductor layer, a material containing Si, Ge, C, such as a silicon layer, a SiGe layer, a Ge layer, or a SiC layer is used. Further, if necessary, an n-type impurity (such as phosphorus) or a p-type impurity (such as arsenic) is implanted into the semiconductor layer to enhance conductivity.

As a method for forming the amorphous semiconductor layer, either a sputtering method or a CVD method can be used.
In particular, when the capacitively coupled plasma CVD method is used, a thin film of an amorphous semiconductor layer having a large area and excellent uniformity can be formed.
When the semiconductor layer is formed using the plasma CVD method, a large amount (about 10 to 20 atomic%) of hydrogen is contained in the semiconductor layer. When excimer laser irradiation is performed in this state, the local heat is suddenly heated, so that hydrogen is instantaneously agglomerated and released, holes are formed in the surface, and the flatness is significantly deteriorated.
Therefore, when crystallization is performed by excimer laser irradiation on an amorphous semiconductor layer formed by a plasma CVD method, a dehydrogenation step (400 to 450 ° C., 1 ° C. in a nitrogen atmosphere) is performed before the crystallization step. It was indispensable to perform (about 2 hours).
On the other hand, in the manufacturing method of the present embodiment, the semiconductor layer is not locally heated because it is crystallized by irradiating laser light within a wavelength range of 350 nm to 500 nm. It is heated relatively gently throughout the thickness of the layer. Thus, even when an amorphous semiconductor layer formed by a plasma CVD method is irradiated with laser light, hydrogen is not released and a dehydrogenation step becomes unnecessary.

As the crystallization apparatus, the same crystallization apparatus as that in the manufacturing method of the first embodiment can be used. For example, the amorphous semiconductor layer can be crystallized by scanning the laser beam as shown in FIG. 2 using the crystallization apparatus 40 shown in FIG.
However, in the case of a thin film, the energy required for crystallization of the entire semiconductor layer is less than in the case of a thick film, so that the amorphous semiconductor layer such as the output of the laser diode 32 of the crystallization device 40 is reduced. The irradiation condition of the energy beam may be different from that of the thick film.

(Example)
[Test 2]
Here, specifically, an amorphous silicon thin film was crystallized and the characteristics were examined.
In addition, as a comparative example, the silicon thin film having the same thickness was crystallized by irradiation with an excimer laser, and the characteristics of the obtained crystalline thin film were compared between the example and the comparative example.

First, an amorphous silicon layer having a thickness of 50 nm was formed on a glass substrate by plasma CVD.
(A p-type impurity, phosphorus is ion-implanted. Ion implantation conditions are a dose of ² × ¹⁰ 15 / cm 2, the energy 5 keV, Fei as _{r p} is the 30nm or less.)
Then, the amorphous silicon layer was crystallized using the crystallization apparatus 40 shown in FIG. The wavelength of the light emitted from the laser diode 32 of the crystallization apparatus 40 was 445 nm, and the scan speed was 500 mm / s. Crystallization was performed by changing the output of the laser diode 32 to 5 W, 6 W, and 8 W, respectively, and samples of the examples were manufactured.

Further, as a comparative example, crystallization was performed by irradiating an excimer laser with a wavelength of 308 nm to an amorphous silicon layer having a thickness of 50 nm. Crystallization was performed by changing the energy density of the excimer laser to 150, 200, 350, 400, and 450 [mJ / cm ² ] to prepare samples of comparative examples.

  Each sample was observed by SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope), and the film obtained using an image (AFM image) observed by AFM (Atomic Force Microscope) The surface condition of was examined.

The image by SEM of each sample of an Example is shown to FIG. 6A-FIG. 6C. 6A is a sample with an output of 5 W, FIG. 6B is a sample with an output of 6 W, and FIG. 6C is a sample with an output of 8 W. In FIGS. 6A to 6C, the laser scanning direction is the vertical direction (the vertical direction in the figure).
When the output is 5 W, the crystal grains are small. When the output is 6 W, the crystal grains are slightly large and have a size of about 50 nm to 300 nm. In the case of an output of 8 W, anisotropic crystals are formed in which crystal grains are continuous in the scanning direction. Thus, it can be seen that the size and state of the crystal grains can be changed by changing the output.

When the crystal grains are small, the mobility is small, but the uniformity is high. Such a silicon layer is suitable for a thin film transistor for driving an organic EL.
Since mobility increases when crystal grains are large or anisotropic crystals are formed, such a silicon layer is suitable for an active element (such as a transistor) that operates at high speed.

Images by TEM of the samples of the examples are shown in FIGS. 7A to 7C. 7A is a sample with an output of 5 W, FIG. 7B is a sample with an output of 6 W, and FIG. 7C is a sample with an output of 8 W. 7A to 7C, the scanning direction of the laser is the vertical direction (the vertical direction in the figure).
7A to 7C, it can be seen that the size and state of the crystal grains can be changed by changing the output.

Images by AFM of each sample of the comparative example are shown in FIGS. 8A to 9E. Samples of Figure 8A is 150 mJ / cm ^2, the sample of FIG. 8B is 200 mJ / cm ^2, the sample of FIG. 8C 350 mJ / cm ^2, Figure 9D sample 400 mJ / cm ^2, Figure 9E is a sample of 450 mJ / cm ² is there.
Further, the surface roughness Rms was measured as the degree of unevenness in the section of lines indicated by AB (vertical direction) and CD (horizontal direction) in each figure. Table 1 shows the surface roughness Rms of each sample of the comparative example.

Images by AFM of the samples of the examples are shown in FIGS. 10A to 10C. 10A is a sample with an output of 5 W, FIG. 10B is a sample with an output of 6 W, and FIG. 10C is a sample with an output of 8 W. In FIGS. 10A to 10C, the laser scanning direction is the vertical direction (the vertical direction in the figure).
Further, surface roughness Rms was measured as the degree of unevenness in the section of the line indicated by AB (vertical direction) and CD (horizontal direction) in each figure. Table 2 shows the surface roughness Rms of each sample of the example.

8A to 9E and the AFM images of the examples of FIGS. 10A to 10C, in either case, the size of the crystal grains can be reduced by changing the laser light irradiation conditions. I understand that it will change.
Among the comparative examples, the crystal grains are the largest at 350 mJ / cm ^{2 in} FIG. 8C.
Comparing the comparative example of FIG. 8C with the example of FIG. 10B, the size of the crystal grains is not so large, and the example of FIG. 10B is slightly larger.
However, when the results of Table 1 and Table 2 are compared, the surface roughness of the comparative example (350 mJ / cm ² ) of FIG. 8C is 14.39 nm and 12.11 nm, while the example of FIG. ) Surface roughness is 5.48 nm and 4.05 nm. In other words, it can be seen that the surface roughness is smaller and the flatness is better in the example in place of the crystal grain size. Similarly, the surface roughness of the other samples of the examples is small instead of the size of the crystal grains.
Therefore, the surface roughness of the crystallized silicon layer is small and flatness when the laser beam is irradiated in the blue visible light region of a slightly longer wavelength range than when the laser beam is irradiated by an excimer laser. It is understood that is superior.

  In the above-described embodiment, the crystal grain size of the polycrystalline silicon layer obtained by crystallization is changed by changing the output of the laser diode, but it is also possible to change the scan speed of the laser beam. Similarly, it is possible to change the crystal grain size and the like of the polycrystalline silicon layer obtained by crystallization.

According to this embodiment described above, an amorphous semiconductor layer (silicon layer or the like) is irradiated with laser light having a wavelength in the range of 350 nm to 500 nm to crystallize the amorphous semiconductor layer. .
Thereby, since crystallization is performed by irradiation with laser light, crystallization can be performed in a relatively short time. In addition, since laser light with a wavelength in the range of 350 nm to 500 nm is irradiated, a crystalline semiconductor layer having excellent flatness, uniformity, crystallinity, and stability can be obtained.

  In addition, according to this embodiment mode, laser light in a wavelength range of 350 nm to 500 nm is irradiated, so that hydrogen in the semiconductor layer is released even when an amorphous semiconductor layer is formed by a plasma CVD method. This eliminates the need for a heat treatment step for dehydrogenation, which is indispensable for excimer laser irradiation.

[Test 3]
In general, in the case of laser annealing, in a silicon film formed by sputtering, Ar atoms that are the sputtering gas are taken into the silicon film, and subsequent rapid heat treatment by a laser beam causes film peeling, so that the irradiation is sufficiently high. Crystallization with energy is difficult.
Therefore, the crystal grains obtained are limited to small particle sizes.
For example, experimental results when crystallization is performed with an excimer laser are described in literature (DY Kim et al, IMID'03 DIGEST, 661, (2003)).
Therefore, although Ar and the sputtering efficiency (film formation rate) do not change so much, the characteristics were compared with the case of using Ar gas with Ne gas having a smaller atomic radius as the sputtering gas.

First, an amorphous silicon layer having a thickness of about 50 nm was formed on a glass substrate by RF sputtering using a silicon target mixed with phosphorus at a high concentration. The resistivity of the silicon target was in the range of 0.0013 to 0.0016 Ωcm.
At this time, several samples were prepared for each of the case where Ar gas was used as the sputtering discharge inert gas and the case where Ne gas was used.
Then, the amorphous silicon layer of each sample was crystallized using the crystallization apparatus 40 shown in FIG. The wavelength of the light emitted from the laser diode 32 of the crystallization apparatus 40 was 445 nm, and the scan speed was 500 mm / s. For each sample, the output of the laser diode 32 was changed within the range of 3W to 6W, and crystallization was performed at each output.

In each case where crystallization was performed while changing the output, the sheet resistance of the silicon layer obtained after crystallization was measured.
As a measurement result, the relationship between the laser output and the sheet resistance is shown in FIG.

The sample using Ar gas could be crystallized without any problems in the output range of 4 W to 4.8 W shown in FIG. However, if the output exceeds 4.8 W, crystallization becomes poor and film peeling occurs. This can be presumed to be because Ar taken in the silicon layer at the time of film formation jumps out by heat at the time of crystallization.
From FIG. 11, in the sample using Ne gas, the sheet resistance is low within a wide range of outputs 4W to 6W. Thereby, laser irradiation is possible to a higher output than when Ar gas is used. Moreover, sheet resistance is low compared with the sample using Ar gas. This effect can be presumed to be due to improved crystallinity. The obtained sheet resistance value was 770Ω / □ when the crystallization output was 5.5 W.

Here, in the case where crystallization is performed on a sample using Ar gas at an output of 4.3 W, and in the case where crystallization is performed on a sample using Ne gas at an output of 5.5 W, N ellipsometry is performed by spectroscopic ellipsometry. And k spectra were analyzed.
The results of the analysis are shown in FIGS. 12A and 12B. FIG. 12A shows the result of the sample using Ar gas, and FIG. 12B shows the result of the sample using Ne gas.
In FIG. 12A and FIG. 12B, comparing the k spectrum particularly around 280 nm, it can be seen that the crystallinity of the film is better when the Ne gas of FIG. 12B is used.

Further, the Raman spectrum of the silicon layer was measured when crystallization of the sample using Ne gas was performed at an output of 4.9 W and at an output of 5.5 W, respectively. The measurement results are shown in FIGS. 13A and 13B. FIG. 13A shows the case of an output of 4.9 W, and FIG. 13B shows the case of an output of 5.5 W.
As can be seen by comparing FIG. 13A and FIG. 13B, when the output is 5.5 W, since the peak is very sharp, it is considered that the crystallinity is very excellent. That is, it is considered that the electrical activation rate of phosphorus in the silicon layer is improved and reflected as a decrease in resistance.

[Test 4]
Next, an amorphous silicon thin film was formed by a CVD method, and crystallization was performed by laser irradiation without performing a dehydrogenation process, and the characteristics were examined.

First, an amorphous silicon layer having a thickness of about 30 nm was formed on a glass substrate by a plasma CVD method through a SiO ₂ layer serving as a buffer layer. Since it is formed by the plasma CVD method, the amorphous silicon layer contains a certain amount of hydrogen.
Thereafter, crystallization was performed using the crystallization apparatus 40 shown in FIG. 1 without performing the dehydrogenation heat step. The wavelength of the light emitted from the laser diode 32 of the crystallization apparatus 40 was set to 445 nm, continuous irradiation (CW mode), and the scan speed was set to 500 mm / s. Then, crystallization was performed by changing the output of the laser diode 32 to 4.5 W and 6 W, respectively.

Although there was no remarkable effect under the condition of the output of 4.5 W, the crystallization was realized very stably when the laser was irradiated under the condition of the output of 6 W.
The crystallized silicon layer crystallized at an output of 6 W was analyzed by spectroscopic ellipsometry and observed by a TEM (transmission electron microscope).
The analysis result (k spectrum) of a spectroscopic ellipsometry is shown in FIG. 14, and the image by TEM is shown in FIG.
In FIG. 14, the k spectrum of single crystal silicon (c-Si) is compared with the case where crystallization is performed at an output of 6 W.

From the analysis result of the absorptance spectrum shown in FIG. 14, when crystallization is performed at an output of 6 W, the peak near 280 nm is sharp, and good crystallinity close to the spectrum of single crystal silicon is obtained. Conceivable.
According to the TEM image shown in FIG. 15, crystal grains having a very large grain size of 0.3 to 0.5 μm are obtained, and the crystallinity in the grains is also good, so that the dehydrogenation step is not performed. It was found that large crystal grains can be obtained stably.

Further, the concentration distribution of each element (silicon, hydrogen, oxygen) from the surface of the crystallized silicon layer crystallized at an output of 6 W to a depth of around 46 nm was measured by SIMS (secondary ion mass spectrometry). . The measurement results are shown in FIG.
From FIG. 16, in the silicon layer portion (up to a depth of about 30 nm), the concentration of hydrogen is small except for the very surface, and the concentration is one order of magnitude lower than that of the lower SiO ₂ layer. That is, it can be seen that hydrogen is removed by laser irradiation without performing the dehydrogenation step.

[Test 5]
Next, an amorphous silicon thin film was formed on a plastic substrate through an underlying buffer layer, crystallized, and the characteristics were examined.
As a material for the plastic substrate, polyimide resin (thermal decomposition start temperature is about 500 ° C.) was used.

First, a ZnS-SiO ₂ (about 0.005 W / cm ° C.) layer having a low thermal conductivity was formed to a thickness of about 0.3 μm as a buffer layer on a plastic substrate made of polyimide resin by RF sputtering. . At this time, a material containing Zn, S, Si, and O as components was used for the sputtering target.
Subsequently, an amorphous silicon layer having a thickness of 50 nm was formed on the buffer layer continuously by sputtering in the same chamber.
Then, the amorphous silicon layer was crystallized using the crystallization apparatus 40 shown in FIG. The wavelength of the light emitted from the laser diode 32 of the crystallization device 40 was set to 445 nm, continuous irradiation (CW mode), the scan speed was set to 500 mm / s, and the output of the laser diode 32 was set to about 1.1 W.

After the laser irradiation, the refractive index of the silicon layer changed and a color change occurred.
This color change was measured by a spectroscopic ellipsometry method (spectral ellipsometer ES-4G manufactured by SOPRA) and analyzed. As a result, the spectra before and after laser irradiation are compared and shown in FIGS. 17A and 17B. FIG. 17A shows the refractive index (N) before and after irradiation, and FIG. 17B shows the absorptance (k) before and after irradiation.
From FIG. 17B, the peak at about 280 nm of the spectrum of the absorptance (k) is stronger after the irradiation than before the irradiation. As a result, the crystal grains are limited, but it is considered that crystallization has occurred.

The above-described effects are effective even in the pulse mode with less damage to the base.
Therefore, instead of continuous irradiation (CW mode), the pulse width is 300 nsec, the top hat beam output is 5.4 W, and the repetition frequency is 1 MHz. went.
As a result, crystallization similar to the case of continuous irradiation was possible.
Therefore, it can be seen that crystallization can be performed without any problem even in the pulse mode.

<4. Third Embodiment>
Next, as a third embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a semiconductor device is shown in FIG.
In this embodiment mode, a thin film transistor and a lateral PIN diode are formed in a crystallized thin film semiconductor layer.

As shown in FIG. 18, a polycrystalline silicon thin film 2, 3 is formed on an insulating substrate 1 such as a glass substrate or a plastic substrate to constitute a semiconductor device 10.
The left polycrystalline silicon thin film 2 is formed with n ⁺ source / drain regions 2A, 2C and p ⁻ channel region 2B of the thin film transistor, and the right polycrystalline silicon thin film 3 has a lateral PIN diode. P ⁺ region 3A, i region 3B, and n ⁺ region 3C are formed. The p ⁺ region 3A, the i region 3B, and the n ⁺ region 3C of the lateral PIN diode are formed side by side in the horizontal direction (lateral direction).
An insulating film 4 is formed on the polycrystalline silicon thin films 2 and 3. This insulating film 4 also includes a gate insulating film under the gate electrode 6 of the thin film transistor.

In the thin film transistor, a gate electrode 6 made of metal is formed on a channel region 2B of the polycrystalline silicon thin film 2 through a gate insulating film made of an insulating film 4.
Further, in the source / drain regions 2A and 2C, an electrode layer 5 made of metal is formed so as to fill the contact hole formed in the insulating film 4.
With these structures, a top-gate thin film transistor is formed.

In the lateral PIN diode, an electrode layer 7 made of metal is formed on and in contact with the p ⁺ region 3A and the n ⁺ region 3C of the polycrystalline silicon thin film 3, respectively.

The polycrystalline silicon thin film 2 of the thin film transistor and the polycrystalline silicon thin film 3 of the lateral PIN diode are both formed on the amorphous silicon thin film formed on the insulating substrate 1 by using the semiconductor device manufacturing method of the present invention. On the other hand, a polycrystalline silicon thin film obtained by crystallization by irradiating a laser beam is used.
Then, by patterning and separating the polycrystalline silicon thin film obtained by crystallization, the polycrystalline silicon thin film 2 of the thin film transistor and the polycrystalline silicon thin film 3 of the lateral PIN diode can be formed simultaneously. it can.
The source / drain regions 2A and 2C of the thin film transistor and the p ⁺ region 3A and n ⁺ region 3C of the PIN diode are formed before or after the step of separating into the respective polycrystalline silicon thin films 2 and 3 by this patterning, for example, polycrystalline silicon. The thin film can be formed by ion implantation of p-type impurities or n-type impurities.

  According to the configuration of the semiconductor device 10 of the present embodiment described above, the polycrystalline silicon thin film 2 of the thin film transistor and the polycrystalline silicon thin film 3 of the lateral PIN diode are formed using the method for manufacturing a semiconductor device of the present invention. By doing so, a polycrystalline silicon thin film excellent in flatness, uniformity and crystallinity can be used as the polycrystalline silicon thin films 2 and 3. Accordingly, it is possible to configure the semiconductor device 10 having a thin film transistor and a PIN diode each having good characteristics (for example, high mobility and high speed operation, high light conversion efficiency, etc.).

In the above-described embodiment, the top gate type thin film transistor is included.
In the semiconductor device of the present invention, a bottom-gate thin film transistor may be formed over the insulating layer.
When forming a bottom gate thin film transistor, an electrode layer of a gate electrode or a wiring layer connected to the electrode layer is formed on an insulating layer such as an insulating substrate, and the electrode layer or the wiring layer is interposed therebetween. Then, an amorphous silicon thin film is formed. Further, this amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film. Then, in the polycrystalline silicon thin film, a channel region is formed in a portion on the gate electrode, and a source / drain region is formed outside the channel region.

<5. Fourth Embodiment>
Next, FIG. 19 shows a schematic configuration diagram (cross-sectional view) of a semiconductor device as a fourth embodiment of the present invention.
This embodiment is a case where a vertical PIN diode is formed in a crystallized thick semiconductor layer.

As shown in FIG. 19, a vertical PIN diode is formed using a polycrystalline silicon layer 16 formed on an insulating substrate 11 such as a glass substrate or a plastic substrate, so that a semiconductor device 20 is configured.
In the semiconductor device 20, transistors and other circuits are formed in other parts (not shown) separately from the vertical PIN diode.

A vertical PIN diode has a structure in which a polycrystalline silicon layer 16 is formed via an electrode layer 12 formed on an insulating substrate 11, and a transparent electrode layer 17 is formed on the polycrystalline silicon layer 16. Has been. The light L incident from above the transparent electrode layer 17 can be received and detected by the PIN diode.
In the polycrystalline silicon layer 16, an n ⁺ region 13, an i region 14 and a p ⁺ region 15 of a vertical PIN diode are stacked in this order from the lower layer.
Note that the n ⁺ region 13 and the p ⁺ region 15 may be stacked so that the n ⁺ region 13 is in an upper layer, upside down from FIG.

For the electrode layer 12, a conductive material of a metal compound such as a metal, an alloy, or a metal nitride can be used.
For the transparent electrode layer 17, a transparent conductive material such as ITO (indium tin oxide) can be used.

  The vertical PIN diode of the semiconductor device 20 of the present embodiment can be used as a light receiving sensor and can also be used as a solar cell.

The polycrystalline silicon layer 16 of the vertical PIN diode is crystallized by irradiating the amorphous silicon layer formed on the insulating substrate 11 with laser light using the method for manufacturing a semiconductor device of the present invention. A polycrystalline silicon layer obtained by performing is used.
By using the method for manufacturing a semiconductor device of the present invention to form the polycrystalline silicon layer 16, a polycrystalline silicon layer having excellent flatness, uniformity and crystallinity is used as the polycrystalline silicon layer 16. Can do. As a result, a PIN diode with high light conversion efficiency can be configured.

  According to the configuration of the semiconductor device of the present embodiment described above, the polycrystalline silicon layer 16 of the vertical PIN diode is formed by using the method for manufacturing a semiconductor device of the present invention. A polycrystalline silicon layer excellent in flatness, uniformity, and crystallinity can be used. As a result, the semiconductor device 20 having a PIN diode with high light conversion efficiency can be configured.

<6. Fifth embodiment>
Next, a schematic configuration diagram (cross-sectional view) of a semiconductor device is shown in FIG. 20 as a fifth embodiment of the present invention.
This embodiment has a tandem structure in which two vertical PIN diodes are stacked one above the other.

As shown in FIG. 20, a lower first vertical PIN diode is formed using a polycrystalline silicon layer 16 formed on an insulating substrate 11 such as a glass substrate or a plastic substrate. The configuration of the first vertical PIN diode is the same as that of the vertical PIN diode of the semiconductor device 20 of the fourth embodiment shown in FIG.
Further, an amorphous silicon layer 24 in which a second vertical PIN diode is formed is stacked on and in contact with the polycrystalline silicon layer 16 in which the first vertical PIN diode is formed. . On the amorphous silicon layer 24, the transparent electrode layer 17 similar to the semiconductor device 20 of the fourth embodiment shown in FIG. 19 is formed, and the semiconductor device 30 is configured.
The second vertical PIN diode is configured by forming an n ⁺ region 21, an i region 22, and a p ⁺ region 23 in the amorphous silicon layer 24 from the lower layer.
Note that the n ⁺ regions 13 and 21 and the p ⁺ regions 15 and 23 may be stacked so that the n ⁺ regions 13 and 21 are in the upper layer, upside down from FIG.

  Similar to the polycrystalline silicon layer 16 of the semiconductor device 20 of the fourth embodiment, the polycrystalline silicon layer 16 is obtained by crystallizing an amorphous silicon layer using the semiconductor device manufacturing method of the present invention. A polycrystalline silicon layer is used. As a result, a polycrystalline silicon layer having excellent flatness, uniformity, and crystallinity can be used as the polycrystalline silicon layer 16, so that a PIN diode with high light conversion efficiency can be configured.

  As the amorphous silicon layer 24, a hydrogenated amorphous silicon layer (a-Si: H) that has been conventionally used in solar cells or the like can be used.

For example, the thickness of the polycrystalline silicon layer 16 is about 1 μm, the thickness of the amorphous silicon layer 24 is about 1 μm, and the total thickness is about 2 μm.
Note that the thickness of each of the silicon layers 16 and 24 may be made thinner than about 1 μm. The thickness of the silicon layers 16 and 24 may be set to a thickness within the range of 0.5 μm to 1.0 μm, for example.
By reducing the thickness of the silicon layers 16 and 24, the amount of silicon used is reduced, so that the material cost can be reduced.

Here, the sunlight spectrum and the absorption spectra of amorphous silicon and polycrystalline silicon are shown in FIG.
As shown in FIG. 21, amorphous silicon (a-Si) has an absorption spectrum peak around 550 nm, and polycrystalline silicon (poly-Si) has an absorption spectrum peak around 750 nm. (A-Si) and polycrystalline silicon (poly-Si) have different absorption spectra (wavelength bands).
Therefore, by using amorphous silicon and polycrystalline silicon together, not only the open circuit voltage (Voc) is increased as a series effect, but also the spectral density distribution of the spectrum of sunlight as shown by the thin line in the figure. A close spectral density distribution is obtained.
From this, as shown in FIG. 20, the amorphous silicon layer 24 is laminated on the polycrystalline silicon layer 16, and the vertical PIN diode is formed on each of the silicon layers 16 and 24. Can be effectively absorbed over a wide wavelength band.

Further, as shown in FIG. 20, prediction calculation is performed for various characteristics of the configuration of the present embodiment in which the amorphous silicon layer 24 is stacked on the polycrystalline silicon layer 16 obtained by crystallization. Went. The thicknesses of the polycrystalline silicon layer 16 and the amorphous silicon layer 24 were 1 μm.
As a result of the calculation, the short-circuit current density Jsc = 23 mA, the open circuit voltage Voc = 1.1 V, and the conversion efficiency = 18%.

As a tandem solar cell, a hydrogenated amorphous silicon layer is stacked on a micropolysilicon layer (polycrystalline silicon layer) formed by a deposition method, and the total thickness of the silicon layer is 3 μm. A proposed configuration has been proposed.
In this proposed configuration, the conversion efficiency is 13 to 14%.
That is, in the configuration of the present embodiment, it can be seen from the above-described calculation results that even higher conversion efficiency can be obtained by this proposed configuration.

The semiconductor device 30 of the present embodiment can be manufactured, for example, as described below.
First, the electrode layer 12 is formed on the insulating substrate 11. As a material of the electrode layer 12, a conductive material such as a metal, an alloy, or a metal compound can be used. The electrode layer 12 is patterned into a predetermined plane pattern after forming the layer.
Next, a first amorphous silicon layer is formed on the electrode layer 12.
Then, after forming the first amorphous silicon layer, the first amorphous silicon layer is crystallized to form the polycrystalline silicon layer 16 by using the method for manufacturing a semiconductor device of the present invention.
Next, an n-type impurity is implanted into the polycrystalline silicon layer 16 to form an n ⁺ region 13, and a p-type impurity is implanted to form a p ⁺ region 15. The n ⁺ region 13 and the p ⁺ region 15 may be formed in either order.
Thereafter, a hydrogenated amorphous silicon layer is formed as the (second) amorphous silicon layer 24 on the polycrystalline silicon layer 16 by, eg, plasma CVD.
Thereafter, an n-type impurity is implanted into the (second) amorphous silicon layer 24 to form an n ⁺ region 21, and a p-type impurity is implanted to form a p ⁺ region 23. The n ⁺ region 21 and the p ⁺ region 23 may be formed in either order.
Further, the transparent electrode layer 17 is formed on the amorphous silicon layer 24.
In this way, the semiconductor device 30 shown in FIG. 20 can be manufactured.

  According to the configuration of the semiconductor device of the present embodiment described above, the polycrystalline silicon layer 16 of the vertical PIN diode is formed by using the method for manufacturing a semiconductor device of the present invention. A polycrystalline silicon layer excellent in flatness, uniformity, and crystallinity can be used. Thereby, the semiconductor device 30 having the PIN diode with high light conversion efficiency can be configured.

  Since the amorphous silicon layer 24 having the second vertical PIN diode is laminated on the polycrystalline silicon layer 16 having the first vertical PIN diode, the tandem structure has been proposed. Similar to the tandem structure, it can detect and detect light over a wide wavelength band of sunlight.

  Further, according to the present embodiment, the amount of silicon used can be significantly reduced as compared with a configuration using a thick bulk silicon layer as in a conventional solar cell or the like. Thereby, material cost can be reduced significantly.

  The present invention is not limited to the above-described embodiments and examples, and various other configurations can be taken without departing from the gist of the present invention.

  1,11 Insulating substrate, 2,3 Polycrystalline silicon thin film, 4 Insulating film, 5,7 electrode layer, 6 Gate electrode, 10, 20, 30 Semiconductor device, 12 Electrode layer, 16 Polycrystalline silicon layer, 17 Transparent electrode layer 24 amorphous silicon layer, 31 light source unit, 32 laser diode, 33 optical fiber, 34 optical head unit, 35 beam homogenizer, 36 output monitor, 37 AF detector, 38 objective lens, 39 beam spot, 40 crystallizer, 41 glass substrate, 42 base layer (buffer layer), 43 amorphous silicon layer, 44 crystalline silicon layer

Claims (16)

Forming an amorphous semiconductor layer having a thickness of 4 nm to 1 μm on the insulating layer;
A method for manufacturing a semiconductor device, comprising: irradiating the semiconductor layer with an energy beam having a wavelength in a range of 350 nm to 500 nm to crystallize the semiconductor layer.   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer includes one or more elements selected from Si, Ge, and C.   The method for manufacturing a semiconductor device according to claim 1, wherein glass or plastic is used as the insulating layer.   4. The method according to claim 1, wherein the step of forming the amorphous semiconductor layer is performed by a sputtering method using Ne gas or a mixed gas containing Ne gas as a sputtering discharge inert gas. 5. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   4. The step of crystallizing the semiconductor layer without performing a heat treatment step for dehydrogenation after performing the step of forming the amorphous semiconductor layer by plasma CVD. The method for manufacturing a semiconductor device according to any one of the above.   6. The manufacturing of a semiconductor device according to claim 1, further comprising a step of introducing an impurity region of an active element into the semiconductor layer before or after the step of crystallizing the semiconductor layer. Method.   The method for manufacturing a semiconductor device according to claim 3, wherein the insulating layer is formed of plastic, and at least one selected from a polyimide resin, a polyamideimide resin, and polysilsesquioxane is used as the plastic.   A buffer layer made of a material having a thickness of 0.2 to 1.5 μm and containing 3 atomic% or more of each of Zn, S, Si, and O is formed on the insulating layer, and then the buffer layer The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor layer is formed thereon. A crystalline semiconductor layer obtained by crystallization by irradiating an amorphous semiconductor layer having a thickness of 4 nm to 1 μm with an energy beam having a wavelength in the range of 350 nm to 500 nm;
And an active element including an impurity region formed in the crystalline semiconductor layer.   The semiconductor according to claim 9, wherein the active element is a thin film transistor, a thickness of the amorphous semiconductor layer is in a range of 4 nm to 100 nm, and the impurity regions are a source region and a drain region of the thin film transistor. apparatus.   The active element is a PIN diode, the thickness of the amorphous semiconductor layer is in the range of 300 nm to 1 μm, and the impurity regions are the p-type region, the i-type region, and the n-type region of the PIN diode. The semiconductor device according to claim 9.   The amorphous second semiconductor layer is formed on the crystalline semiconductor layer, and a second PIN diode is formed on the amorphous second semiconductor layer. Semiconductor device.   The semiconductor device according to claim 9, wherein the crystalline semiconductor layer contains one or more elements selected from Si, Ge, and C.   The semiconductor device according to claim 9, wherein an insulating layer is provided below the semiconductor layer, and the insulating layer is made of glass or plastic.   The semiconductor device according to claim 14, wherein the insulating layer is made of plastic, and at least one selected from a polyimide resin, a polyamideimide resin, and polysilsesquioxane is used as the plastic.   A buffer layer made of a material having a thickness of 0.2 to 1.5 μm and containing each of Zn, S, Si, and O components of 3 atomic% or more is provided between the insulating layer and the semiconductor layer. The semiconductor device according to claim 15.