JP2012060651A - Multiple lane transmission method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform multiple lane transmission even when BER is in poor conditions.SOLUTION: The present invention improves error resistance, in a transmission system for distributing a single signal to a plurality of lanes and coupling them in a transmitting/receiving section, by using any one or more of: addition of an error correcting code for a bit stream to be used for lane identification and skew detection in distribution means 303, and error correction using the error correcting code in coupling means 401; bit pattern verification using bits less than those specified by OTN recommendation in the bit stream to be used for the lane identification and the skew detection in the coupling means 401; and bit error allowance for the bit stream to be used for the lane identification and the skew detection in the coupling means 401.

Description

  The present invention relates to a multilane transmission method and system, and more particularly, to a multilane transmission method and system for transmitting a single signal through a plurality of lanes.

  Due to the rapid increase in Internet traffic, there is a need to increase the capacity of backbone networks. The optical transmission systems that support backbone networks have so far achieved higher capacities by increasing the bit rate and wavelength multiplexing technology. Specifically, the bit rate is increased to 2.5 Gb / s, 10 Gb / s, and 40 Gb / s, and these signals are further wavelength-multiplexed, for example, 10 Gb / s × 80 wavelengths = 800 Gb / s, 40 Gb. An optical transmission system having a large capacity of / s × 40 wavelengths = 1.6 Tb / s has been realized. Furthermore, it is considered that a transmission system exceeding 100 Gb / s per wavelength will be required in the future due to the appearance of 100 Gb / s class client signals such as 100 G Ethernet (registered trademark).

  In order to realize a transmission system exceeding 100 Gb / s per wavelength, there are technical difficulties due to its high-speed operation. For example, in conventional high-speed modulation schemes such as NRZ and RZ, operation exceeding 100 Gb / s is difficult and transmission signal deterioration becomes large. Therefore, not only light intensity but also phase and the like are used. Research and development of more advanced modulation systems is progressing.

Specifically, optical / electronic devices using multi-level modulation technology such as DQPSK (Differential Quadrature Phase Shift Keying) modulation method and DP-QPSK (Dual Polarization-Quadrature Phase Shift Keying) modulation method, polarization multiplexing technology, etc. Reducing the operating speed required for the system has been studied. When such a modulation method is used, it can be seen that a single signal is transmitted in a plurality of physical lanes within one wavelength. For example, in the case of 112 Gb / s DP-QPSK,
(1) X polarization I (in-phase) channel;
(2) X polarization Q (quadrature-phase) channel;
(3) Y polarization I channel;
(4) Y polarization Q channel;
It can be seen that four 28 Gb / s physical lanes are transmitted at one wavelength.

An example of such a transmission system is shown in FIG. In the transmission system shown in the figure, a transmission device 10 on the transmission side and a transmission device 20 on the reception side are connected by an optical fiber 30, and the transmission device 10 on the transmission side includes a plurality of transmission units 11 _{1 to} 11 _N The wavelength division unit 12 multiplexes transmission signals from the transmission units 11 _{1 to} 11 _N. The transmission device 20 on the reception side includes a wavelength separation unit 21 that separates transmission signals (wavelengths) input via the optical fiber 30 and a plurality of reception units 22 _{1 to} 22 _N. Each transmission unit 11 includes a framer unit 111, an FEC encoding unit 112, and a distribution unit 113. Each reception unit 22 includes a combination unit 221, an FEC decoding unit 222, and a framer unit 223. Signals are transmitted in a plurality of lanes between the coupling units 221.

  In this way, when a single signal is transmitted in multiple lanes, the distribution unit 113 of the transmission unit 11 needs to distribute the single signal to a plurality of signals, and the coupling unit 221 of the reception unit 22 has signals of multiple lanes. Need to be processed to combine them into a single signal. At that time, a skew occurs between the lanes on the receiving side due to a difference in transmission delay of each lane. In addition, there is a possibility that the lanes may be changed due to the rotation of the polarization. This is shown in FIG. As a result, the coupling unit 221 on the reception side needs a lane identification function and a skew detection function for a plurality of lanes.

  As a technology for realizing the lane identification function and the skew detection function, ITU-T Recommendation G. 709 (OTN interface) A method of transmitting OTU3 and OTU4 signals defined in Annex C of Amendment 3 using 40G Ethernet and 100G Ethernet modules (these Ethernet modules are multi-lane transmission) can be used. This is based on the head area (FAS: frame alignment signal) of the OTU frame shown in FIG. 31, and the OTU frame is divided into blocks of 16 bytes as shown in FIG. Multi-lane transmission is possible by distributing these blocks to logical lanes. As shown in FIG. 33, in block distribution to a plurality of lanes, FAS appears in each logical lane by changing the distribution start lane for each frame. The overhead actually used for lane identification and skew detection is shown in FIG. Each channel recognizes the start position of the frame by checking FAS OH bytes 3 to 5 in which a fixed bit pattern is stored. Further, 240 numbers from 0 to 239 are assigned in order to the FAS OH byte 6 and distributed to each logical lane by the distribution unit 113 on the transmission side.

For example,
-FAS OH byte 6 = "0" in logical lane 0;
-FAS OH byte 6 = "1" in logical lane 1;
-FAS OH byte 6 = "2" in logical lane 2;
・
・
-FAS OH byte 6 = "19" in logical lane 19;
Next, return to logical lane 0 again-FAS OH byte 6 = "20" in logical lane 0;
-FAS OH byte 6 = "21" in logical lane 1;
-FAS OH byte 6 = "22" in logical lane 2;
・
・
-FAS OH byte 6 = "39" in logical lane 19;
Grant as follows. If a number is assigned up to 239, then it returns to 0 again.

  On the receiving side, the remainder obtained by dividing the value of FAS OH byte 6 received for each logical lane by the number of logical lanes 20 is the number for identifying each logical lane.

  Since the number of numbers to be assigned is 240 which is a multiple of the number of logical lanes 20 (0 to 239 as the number to be assigned), in the above example, for example, logical lane 0 always has a remainder 0 and logical lane 1 has a remainder. It is always 1, etc., and can be distinguished from other logical lanes. In the above description, it is possible to identify the frame head position and logical lane, but it is possible to detect skew by combining the FAS OH byte 6 and MFAS values and comparing with other logical lanes. . The combination of FAS OH byte 6 and MFAS values is used to expand the skew detection range.

  The method described above is specified for use in short-distance transmission of OTU frames (OTU3 or OTU4) using 40GbE or 100GbE modules, but OTU3 or OTU4 multilane transmission without using Ethernet modules. It is conceivable to divert it.

"Interfaces for the Optical Transport Network (OTN)", March 2003, ITU-T Recommendation G.709 / Y.1331 "Interfaces for the optical transport network (OTN) Amendment 3", April 2009, ITU-T Recommendation G.709 / Y.1331 Amendment 3 "Characters of optical transport network hierarchy equipment functional blocks", December 2006, ITU-T Recommendation G.798

  However, some problems arise when trying to realize multi-lane transmission exceeding 100 Gb / s using the above G.709 Amendment 3, Annex C.

  First of all, in the reception of transmission signals exceeding 100 Gb / s, we are going to shift from the conventional simple direct detection method to a method using a digital signal processing technique such as a digital coherent reception method. This method has an excellent feature such that it is possible to restore a signal that has been transmitted and significantly deteriorated by digital signal processing.

However, since digital signal processing is performed after being transmitted and combined through a plurality of physical lanes, a signal with a low code error rate (BER) before digital signal processing is performed at the combining unit ( For example, BER = 10 ⁻² ) is received. Referring to FIG. 29, in the digital coherent reception method, the digital signal processing is performed immediately before or after the FEC decoding unit 222 and does not come before the combining unit. Therefore, the poor BER before digital signal processing and error correction is performed. The combining unit 221 receives a signal having Even in such a poor BER, it is necessary to implement lane identification and skew detection without delay. However, the method specified in G.709 Amendment 3, Annex C uses OTU3 and OTU4 signals using Ethernet modules. Therefore, the operation in a situation where the BER is inferior is not considered.

  The method defined in G.709 Amendment 3, Annex C is such that when a 112G OTU4 signal is transmitted by a 100G Ethernet module, 20 logical lanes are used. When a signal of 20 logical lanes is transmitted as a transmission signal composed of 4 physical lanes, 4 signals are generated by bit-multiplexing (5: 1) the 5 logical lanes, and each signal is transmitted in each physical lane. The receiving side first separates the received signals of the four physical lanes into bits (1: 5) to restore 20 logical lanes, and then performs lane identification and skew detection on the 20 logical lane signals. At this time, since the error tolerance is low, normal operation cannot be performed in a situation where the BER is poor.

  Here, a numerical calculation result indicating characteristics of the operation in a situation where the BER is inferior is shown. The operation of the coupling unit in multilane transmission can be roughly divided into two. One is “frame synchronization” for finding a FAS as a data delimiter in each logical lane, and the other is “logical lane identification” for identifying which logical lane is the self lane among a plurality of logical lanes. It is. FIG. 35 shows state transitions defined by ITU-T for frame synchronization and logical lane identification. For frame synchronization, two states, IF (In-frame) state and OOF (Out-of-frame) state, are defined. If 4 bytes of FAS 6 bytes are detected in 2 frames in the OOF state, the IF state is set. Transition. On the other hand, in the IF state, the third to fifth bytes of the FAS are confirmed every frame, and if the bit pattern does not match for five consecutive frames, the state transitions to OOF. For logical lane identification, two states, an OLA (Out-of-lane-alignment) state and an ILA (In-lane-alignment) state are defined, and if a consistent lane identification is possible in the OLA state, the ILA state If a consistent lane identification is not possible in the ILA state, the state transits to the OLA state. When all logical lanes are synchronized in frame and logical lane identification is possible, it is possible to detect how much each logical lane is shifted in time from other logical lanes, that is, skew detection.

FIG. 36 shows the frame synchronization characteristics. The horizontal axis represents the code error rate of the signal input to the combining unit, and the vertical axis represents time (number of frames). Further, the number of rear protection steps is changed as a parameter in the range of 2 to 5. Note that the backward protection stage number M means transition to the frame synchronization state when the frame synchronization pattern matching is detected M times as a result of the frame synchronization pattern matching in the frame synchronization loss state. It is desirable for the frame synchronization to transition to the frame synchronization state as soon as possible. In this figure, looking at the characteristics in the case of 2 backward protection levels defined in OTN, for example, when BER = 10 ⁻³ , the number of frames required for establishing frame synchronization is almost the same 2 as the number of backward protection levels. When BER = 3 × 10 ⁻² , approximately 10 frames are required, and when BER = 5 × 10 ⁻² , approximately 30 frames of synchronization establishment time are required. FIG. 37 shows the time until the frame synchronization is lost in the frame synchronization state. The horizontal axis represents the code error rate of the signal input to the combining unit, and the vertical axis represents time (number of frames). Further, the number of forward protection steps is changed as a parameter in the range of 1, 3, 5,. Note that the forward protection stage number N means that the frame synchronization state transitions to the out-of-frame synchronization state when N-time consecutive mismatches are detected as a result of the frame synchronization pattern matching. Since it is desirable that the characteristics shown in FIG. 37 be maintained in a frame synchronization state as much as possible, it can be said that the larger the time (number of frames) on the vertical axis, the better the characteristics. Looking at the characteristics of the number of forward protection stages 5 defined in the standard, for example, when BER = 10 ⁻³ , synchronization is lost at about 1 × 10 ⁸ frames, and when BER = 10 ⁻² , synchronization is lost at about 2000 frames. . In the case of 20 logical lanes, the frame period of each logical lane is approximately 20 microseconds, so the above frame numbers correspond to 30 minutes and 40 milliseconds, respectively, and frame synchronization is lost in a very short time. End up.

Next, lane identification characteristics are shown. FIG. 38 shows the time until lane identification is established in the case of 20 logical lanes used in OTU4 transmission. FIG. 39 shows the time until the lane identification is removed in the case of 20 logical lanes. It is desirable that the lane identification is quickly established and the lane identification is rarely missed. In this numerical calculation, the number of protection steps is also changed as a parameter in lane identification. The standard corresponds to the case where the number of front and rear protection stages is one. The number of frames required for establishing characteristics Reading the lane identification of cases take more than 100 frames when approximately 20-30 frames, the BER = 2 × ^{10 -2} when the BER = ^{10 -2.} On the other hand, when BER = 10 ⁻³ , lane identification is lost in several frames. In the case where the BER is good (for example, BER = 10 ⁻¹² ), in the situation where the BER is inferior, considering that the lane identification is established in almost one frame, and once the lane identification is established, it is hardly deviated. Establishing the lane identification takes much more time, and even if the lane identification is established, the lane identification failure occurs instantaneously, and thus it cannot be said that the characteristics can withstand practical use.

  Note that “physical lane” and “logical lane” will be supplemented. A physical lane indicates a lane determined by a hardware configuration and a transmission method, and a logical lane indicates a lane used for skew detection and lane identification. For example, in transmission using a 100 GbE module of an OTU4 signal specified in G.709 Amendment 3, Annex C, the number of physical lanes varies depending on the 100 GbE module used, but 10 physical lanes and 4 physical lanes are possible. The number of logical lanes is 20.

  Second, when transmission exceeding 100 Gb / s is performed, the influence of various degradation factors in transmission (for example, chromatic dispersion, polarization mode dispersion, etc.) on the transmission signal is 10 Gb / s or 40 Gb / s. Very large compared to transmission. Even in such a situation, it is conceivable to use an error correction code (FEC) having a higher error correction capability in order to keep the transmission distance equal to the conventional one. The redundancy of standard FEC specified in G.709 is 6.7%, and the OTU frame structure is determined based on this redundancy. Also, multi-channel transmission defined by G.709 Amendment 3 and Annex C is defined on the premise of a frame structure based on the redundancy as shown in FIG. 32 and FIG.

  Therefore, for example, when using a non-standard redundancy FEC such as 20% or 30%, the OTU frame structure is different from the standard. Therefore, the method specified in G.709 Amendment 3, Annex C is used. It cannot be applied as it is.

The present invention has been made in view of the above points, and an error that enables normal lane identification and skew detection even in an area where the BER is inferior, such as 10 ⁻² , assumed when using digital coherent reception technology. An object of the present invention is to provide a multilane transmission method and system that enable multi-lane transmission with high tolerance, and further enable transmission of signals using FEC with a redundancy other than G.709 standard in multiple lanes. .

The present invention (Claim 1) is a multi-lane transmission system having a transmission side apparatus for transmitting a single signal using an OTU frame (OTUk or OTUkV) by a plurality of physical lanes and a reception side apparatus for combining received frames. A multilane transmission method in
Multilane transmission system
In the sending device:
An error correction code is added to the bit string used for frame synchronization or the bit string used for lane identification, or both using an overhead area,
In the receiving device:
An error correction step is performed in which error correction is performed on the bit string used for frame synchronization in the OTU frame and / or the bit string used for lane identification using the error correction code added by the transmission side apparatus.

Further, the present invention (Claim 2) is a transmission-side apparatus,
When the redundancy of the error correction code is other than the standard redundancy of 6.7%, a value obtained by multiplying the number of logical lanes and the least common multiple of 4 by 4, ie, “LCM (number of logical lanes, 4) × 4” ”Decrease or increase the number of columns in the OTU frame per column,
The 16 bytes of the frame are distributed as a block to a plurality of logical lanes, and the logical lanes are allocated to the physical lanes for transmission.

  In the present invention (claim 3), the number of physical lanes is four and the number of logical lanes is four.

  FIG. 1 is a principle configuration diagram of the present invention.

According to the present invention (Claim 4), there is provided a multi-side including a transmitting side device that transmits a single signal using an OTU frame (OTUk or OTUkV) through a plurality of physical lanes, and a receiving side device that combines received frames. A lane transmission system,
An error correction encoding means 311 for adding an error correction code to the transmission side apparatus using an overhead region for a bit string used for frame synchronization or a bit string used for lane identification, or both;
An error correction decoding means 412 for performing error correction on the receiving side apparatus using the error correction code added by the transmitting side apparatus to the bit string used for frame synchronization in the OTU frame and / or the bit string used for lane identification; Are provided.

Further, the present invention (Claim 5) is a transmission-side apparatus,
When the redundancy of the error correction code is other than the standard redundancy of 6.7%, a value obtained by multiplying the number of logical lanes and the least common multiple of 4 by 4, ie, “LCM (number of logical lanes, 4) × 4” A frame generation unit 301 that decreases or increases the number of columns of the OTU frame in units of columns and outputs to the encoding unit;
Distributing means 303 is provided that distributes 16 bytes of a frame provided with redundancy input from the encoding means 302 to a plurality of logical lanes as one block, and assigns the logical lanes to physical lanes for transmission.

  According to the present invention (claim 6), the number of physical lanes is four and the number of logical lanes is four.

  The feature of the present invention is that error correction in the distribution unit 303 is performed in a transmission system in which a single signal is distributed and combined into a plurality of lanes by a transmission / reception unit in order to enable multi-lane transmission even in a situation where the BER is poor. Addition of error correction code to bit string used for lane identification and skew detection in encoding means 331, error correction using error correction decoding means 412 in combining means 401, and bit pattern verification in combining means 401 Bit pattern matching that uses a smaller number of bits than specified in the OTN recommendation in the bit string used for lane identification and skew detection in means 411, and bit error for the bit string used for lane identification and skew detection in error acceptance means 413 in combining means 401 Use one or more of acceptable Increase the error tolerance. It also extends the OTU frame structure to allow use of non-standard redundancy FEC. The OTU frame is reduced or increased in units of “LCM (number of logical lanes, 4) × 4” columns so that the signal can be distributed to each lane every 16 bytes (LCM means the least common multiple). Since the increment / decrement unit of the number of columns is the above-described column unit, a half-sized area that is not used as FEC may be generated.

  In addition, a configuration using four logical lanes is provided in order to increase error tolerance during OTU4 or OTU4V transmission. In the prior art, error tolerance has been a problem due to the large number of logical lanes.

  As described above, according to the present invention, the number of bits used for FAS and MFAS used for lane identification and skew detection is reduced in a transmission method in which a single signal is distributed and combined in a plurality of lanes by a transmission / reception unit. By performing bit pattern verification, bit error tolerance, and bit error correction, it is possible to operate normally even in a situation where the BER is poor. In addition, an error correction code other than the redundancy specified in the standard was used by increasing / decreasing the OTU frame length by “LCM (number of logical lanes, 4) × 4” (LCM means the least common multiple) column unit. Even in this case, a single signal can be distributed to a plurality of lanes. Further, in the case of multi-lane transmission of OTU4 or OTU4V, normal operation in a wider BER range is possible by setting the number of logical lanes to 4 instead of the standard 20.

It is a principle block diagram of this invention. It is a block diagram of the transmission apparatus in the 1st Embodiment of this invention. It is a figure which shows the OTU frame structure which enabled use of FEC of redundancy other than G.709 standard in the 1st Embodiment of this invention. It is a performance comparison result between 4 logical lanes and 20 logical lanes. It is a figure which shows the overhead used for deskew and lane identification in the case of 4 logical lanes in the 2nd Embodiment of this invention. It is a figure which shows the lane identification establishment characteristic (4-lane, no error tolerance) in the 2nd Embodiment of this invention. It is a figure which shows the lane discriminating characteristic (4-lane, no error tolerance etc.) in the 2nd Embodiment of this invention. It is a figure which shows the frame synchronization establishment characteristic (1 bit error tolerance) in the 3rd Embodiment of this invention. It is a figure which shows the frame synchronization establishment characteristic (2 bits error tolerance) in 3rd Embodiment. It is a figure which shows the loss-of-frame characteristic (1 bit error tolerance) in the 3rd Embodiment of this invention. It is a figure which shows the out-of-synchronization characteristic (2 bit error tolerance) in the 3rd Embodiment of this invention. It is the detail (OTU overhead) of the overhead area | region utilized in the 4th Embodiment of this invention. It is the detail (OTU overhead) of the overhead area | region utilized in the 4th Embodiment of this invention. It is a figure which shows the lane identification establishment characteristic (4-lane, 1 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane discriminating characteristic (4-lane, 1 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane discriminating characteristic (4-lane, 2 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane identification establishment characteristic (only 20th lane and the 6th byte of FAS are used) in the 4th Embodiment of this invention. It is a figure which shows the lane identification establishment characteristic (20-lane, only the 6th byte of FAS is used, 1 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane identification establishment characteristic (20-lane, using only the 6th byte of FAS, 2 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane discrimination | determination characteristic (only 20th lane and the 6th byte of FAS are used) in the 4th Embodiment of this invention. It is a figure which shows the lane discrimination | determination characteristic (20-lane, only the 6th byte of FAS is used, 1 bit error correction) in the 4th Embodiment of this invention. It is a figure which shows the lane discriminating characteristic (20-lane, using only the 6th byte of FAS, 2-bit error correction) in the fourth embodiment of the present invention. It is an example of the bit number reduction method used for the lane identification at the time of 4 lanes in the 5th Embodiment of this invention. It is an example of the bit number reduction method used for the lane identification at the time of 20 lanes in the 5th Embodiment of this invention. It is a lane discriminating characteristic (4-lane, using only 2 bits of each lane MFAS) in the fifth embodiment of the present invention. This is a lane identification loss characteristic (4-lane, using only 2 bits of each lane MFAS, 1-bit error correction) in the fifth embodiment of the present invention. It is a lane identification loss characteristic (20-lane, using only the 5th bit of the 6th byte of each lane FAS) in the fifth embodiment of the present invention. This is a lane identification loss characteristic (20-lane, using only 5 bits of 6th byte of each lane FAS, 1-bit error correction) in the fifth embodiment of the present invention. It is a block diagram of a transmission system. It is a figure which shows the skew generation in the conventional multilane transmission. It is a figure which shows a standard OTU frame structure. It is a figure which shows the division | segmentation method of the OTU frame used at the time of multilane transmission of the OTU frame prescribed | regulated by G.709 Amendment 3, Annex C. It is a figure which shows the division | segmentation method of the OTU frame prescribed | regulated by G.709 Amendment 3, Annex C. G.709 Amendment 3, the overhead used for skew detection and lane identification specified in Annex C (in the case of 20 logical lanes). It is a state transition diagram of frame synchronization and lane identification defined in ITU-T. It is a figure which shows a frame synchronization establishment characteristic. It is a figure which shows a frame synchronization loss characteristic. It is a figure which shows the lane identification establishment characteristic (20-lane, no error tolerance). It is a figure which shows a lane discrepancy characteristic (20-lane, no error tolerance etc.).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
The configuration of the transmission system of the present invention is the same as that of the transmission apparatuses 10 and 20 in FIG. 29 described above, but the functions of the transmission unit and the reception unit are different.

  In the present embodiment, in a transmission system in which a single signal using an OTU frame is transmitted by a plurality of physical lanes, the value obtained by multiplying the number of logical lanes and the least common multiple of 4 by four, that is, “LCM (logical The case of changing the FEC redundancy by increasing or decreasing the number of columns of the OTU frame in units of lanes, 4) × 4 ”columns will be described. However, LCM (X, Y) indicates the least common multiple of X and Y.

  Hereinafter, an OTU frame including standard redundancy and standard FEC is referred to as OTUk. A non-standard redundancy or FEC type is called OTUkV (V: vender specific).

  FIG. 2 shows the configuration of the transmission apparatus according to the first embodiment of the present invention. 2 includes a framer unit 301, an FEC encoding unit 302, and a distribution unit 303, and a receiving side device (receiving unit) 400 includes a combining unit 401 and FEC decoding. Part 402 and framer part 403.

  The framer unit 301 of the transmission unit 300 has a frame change function 311. When the redundancy of the error correction code is other than the standard redundancy of 6.7% in the frame change function 311, the OTU frame Are reduced or increased in units of “LCM (number of logical lanes, 4) × 4”. The FEC encoding unit 302 encodes a frame with the redundancy changed by the framer unit 301. The distribution unit 303 distributes 16 bytes to a plurality of logical lanes as one block, and includes an error correction encoding unit 331 that adds an error correction code to a bit string used for lane identification and skew detection.

  The combining unit 401 of the receiving unit 400 combines frames transmitted in a plurality of lanes, and includes a bit pattern matching unit 411, an error correction decoding unit 412, and an error permission unit 413. The FEC decoding unit 402 performs decoding based on the redundancy set in the frame. The framer unit 403 processes the decoded frame.

  Details of the error correction coding unit 331, the bit pattern matching unit 411, the error correction decoding unit 412, and the error permission unit 413 will be described later in the following embodiments.

  FIG. 3 shows an extended OTU frame structure that enables use of FEC with a redundancy other than the G.709 standard in the first embodiment of the present invention. In the figure, “FAS” is “frame alignment signal” and “OH” is “overhead”. The standard FEC redundancy is 256/3824 = 6.7% redundancy adding 256 columns redundancy (3825 to 4080 columns) to 3824 columns. In transmissions exceeding 100 Gb / s, in order to realize stronger error correction performance, it is considered to use FEC having a redundancy of about 20% different from the standard. When the FEC encoding unit 302 uses non-standard redundancy FEC, the framer unit 301 (frame change function 311) reduces the number of FEC columns in units of “LCM (number of logical lanes, 4) × 4” or By increasing the number, the distribution unit 303 can divide the OTU frame into 16-byte units without excess or deficiency, and can evenly distribute the plurality of logical lanes. Since columns are added in units of “LCM (number of logical lanes, 4) × 4” columns, a half-sized area that is not used as an FEC may be generated.

  “LCM (number of logical lanes, 4) × 4”, which is the unit of increase / decrease of the column, will be described. When distributing data to a plurality of logical lanes in units of 16 bytes, the number of blocks of 16 bytes needs to be a multiple of the number of logical lanes. Further, since the frame structure of the OTU is composed of 4 rows, it needs to be a multiple of 4. Therefore, the increase / decrease unit of the number of blocks is LCM (number of logical lanes, 4). Since the number of bytes to be increased or decreased is 16 bytes for one block, it is “LCM (number of logical lanes, 4) × 16” bytes. The number of columns corresponding to this number of bytes is divided by the number of rows in the OTU frame of 4 and becomes “LCM (number of logical lanes, 4) × 4” columns. When the number of columns is increased or decreased in such units, the OTU frame can be divided into 16-byte units without excess or deficiency, and can be evenly distributed to a plurality of logical lanes.

[Second Embodiment]
FIG. 34 shows the overhead (in the case of 20 logical lanes) used for lane identification and skew detection defined in G.709 Amendment 3, Annex C.

In OTU4 transmission, when the method described in G.709 Amendment 3, Annex C is applied to multilane transmission, it is conceivable to use 20 logical lanes as described above. At this time, the overhead used for lane identification and skew detection is 5 bytes shown in FIG. 34 for each logical lane. The total is 20 logical lanes × 5 bytes × 8 = 800 bits. When BER = 10 ⁻² or the like assumed in digital coherent transmission or the like, several bits (800 × 10 ⁻² = 8) are erroneously calculated in these bits. In such a state, normal lane identification and skew detection operations become difficult.

  Therefore, assuming a signal of 4 physical lanes such as a DP-QPSK signal, normal operation is realized even in a situation where the BER is poor by using 4 logical lanes.

  FIG. 4 is a calculation result comparing the performance of 4 logical lanes and 20 logical lanes. In the figure, the horizontal axis represents the code error rate of the signal input to the coupling unit 401 after transmission, and the vertical axis represents out-of-frame (OOF) or out-of-lane-alignment (OLA). The average occurrence interval is shown. Further, the case where there is an error tolerance described in a third embodiment described later is shown. Even if there is no error tolerance, the 4 logical lanes perform much better than the 20 logical lanes.

  FIG. 5 shows the overhead used for skew detection and lane identification in the case of four logical lanes in the second embodiment of the present invention.

  The difference from the case of 20 logical lanes is that FAS OH byte 6 is not used. FAS OH byte 6 was used in 20 logical lanes because the corresponding byte is used as a counter for one cycle in 240 frames (multiple of 20), and the remainder is divided by 20 on the receiving side. This was for use in logical lane identification.

On the other hand, MFAS (multi-frame alignment signal) (this is a counter of one cycle with 256 frames) can be used for this purpose in 4 logical lanes, so there is no need to use FAS OH byte 6 . From the above, the overhead used for lane identification and skew detection in 4 logical lanes is 4 bytes shown in FIG. 5 for each logical lane. The total is 4 logical lanes × 4 bytes × 8 = 128 bits. When BER = 10 ^−2, the number of overhead errors is 128 × 10 ⁻² = 1.28 bits, and the number of errors can be significantly reduced compared to 20 logical lanes. As a result, 4 logical lanes can operate normally over a wider BER range than 20 logical lanes. For example, when 4 logical lanes are applied to OTU4 or OTU4V transmission, the characteristics of lane identification establishment are as shown in FIG. 6, and the characteristics of lane identification loss are as shown in FIG. Compared to the drawings for 20 logical lanes (FIGS. 38 and 39), 4 logical lanes have much better characteristics than 20 logical lanes, that is, 4 logical lanes establish lane identification more quickly, It can be seen that once lane identification is established, the lane identification state is maintained for a longer time.
[Third Embodiment]
In the present embodiment, a case where a bit error is allowed in receiving section 400 shown in FIG. 2 will be described.

  In order to enable operation in a worse BER environment, the error tolerance unit 413 of the coupling unit 401 allows bit errors in FAS and / or MFAS, which are overhead used for lane identification and skew detection. . FAS has a fixed bit pattern, and FAS OH bytes 3 to 5 store the fixed bit pattern called OA1 (bit pattern “1111 0110”) and OA2 (bit pattern “0010 1000”). Indicates the start position. By allowing an n-bit bit error for this FAS OH byte, the normal operation range can be expanded.

  On the other hand, MFAS assigns 256 numbers (0 to 255) to each frame. Considering 4 logical lanes, “logical lane 0” has values of 0, 4, 8, 12,..., 252 for example, and “logical lane 1” is 1, 5, 9, 13,. “Logic Lane 2” has values of 2, 6, 10, 14,..., 254, and “Logic Lane 3” has values of 3, 7, 11, 15,. Looking at the MFAS received by each logical lane at a certain timing, for example, the value of logical lane (0, 1, 2, 3) = received MFAS (8, 9, 10, 11) is received. At this time, each logical lane has its own MFAS continuity (increment 4) and consistency with other logical lanes (four consecutive values), so operation is possible even if n-bit error in the overhead is allowed. It may become. Therefore, the normal operation range is expanded in the case of n-bit error tolerance.

  In addition, the number of forward protection steps may be used together as necessary for out of frame synchronization or out of lane identification. The allowable bit error number n is designed based on the assumed worst BER, the type of error (random, burst, etc.), the number of forward protection stages, and the like. In the following, numerical calculation results of characteristics when bit error is allowed for frame synchronization will be shown. The frame synchronization establishment characteristics when a 1-bit error is allowed are shown in FIG. 8, and the frame synchronization establishment characteristics when a 2-bit error is allowed are shown in FIG. Considering that FIG. 36 shows the characteristics when no error is allowed, it can be seen that the number of frames required to establish frame synchronization is significantly reduced and the characteristics are improved as the error tolerance is increased. However, since the probability of erroneous frame synchronization increases when the error tolerance is increased, it is necessary to design the erroneous frame synchronization probability to be sufficiently small in the BER that is expected to operate. Next, characteristics of loss of frame synchronization are shown in FIG. 10 (1 bit error allowed) and FIG. 11 (2 bit error allowed). Considering that the characteristics when the error is not allowed are the characteristics shown in FIG. 37, it is possible to increase the average time until the frame synchronization is lost by allowing the error of the frame synchronization loss as well. I understand.

[Fourth Embodiment]
In the third embodiment, an example in which a bit error is allowed in the receiving unit 400 shown in FIG. 2 has been described. In this embodiment, in order to further improve the tolerance against BER degradation of the overhead, an error of the combining unit 401 is performed. The correction decoding unit 412 performs error correction of FAS and / or MFAS, which are overhead used for skew detection and lane identification. In the error correction encoding unit 331 of the distribution unit 303, it is necessary to add a redundant bit string in order to perform error correction. For example, RES (one row, one row, unused area in the OTU overhead shown in FIG. 12). 13-14 columns) and GCC0 (1 row, 11-12 columns) that can be used for various purposes.

  In addition, other unused areas such as overhead (RES, GCC1, GCC2, EXP, etc. included in line 2-4) may be used as shown in FIG. However, it must be distributed to the same logical lane. By using these areas and adding redundant bits and adding an error correction code for the overhead, normal operation is possible even in a poor BER area.

  The numerical calculation results of the lane identification characteristics in the case of 4 logical lanes and 20 logical lanes are shown below. FIG. 14 shows the characteristics of lane identification establishment when a 1-bit error is corrected in the case of 4 logical lanes. Based on the fact that the characteristics when error correction is not performed are shown in FIG. 6, it can be understood that lane identification can be performed quickly by correcting 1 bit error. FIG. 15 shows the characteristics of lane discrepancy when 1-bit error is corrected in 4 logical lanes, and FIG. 16 shows characteristics when 2-bit error is corrected. Considering that the characteristics when error correction is not performed are shown in FIG. 7, it is possible to increase the time until lane identification is removed by performing error correction. Next, characteristics in the case of 20 logical lanes are shown. The FAS 6th byte and MFAS are used in combination for lane identification and skew detection of the 20 logical lanes defined in the standard, but here only the 6th byte of FAS is identified and skewed in order to improve error tolerance. Consider using it for detection. First, FIG. 17 shows the characteristics of lane identification establishment when the number of bits used for lane identification is reduced by using only the sixth byte of FAS. Based on the fact that the characteristics of the standard are shown in FIG. 38, it can be seen that rapid lane identification can be realized. Next, FIG. 18 (1-bit error correction) and FIG. 19 (2-bit error correction) show the characteristics of lane identification when error correction is used in addition to the reduction in the number of bits used. It can be seen that the higher the number of error corrections, the better the characteristics. Next, the characteristics of lane identification loss are shown in FIG. 20 (when only the FAS 6th byte is used to reduce the number of bits used for lane identification), FIG. 21 (when only the FAS 6th byte is used and 1 bit error correction is performed), FIG. 22 (when only the 6th byte of FAS is used and 2-bit error correction is performed) is shown. Compared with FIG. 39 showing the standard-defined characteristics, it is possible to increase the time until the lane identification is deviated, and it is understood that the characteristics are remarkably good.

  As a specific method of error correction, a CRC code, a Hamming code, a Reed-Solomon code, or the like can be used. It is also possible to use majority decision. As a method of reducing the number of bits to be used, in the case of the 20 logical lanes shown above as an example, the standard specification uses 16 bits combining the FAS 6th byte and MFAS. For example, a method using only 5 bits that can identify 20 logical lanes (because 5 bits can represent 32 patterns), a method using only 2 bits of MFAS in 4 logical lanes, etc. By reducing the number of bits used, it is possible to reduce the probability that a bit error will occur in those bits, and to realize good characteristics. Furthermore, better characteristics can be realized by using a combination of error tolerance and error correction for the reduced number of bits. (A detailed example of the reduction in the number of used bits will be described below as a fifth embodiment.) Although the method for reducing the number of bits used for error correction code and lane identification has been described above, the present invention is not limited to this. is not.

Further, the third embodiment and the fourth embodiment may be combined and used, for example, by allowing bit error for FAS and correcting bit error for MFAS.
[Fifth Embodiment]
In this embodiment, an example is shown in which a bit pattern matching unit 411 in which the number of bits used for lane identification is shorter than a standard rule is used. FIG. 23 shows an example of reducing the number of bits used for lane identification when there are 4 logical lanes, and FIG. 24 shows an example of reducing the number of bits used for lane identification when there are 20 logical lanes. In the case of 4 logical lanes, the standard specifies that 8 bits of MFAS are used, but even if only 2 bits of 7th and 8th bits of MFAS are used as shown in FIG. 23 (0, 0), Four types can be expressed as (0, 1), (1, 0), (1, 1). Similarly, in the case of 20 logical lanes, the standard specifies that the 6th byte of FAS and MFAS are combined and 16 bits are used. However, as shown in FIG. 24, 4, 5, 6, 7, Even using only the 5th bit of the 8th bit, 20 patterns (0, 0, 0, 0, 0) to (1, 0, 0, 1, 1) can be expressed. If the above numbers are assigned, lane identification can be performed on the receiving side.

  The effect of reducing the number of bits used for lane identification is shown by numerical calculation of the lane identification loss characteristic. FIG. 25 shows the lane identification loss characteristics when only 2 bits of MFAS are used in each lane as described above in the case of 4 logical lanes. Considering that the characteristic when the number of used bits is not reduced is that shown in FIG. 7, it is possible to significantly increase the time until lane identification is lost. FIG. 26 shows the lane identification loss characteristics when the number of used bits is reduced and 1-bit error correction is performed. It can be seen that it has even better characteristics.

  Next, FIG. 27 (no error correction or the like) and FIG. 28 (1 bit error correction) show the lane identification loss characteristics when only 5 bits of the 6th FAS byte are used in each lane for 20 logical lanes. Considering that the characteristic when the number of used bits is not reduced is that shown in FIG. 39, it is possible to significantly increase the time until the lane identification is deviated.

  For the lane identification, the number of protection stages can be used. For example, regarding the number of backward protection stages when establishing the lane identification, for example, when the number of backward protection stages is M, the consistency of all lanes in the lane identification out-of-lane state It is considered that the lane identification is established when the obtained lane identification is performed M times, and when the number of forward protection stages is N, the lane identification established state transitions to the lane identification loss state when the consistent lane identification cannot be performed N times. This method is considered as an example. Alternatively, since the lane number (the value of the sixth byte of FAS or the value of MFAS) received in each lane has a certain rule in each lane, a method of setting the protection stage number separately from the lane identification for each lane is also conceivable. For example, when the number of forward protection stages is N, each lane independently confirms the lane number of its own lane. However, a method of transitioning to the lane identification failure state also in the entire lane when the lane identification failure state occurs. Since the bit error tolerance varies depending on the method for setting the number of protection stages, the design is performed based on the assumed BER region.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

10 Transmission equipment (transmission side)
11 Transmission unit 12 Wavelength multiplexing unit 20 Transmission device (reception side)
21 wavelength demultiplexing unit 22 receiving unit 30 optical fiber 111 framer unit 112 FEC encoding unit 113 distribution unit 221 combining unit 222 FEC decoding unit 223 framer unit 300 transmitting side device, transmission unit 301 frame generation unit, framer unit 302 encoding unit , FEC encoding unit 303 Distributing unit, distributing unit 311 Frame changing function 331 Error correction encoding unit, error correction encoding unit 400 Receiving side device, receiving unit 401 Combining unit, combining unit 402 Decoding unit, FEC decoding unit 403 Frame processing means, framer section 411 bit pattern matching means, bit pattern matching section 412 error correction decoding means, error correction decoding section 413 error permission means, error permission section

Claims (6)

A multilane transmission method in a multilane transmission system having a transmission side device that transmits a single signal using an OTU frame (OTUk or OTUkV) by a plurality of physical lanes and a reception side device that combines received frames,
The multilane transmission system includes:
In the transmission side device,
An error correction code is added using an overhead area to the bit string used for the frame synchronization or the bit string used for the lane identification, or both,
In the receiving device,
An error correction step is performed in which error correction is performed on the bit string used for frame synchronization in the OTU frame, the bit string used for lane identification, or both using an error correction code added by the transmission side device. Multilane transmission method. In the transmission side device,
When the redundancy of the error correction code is other than the standard redundancy of 6.7%, a value obtained by multiplying the number of logical lanes and the least common multiple of 4 by 4, ie, “LCM (number of logical lanes, 4) × 4” ”Decrease or increase the number of columns in the OTU frame per column,
The multi-lane transmission method according to claim 1, wherein 16 bytes of the frame are distributed as a block to a plurality of logical lanes, and the logical lanes are allocated to physical lanes for transmission. The multilane transmission method according to claim 1 or 2, wherein the number of physical lanes is four and the number of logical lanes is four. A multi-lane transmission system comprising: a transmission side device that transmits a single signal using an OTU frame (OTUk or OTUkV) through a plurality of physical lanes; and a reception side device that combines received frames.
An error correction coding means for adding an error correction code to the transmission side device using an overhead region for the bit string used for the frame synchronization or the bit string used for the lane identification, or both;
Error correction decoding in which the receiving side apparatus performs error correction using the error correction code added by the transmitting side apparatus on the bit string used for frame synchronization in the OTU frame and / or the bit string used for lane identification Means,
A multi-lane transmission system characterized by comprising: The transmitting device is:
When the redundancy of the error correction code is other than the standard redundancy of 6.7%, a value obtained by multiplying the number of logical lanes and the least common multiple of 4 by 4, ie, “LCM (number of logical lanes, 4) × 4” A frame generating means for decreasing or increasing the number of columns of the OTU frame per column and outputting to the encoding means;
Distributing means for distributing 16 bytes of a frame provided with redundancy input from the encoding means to a plurality of logical lanes as one block, and assigning the logical lanes to physical lanes for transmission.
The multi-lane transmission system according to claim 4. The multilane transmission system according to claim 4 or 5, wherein the number of physical lanes is four and the number of logical lanes is four.

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