JP2012060331A - Reception apparatus and reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure merits depending on circuit scale, and implement a high precision error correction in various environments.SOLUTION: A reception apparatus is so configured that a first decoding section performs a first decoding process on received coded data, parallel sections of a second decoding section perform a plurality of systems of parallel and individual decoding processes on the received coded data and error correction information generated by the first decoding section, and an integration/selection section of the second decoding section integrates or selects outputs of the parallel sections to generate final corrected data in the second decoding section.

Description

  The present invention relates to a receiving apparatus and a receiving method that perform error correction on received encoded data, and in particular, can obtain merits according to the circuit scale and perform high-accuracy error correction in various environments. The present invention relates to a receiving apparatus and a receiving method capable of performing the above.

  In recent years, in-vehicle DTV (digital television) receivers have become widespread. The DTV broadcast wave conforms to the OFDM (Orthogonal Frequency Division Multiplexing) system, and when demodulating information from the DTV broadcast wave, it is necessary to perform so-called OFDM demodulation.

  By the way, in the above-mentioned in-vehicle DTV receiver, the reception environment constantly changes according to the speed and direction of the vehicle and the environment around the vehicle. Therefore, it is possible to stably receive broadcast waves even in such a mobile environment. It has been demanded.

  For this reason, it is widely performed to improve reception performance using an error correction circuit (error correction unit) that performs error correction of a received signal. Here, error correction decoding methods such as Viterbi decoding and Reed-Solomon decoding (hereinafter referred to as “RS decoding”) are widely used for error correction of received signals. . The reception performance is generally indicated by a carrier-to-noise ratio (hereinafter referred to as “CN ratio”), throughput, and the like.

  Various techniques have been proposed for the purpose of further improving the reception performance. For example, a technique aimed at improving the CN ratio includes feeding back an error correction result by a concatenated decoding circuit in which a Viterbi decoding circuit and an RS decoding circuit are connected in series, and performing error correction by the concatenated decoding circuit with a predetermined likelihood. There is something to do repeatedly.

  In addition, in the technology aimed at improving throughput, a plurality of Viterbi decoding circuits having different constraint lengths indicating redundancy for error correction are provided, and the Viterbi decoding circuit is appropriately selected according to the importance of the received signal. Some of them perform error correction (see Patent Document 1).

JP 2006-094051 A

  However, when the technique for repeatedly performing error correction using the above-described concatenated decoding circuit is used, the error correction pattern is fixed to repeat the process with a predetermined likelihood, and the error correction amount is saturated at a constant amount. was there. That is, although the circuit scale is increased by repetition, it is difficult to obtain a merit corresponding to the increase in the circuit scale.

  In addition, when the technique of Patent Document 1 is used, the reception performance can be improved according to the importance of the received signal. However, for example, when multipath or fading occurs in the above-described mobile environment, the influence is affected. I could not respond.

  From these, it is a big problem how to realize a receiving apparatus or receiving method that can obtain merit according to the circuit scale and can perform highly accurate error correction in various environments. It has become.

  The present invention has been made to solve the above-described problems caused by the prior art, and can obtain merits according to the circuit scale and perform high-precision error correction in various environments. An object of the present invention is to provide a receiving apparatus and a receiving method capable of performing the above.

  In order to solve the above-described problems and achieve the object, the present invention is a receiving device that performs error correction on received encoded data, and is generated by decoding the encoded data and the encoded data. Parallel correction means for performing error correction in parallel with a plurality of systems on the received encoded data based on error correction information, and adjustment means for individually adjusting the error correction information different for each system It is characterized by that.

  Further, the present invention is a reception method for performing error correction on received encoded data, the received encoded data based on the encoded data and error correction information generated by decoding the encoded data. On the other hand, a parallel correction process for performing error correction in parallel in a plurality of systems and an adjustment process for individually adjusting the error correction information different for each system are provided.

  According to the present invention, based on encoded data and error correction information generated by decoding the encoded data, the received encoded data is corrected in parallel in a plurality of systems, and each system is corrected. Since different error correction information is individually adjusted, it is possible to obtain merits according to the circuit scale and to perform highly accurate error correction even in various environments.

FIG. 1 is a diagram showing an outline of an error correction method according to the present invention. FIG. 2 is a block diagram illustrating the configuration of the receiving apparatus according to the present embodiment. FIG. 3 is a diagram for explaining the circuit scale of the receiving apparatus. FIG. 4 is a diagram for explaining the expandability of the receiving apparatus. FIG. 5 is a diagram for explaining likelihood adjustment processing performed by the likelihood adjustment unit. FIG. 6 is a diagram for explaining the integration selection process performed by the integration selection unit. FIG. 7 is a flowchart illustrating a processing procedure of the first decoding process executed by the receiving device. FIG. 8 is a flowchart illustrating a processing procedure of the second decoding process executed by the receiving device.

  Exemplary embodiments of a receiving apparatus and a receiving method according to the present invention are explained in detail below with reference to the accompanying drawings. In the following, the outline of the error correction method according to the present invention will be described with reference to FIG. 1, and then an embodiment of a receiving apparatus to which the error correction method according to the present invention is applied will be described with reference to FIGS. I decided to.

  First, the outline of the error correction method according to the present invention will be described with reference to FIG. FIG. 1 is a diagram showing an outline of an error correction method according to the present invention. Note that (A) in the figure shows the problems of the error correction technique according to the prior art, and (B) in the figure shows the characteristics of the error correction technique according to the present invention.

  As shown in (A-a) of the figure, in the error correction method according to the prior art, error correction is performed by sequentially passing the received signal to a predetermined decoding processing circuit connected in series. .

  Specifically, the decoding of the previous stage is performed such that the received signal that has been subjected to error correction by the decoding process circuit of the first stage is input to the decoding process circuit of the second stage and then the decoding process of the second stage is performed. The error correction is performed while sequentially taking over the error correction result by the processing circuit to the subsequent decoding processing circuit.

  That is, the accuracy of error correction is improved by repeating the predetermined decoding process. However, as described above, the repetition of the predetermined decoding process causes the error correction pattern to be fixed and the error correction amount to be saturated.

  For example, (Ab) in the figure shows an increase in the amount of error correction from the previous stage at each time point t1 to t5 of each decoding process shown in (Aa) in the figure (see the hatched portion in the figure). ) And the total amount of error correction including the increased amount.

  According to (Ab) in the figure, the error correction amount increases until the third stage decoding process (see t3 in the figure), but the increment is gradually decreased, and the fourth or fifth stage. It can be seen that there is no increase at the time points t4 and t5 of the decoding process, and that the total amount of error correction is saturated by a certain amount (so-called peaked state).

  That is, although the circuit scale and the processing time are increased by repeating the predetermined decoding process, it is not possible to obtain a merit that matches the increase in the circuit scale and the processing time.

  Therefore, in the error correction method according to the present invention, the second-stage decoding process that takes over the error correction result of the first-stage decoding process is configured as a parallel decoding process. Specifically, as shown in the part surrounded by the broken closed curve 1 in (Ba) in the figure, the decoding processing circuits in the second stage are connected in parallel, and each decoding is performed. The error correction result of the decoding process by the processing circuit is “integrated” or “selected” in the integration selection process.

  Here, each decoding process by the “parallel” decoding processing circuit is represented as “decoding process α”, “decoding process β”, and “decoding process γ” in the figure, respectively. Process.

  Such “individual” decoding processing can be realized by performing “individual likelihood adjustment” in accordance with various environments such as a fading environment and a multipath environment. Details of this point will be described later with reference to FIG.

  In the integration selection process, error correction results are optimized by “integrating” or “selecting” each error correction result obtained by the “individual” decoding process. Details of the integration selection process will be described later with reference to FIG.

  As a result, as shown in (Bb) of the figure, the error correction amount can be quickly increased by a predetermined amount at time t2 of the second-stage parallel decoding process. That is, high-accuracy error correction that matches the circuit scale and processing time can be performed. Accordingly, it is possible to eliminate the decoding process at the subsequent time points t3 to t5.

  As described above, in the error correction method according to the present invention, the decoding processing circuits are connected in “parallel”, and each decoding processing by the decoding processing circuits is performed “individually” and “in parallel”. . Further, the error correction results are optimized by “integrating” or “selecting” the error correction results of the decoding processes performed “individually” and “parallel”.

  Therefore, a merit according to the circuit scale can be obtained, and highly accurate error correction can be performed even in various environments. By connecting the decoding processing circuits “in parallel” in this way, there is an advantage that the internal buffer can be shared between the circuits. Details of this point will be described later with reference to FIGS.

  Hereinafter, an embodiment of the receiving apparatus to which the error correction method described with reference to FIG. 1 is applied will be described in detail. Hereinafter, the fact that the subsequent decoding process takes over the error correction result of the preceding decoding process is referred to as “feedback”.

  FIG. 2 is a block diagram illustrating a configuration of the receiving device 10 according to the present embodiment. In the figure, only components necessary for explaining the characteristics of the receiving apparatus 10 are shown, and descriptions of general components are omitted.

  Further, in the same figure, each parallel unit included in the second decoding unit 12 corresponding to the “parallel decoding process (second stage)” illustrated in FIG. 1 is represented as a first parallel unit 12-1 and a second parallel unit 12-. Branch numbers are given as shown in 2 or the third parallel part 12-3.

  As illustrated in FIG. 2, the reception device 10 includes a first decoding unit 11, a second decoding unit 12, a third decoding unit 13, and a storage unit 14. The first decoding unit 11 further includes an FFT unit 11a, a demapping unit 11b, a Viterbi decoding unit 11c, a byte deinterleaving unit 11d, and an RS decoding unit 11e.

  The second decoding unit 12 further includes a plurality of parallel units including a first parallel unit 12-1, a second parallel unit 12-2, and a third parallel unit 12-3. The first parallel unit 12-1 includes a byte interleaving unit 12-1a, a likelihood adjusting unit 12-1b, a Viterbi decoding unit 12-1c, a byte deinterleaving unit 12-1d, and an RS decoding unit 12- 1e.

  In addition, the structure of each parallel part containing the 2nd parallel part 12-2 and the 3rd parallel part 12-3 shall be the same as that of the 1st parallel part 12-1. Accordingly, hereinafter, each parallel unit included in the second decoding unit 12 will be described using the first parallel unit 12-1.

  The storage unit 14 includes a plurality of likelihood adjustment parameters including a first likelihood adjustment parameter 14-1, a second likelihood adjustment parameter 14-2, and a third likelihood adjustment parameter 14-3, and a delay. Each of the buffers 14a is stored.

  The first decoding unit 11 is a processing unit corresponding to the “decoding process (first stage)” illustrated in FIG. 1 and performs processing such as acquisition of encoded data, demapping, and error correction. The FFT unit 11a is a processing unit that performs processing of acquiring encoded data superimposed on a carrier wave by FFT (Fast Fourier Transform) and outputting the acquired encoded data to the demapping unit 11b. .

  The demapping unit 11b is a processing unit that performs a process of demapping the encoded data input from the FFT unit 11a and outputting the demapped data to the Viterbi decoding unit 11c. The demapping unit 11b also stores the demapped data in the delay buffer 14a.

  The Viterbi decoding unit 11c is a processing unit that performs error correction by Viterbi decoding based on the demapped data input from the demapping unit 11b, and outputs the corrected data to the byte deinterleave unit 11d. . The Viterbi decoding unit 11c also performs a process of outputting the likelihood generated at the time of error correction by Viterbi decoding to the byte deinterleaving unit 11d.

  Specifically, the Viterbi decoding unit 11c calculates a branch metric and a path metric indicating the likelihood of each path based on the Hamming distance between the demapped data and the data corresponding to each path in the trellis diagram.

  Then, the Viterbi decoding unit 11c estimates the maximum likelihood path based on the calculated branch metric and path metric, and outputs a bit string corresponding to the maximum likelihood path as corrected data.

  The byte deinterleave unit 11d rearranges and arranges the parts rearranged in units of bytes on the transmission device side for the purpose of improving correction accuracy when a burst error occurs, included in the corrected data input from the Viterbi decoding unit 11c. It is a processing unit that performs a process of outputting the returned data to the RS decoding unit 11e. Further, the byte deinterleaving unit 11d also performs a process of outputting the likelihood input from the Viterbi decoding unit 11c to the RS decoding unit 11e.

  The RS decoding unit 11e performs error correction by RS decoding based on the rearranged data input from the byte deinterleave unit 11d, and outputs the corrected data to each parallel unit of the second decoding unit 12. It is a processing part to perform.

  The RS decoding unit 11e also performs a process of outputting the likelihood input from the byte deinterleaving unit 11d to each parallel unit of the second decoding unit 12. Hereinafter, the information including the corrected data and the likelihood output from the RS decoding unit 11e is referred to as “error correction information”.

  The second decoding unit 12 is a processing unit corresponding to the “parallel decoding process (second stage)” illustrated in FIG. 1, the “encoded data” acquired by the first decoding unit 11, and the decoding unit 11. Is a processing unit that performs error correction on encoded data by integrating or selecting error correction results after performing error correction individually in parallel based on the “error correction information” generated by.

  The first parallel unit 12-1 is one of a plurality of parallel units that are included in the second decoding unit 12 and execute decoding processing in parallel. The byte interleaving unit 12-1a rearranges the corrected data included in the error correction information input from the RS decoding unit 11e of the first decoding unit 11 in units of bytes and outputs the data to the likelihood adjustment unit 12-1b Is a processing unit.

  The likelihood adjustment unit 12-1b adjusts the likelihood included in the error correction information input from the byte interleaving unit 12-1a based on the adjustment parameter stored in the first likelihood adjustment parameter 14-1. It is a processing part to perform. Details of the likelihood adjustment processing will be described later with reference to FIG.

  The Viterbi decoding unit 12-1c performs error correction by Viterbi decoding and outputs the corrected data to the byte deinterleaving unit 12-1d, similarly to the Viterbi decoding unit 11c of the first decoding unit 11 described above. It is a processing part to perform.

  However, the Viterbi decoding unit 11c of the first decoding unit 11 is a point in which post-demapping data serving as input data is input from the delay buffer 14a of the storage unit 14, and the likelihood adjusted by the likelihood adjusting unit 12-1b. The difference is that the maximum likelihood path is estimated based on the above.

  The byte deinterleaving unit 12-1d is a processing unit that performs processing of rearranging the data rearranged in the byte interleaving unit 12-1a and outputting the rearranged data to the RS decoding unit 12-1e.

  Similar to the RS decoding unit 11e of the first decoding unit 11 described above, the RS decoding unit 12-1e performs error correction by RS decoding, and performs processing to output the corrected data to the integrated selection unit 12a. It is.

  The integration selection unit 12a is a processing unit that performs processing of integrating or selecting the corrected data input from the parallel units and outputting the final corrected data in the second decoding unit 12. The corrected data may be output from the integration selection unit 12 a to an external device, or may be output to the third decoding unit 13 and further subjected to a decoding process by the third decoding unit 13. Details of integration or selection processing by the integration selection unit 12a will be described later with reference to FIG.

  The third decoding unit 13 is a processing unit that performs a decoding process based on the corrected data when the corrected data is input from the second decoding unit 12. In addition, about the structure of this 3rd decoding part 13, it is good also as a structure which performs a serial decoding process like the 1st decoding part 11, and a parallel decoding process like the 2nd decoding part 12 It is good also as composition which performs.

  The storage unit 14 is a storage unit configured by a storage device such as a hard disk drive, a nonvolatile memory, or a register, and includes a first likelihood adjustment parameter 14-1, a second likelihood adjustment parameter 14-2, and a third likelihood. A plurality of likelihood adjustment parameters including the degree adjustment parameter 14-3 and the delay buffer 14a are stored.

  The first likelihood adjustment parameter 14-1, the second likelihood adjustment parameter 14-2, and the third likelihood adjustment parameter 14-3 are the likelihoods when performing Viterbi decoding in each parallel unit of the second decoding unit 12. The parameter to be adjusted. Details of the parameter contents will be described later with reference to FIG.

  In FIG. 2, the likelihood adjustment parameters 14-1 to 14-1 are examples corresponding to the second decoding unit 12, but Viterbi decoding in the first decoding unit 11 or the third decoding unit 13 is shown. It is good also as using in the case of.

  The delay buffer 14a is a storage area for storing encoded data after demapping acquired by the first decoding unit 11. The delay buffer 14a plays a role of waiting for the so-called first stage decoding process executed by the first decoding unit 11 from the second stage and subsequent decoding processes.

  Here, advantages of the receiving device 10 from the circuit scale will be described in comparison with a conventional receiving device. FIG. 3 is a diagram for explaining the circuit scale of the receiving apparatus 10. In addition, (A) in the figure shows a simplified diagram of the circuit configuration in the conventional receiving apparatus, and (B) in the figure shows a simplified diagram of the circuit configuration in the receiving apparatus 10 according to the present embodiment. ing.

  As shown in FIG. 6A, in the conventional receiving apparatus, a circuit is provided so as to improve the accuracy of the decoding process by feeding back the decoding result of the preceding stage sequentially starting from the decoding result of the decoding unit (first stage). Was configured. Therefore, a feedback circuit for feedback is required between the decoding units. Further, as shown in FIG. 5A, each of the decoding units in the second and subsequent stages requires a dedicated delay buffer.

  In this regard, as shown in (B) of the figure, according to the receiving device 10 according to the present embodiment, in the second decoding unit 12 corresponding to the second stage, the first parallel unit 12-1 and the second parallel unit 12. -2 and the third parallel unit 12-3 are configured to perform the decoding process in parallel, so that the feedback circuit and the delay buffer 14a can be shared. Therefore, it can be made compact in terms of circuit scale as compared with the conventional receiving apparatus.

  Such a circuit scale advantage is also advantageous in terms of scalability. FIG. 4 is a diagram for explaining the expandability of the receiving device 10. Note that (A) in the figure is a diagram for explaining the extensibility in the conventional receiving apparatus, and (B) in the figure is for explaining the extensibility in the receiving apparatus 10 according to the present embodiment. Each figure is shown.

  As shown in the portion surrounded by the broken closed curve 2 in FIG. 5A, when the circuit of the decoding unit (fifth stage) is added in the conventional receiving apparatus, the feedback circuit and the five stages are added along with the addition. It was necessary to add a delay buffer for the eye. In other words, it is necessary to newly secure a region for arranging the feedback circuit and the delay buffer for the fifth stage in conjunction with the addition of one circuit of the decoding unit (the fifth stage).

  In this regard, as shown in the portion surrounded by the broken closed curve 3 in FIG. 5B, according to the receiving device 10 according to the present embodiment, when the circuit of the fourth parallel unit 12-4 is added, With such an extension, the input wiring from the existing feedback circuit and the input wiring from the delay buffer 14a can be branched (see the broken arrow in FIG. 5B). That is, it is not necessary to newly secure an area for arranging the feedback circuit and the dedicated delay buffer in conjunction with the addition of one circuit of the fourth parallel unit 12-4.

  Further, according to the receiving device 10 according to the present embodiment, it is possible to connect and add decoding processing circuits in parallel instead of connecting them in series as in the conventional receiving device, so that the influence of the decoding result in the previous stage is reduced. It is possible to easily add a decoding processing circuit that does not receive.

  In other words, when the amount of error correction reaches the peak for the circuit scale, and it is difficult to obtain the merit according to the circuit scale, error correction is performed from a new viewpoint (for example, by performing a new likelihood adjustment). It is possible to easily add a decoding processing circuit to be performed, and to easily obtain a merit according to the circuit scale.

  Next, details of the likelihood adjustment processing performed by the likelihood adjustment unit 12-1b illustrated in FIG. 2 will be described with reference to FIG. FIG. 5 is a diagram for explaining likelihood adjustment processing performed by the likelihood adjustment unit 12-1b. Note that (A) in the figure shows a basic example of the likelihood adjustment process, (B) in the figure shows an example of setting each likelihood adjustment parameter, and (C) in the figure shows various examples. A correspondence example between the environment and each likelihood adjustment parameter is shown.

  As shown to (A) of the figure, the likelihood adjustment part 12-1b refers to the corrected data of the error correction information input from the RS decoding part 11e via the byte interleaving part 12-1a, and It is determined that the likelihood adjustment is performed for the normal location (see “normal location” in the “feedback data” item) (see “Yes” in the “likelihood adjustment” item). Further, it is determined that the likelihood adjustment is not performed for the error location (see “error location” in the “feedback data” item) (see “No” in the “likelihood adjustment” item).

  And as shown to (A) of the figure, when performing likelihood adjustment, the likelihood adjustment part 12-1b adds a branch metric (BM addition) about the path | pass which corresponds to the data after correction, and does not correspond. For a certain path, likelihood adjustment is performed by subtracting the branch metric (BM subtraction) (see “path” item).

  Further, as shown in FIG. 5A, the likelihood adjustment unit 12-1b, when performing likelihood adjustment, increases or decreases the branch metric addition / subtraction amount when the amount of error locations in the corrected data is large. Make adjustments to increase (see “Large” in “Error amount”). This is intended to prevent the path metric from becoming difficult to fluctuate with this because the frequency of adding and subtracting branch metrics decreases when the amount of error locations in the corrected data is large.

  On the other hand, as shown to (A) of the figure, likelihood adjustment part 12-1b performs adjustment which makes the addition / subtraction amount of a branch metric small, when the amount of the error location in corrected data is small ("" (See “Small” in the “Error amount” item.) This is intended to prevent the path metric from fluctuating excessively because the frequency of adding / subtracting branch metrics increases when the amount of error locations in the corrected data is small.

  Then, on the premise of such a basic example of the likelihood adjustment process, settings as shown in FIG. 5B can be made for each likelihood adjustment parameter in the storage unit 14. As shown in FIG. 5B, each likelihood adjustment parameter includes “addition” item, “subtraction” item, “addition value” item, “subtraction value” item, and “conditions”. Information including items. The “conditions” item can include various conditions such as an “error density” item and a “speed” item.

  The “addition” item is an item in which a setting value indicating whether or not to perform likelihood adjustment for adding a branch metric when likelihood adjustment is performed is stored. Similarly, the “subtraction” item is an item in which a setting value indicating whether or not likelihood adjustment for subtracting the branch metric is performed is stored. Note that (B) in the figure shows an example in which the set value is set according to “Yes” or “No”.

  The “addition value” item is an item in which a prescribed addition value in the case of performing likelihood adjustment by “addition” is stored. Similarly, the “subtraction value” item is an item in which a predetermined subtraction value in the case of performing likelihood adjustment by “subtraction” is stored. Note that the predetermined addition / subtraction value can be adjusted at any time according to the amount of error portions in the corrected data.

  The “conditions” item is an item for storing parameters for performing adjustment according to various reception environments. The “error density” item is an item in which a setting value indicating whether or not to consider an environment in which a burst-like error is likely to occur with a high density of error locations is stored.

  Further, the “speed” item is an item in which a setting value for determining whether or not to consider an environment in which the distribution of error locations is likely to fluctuate depending on the moving speed or the like is stored. Note that (B) in the figure shows an example in which “◯” mark is set when each environment is considered, and “−” mark is set when the environment is not considered.

  Then, for example, when referring to the first likelihood adjustment parameter shown in FIG. 5B, the likelihood adjustment unit 12-1b adds or subtracts the addition value “X1” and the subtraction value “Y1” to the branch metric. Therefore, the likelihood adjustment that does not consider “error density” and “speed” is performed.

  Similarly, when referring to the second likelihood adjustment parameter shown in FIG. 5B, the likelihood adjustment unit 12-1b adds the addition value “X2” to the branch metric, The likelihood adjustment considering “speed” is performed.

  Similarly, when referring to the third likelihood adjustment parameter shown in FIG. 5B, the likelihood adjustment unit 12-1b subtracts the subtraction value “Y2” from the branch metric, The likelihood adjustment considering “” is performed.

  By providing the setting value for each likelihood adjustment parameter as described above, the receiving apparatus 10 according to the present embodiment can perform error correction suitable for various environments. In addition, by performing error appropriateness suitable for each of various environments in parallel, it is possible to realize highly accurate error correction utilizing each advantage.

  For example, as shown in (C) of the figure, the likelihood adjustment parameter optimized for the AWGN (Additive white Gaussian Noise) environment is stored in the first likelihood adjustment parameter 14-1. When the first likelihood adjustment parameter 14-1 and the first parallel unit 12-1 are associated with each other, the first parallel unit 12-1 can perform error correction specialized for the AWGN environment.

  Similarly, after storing the likelihood adjustment parameter optimized for the fading environment in the second likelihood adjustment parameter 14-2, the second likelihood adjustment parameter 14-2 and the second parallel unit 12-2 are In the case of association, the second parallel unit 12-2 can perform error correction specialized for the fading environment.

  Similarly, after the likelihood adjustment parameter optimized for the multipath environment is stored in the third likelihood adjustment parameter 14-3, the third likelihood adjustment parameter 14-3 and the third parallel unit 12- 3 is associated, the third parallel unit 12-3 can perform error correction specialized for the multipath environment.

  Then, by integrating or selecting the error correction results by the parallel units, the receiving apparatus 10 according to the present embodiment can output the corrected data after error correction with high accuracy. This point will be described below with reference to FIG.

  FIG. 6 is a diagram for explaining the integration selection process performed by the integration selection unit 12a. Note that (1) in the figure shows an example of the corrected data output from the first decoding unit 11 in the first stage, and (2) in the figure shows each example of the second decoding unit 12 in the second stage. Examples of corrected data output by the processing unit are shown. In the figure, “□” marks indicate normal bits in the corrected data, and “■” marks indicate error bits.

  First, it is assumed that, as a result of the decoding process in the first decoding unit 11 in the first stage, corrected data (number of error bits = 14) shown in FIG. That is, the corrected data is output to the second decoding unit 12 at the second stage as error correction information (feedback data).

  Then, as shown in (2-1) in the figure, different corrected data is obtained by the decoding process in each parallel unit 12-1 to 12-3 of the second decoding unit 12 based on the feedback data. (Refer to (2-1a) to (2-1c) in the figure).

  For example, (2-1a) in the figure shows an example in which corrected data with the number of error bits = 8 is output by the decoding process in the first parallel unit 12-1. Further, (2-1b) in the figure shows an example in which corrected data with the number of error bits = 10 is output by the decoding process in the second parallel unit 12-2. Further, (2-1c) in the figure shows an example in which the corrected data with the number of error bits = 21 is output by the decoding process in the third parallel unit 12-3.

  As already described above, the parallel units 12-1 to 12-3 of the second decoding unit 12 can perform error correction specialized for individual environments, for example, by performing different likelihood adjustments. . Therefore, as shown in (2-1) in the figure, the error correction results of the parallel units 12-1 to 12-3 are likely to be different from each other.

  Further, as shown in (2-1c) of the figure, by the decoding process in the second decoding unit 12, more error bits than the corrected data (number of error bits = 14) output from the first decoding unit 11 (Error bit number = 21) may be detected. This is because, in the decoding process of the third parallel unit 12-3 shown in (2-1c) of the figure, especially when likelihood adjustment is performed by narrowing down the “conditions” (see FIG. 5B). Easy to happen.

  Then, as shown in (2-2) of FIG. 6, the integration selection unit 12a integrates or selects the corrected data output from the parallel units 12-1 to 12-3, so that the second decoding unit 12 finally The corrected data to be output automatically is generated.

  For example, as shown in (2-2) of the figure, the integration selecting unit 12a sets the error bit included in each corrected data output by each parallel unit 12-1 to 3 to be true and sets the normal bit to be false. In this case, final corrected data can be generated by taking the logical product of the corrected data.

  Specifically, the integration selecting unit 12a detects an error in any of the corrected data of the parallel units 12-1 to 12-3, as illustrated in the portion surrounded by the closed curve 5 of the broken line in FIG. The bit is used as an error bit (refer to the mark “■” surrounded by a closed curve 5a with a broken line). Further, as illustrated in a portion surrounded by a broken closed curve 4, 6 or 7 in the figure, a bit detected as normal in any of the corrected data is defined as a normal bit (broken closed curves 4a, 6a). Or “□” surrounded by 7a).

  It should be noted that at least bits that are detected to be normal in each of the corrected data, such as a portion surrounded by a closed curve 4 with a broken line, are normal bits, and each bit as indicated by a portion surrounded by a closed curve 5 with a broken line As long as a bit detected as an error is an error bit in any of the corrected data, the handling of other bits is not limited.

  For example, as described above, when an error bit included in each corrected data is true and a normal bit is false, each corrected data may be logically ORed. In such a case, the bits surrounded by the dashed closed curve 6a or 7a in the figure are handled as error bits instead of normal bits.

  Further, the frequency detected as an error in each corrected data may be used. For example, the bit corresponding to the portion surrounded by the broken closed curve 6 in the figure is detected as an error once in the decoding process of the third parallel unit 12-3. In addition, the bit corresponding to the portion surrounded by the broken closed curve 7 is detected as an error twice in the decoding process of the first parallel unit 12-1 and the third parallel unit 12-3.

  At this time, if the predetermined threshold value treated as an error is set twice or more, the bit surrounded by the broken closed curve 6a in the figure is a normal bit, and the bit surrounded by the broken closed curve 7a in the figure is an error bit. Will be handled respectively.

  Further, the integration selecting unit 12a can select one optimum corrected data among the corrected data output from the parallel units 12-1 to 12-3. Such selection may be performed on the corrected data with the fewest error bits, or the corrected data with the most error bits may be used as feedback data for a new decoding process.

  Next, a processing procedure of the first decoding process executed by the receiving device 10 will be described with reference to FIG. FIG. 7 is a flowchart illustrating a processing procedure of the first decoding process executed by the receiving device 10.

  As shown in FIG. 7, when the FFT unit 11a acquires encoded data by FFT (Fast Fourier Transform) (step S101), the demapping unit 11b performs demapping of the acquired encoded data. Perform (step S102).

  Then, the Viterbi decoding unit 11c performs Viterbi decoding based on the demapped data (step S103), and the byte deinterleaving unit 11d rearranges the data rearranged in units of bytes on the transmission device side (step S104). .

  Then, the RS decoding unit 11e performs RS decoding of the rearranged data (step S105), and the decoded data (after error correction) is second decoded as error correction information together with the likelihood generated by the Viterbi decoding unit 11c. After feeding back to the unit 12 (step S106), the process is terminated.

  Next, a processing procedure of the second decoding process executed by the receiving device 10 will be described with reference to FIG. FIG. 8 is a flowchart illustrating a processing procedure of the second decoding process executed by the receiving device 10.

  As shown in FIG. 8, the second decoding unit 12 performs predetermined decoding processing in parallel for 1 to n pieces (see the portion surrounded by a broken-line rectangle in the figure). Description will be made using each processing unit and its reference provided in the first parallel unit 12-1 already shown in FIG.

  As shown in FIG. 8, the byte interleave unit 12-1a rearranges the decoded data included in the error correction information input from the first decoding unit 11 in units of bytes (step S201). Then, the likelihood adjustment unit 12-1b adjusts the likelihood included in the error correction information based on the first likelihood adjustment parameter 14-1 (step S202). Note that the likelihood adjustment parameter is individually associated with each of 1 to n parallel decoding processes.

  Subsequently, the Viterbi decoding unit 12-1c performs Viterbi decoding based on the encoded data input from the delay buffer 14a and the error correction information input from the likelihood adjustment unit 12-1b (step S203). Then, the byte deinterleave unit 12-1d rearranges the data rearranged in step S201 (step S204).

  Then, the RS decoding unit 12-1e performs RS decoding of the rearranged data, and then outputs the decoded (after error correction) data to the integration selection unit 12a (step S205).

  Subsequently, the integration selection unit 12a integrates or selects the decoded data input from 1 to n parallel decoding processes, that is, the error correction result (step S206). Then, the integration selection unit 12a outputs an output signal generated by integration or selection (step S207), and ends the process.

  As described above, in this embodiment, the first decoding unit performs the first decoding process based on the received encoded data, and each parallel unit of the second decoding unit receives the received encoded data, And based on the error correction information generated by the first decoding unit, the decoding processing is performed in parallel and individually in a plurality of systems, and the integration selection unit of the second decoding unit integrates or selects the output result of each parallel unit Thus, the receiving apparatus is configured to generate the final corrected data of the second decoding unit. Therefore, a merit according to the circuit scale can be obtained, and highly accurate error correction can be performed even in various environments.

  In the above-described embodiment, the description has been given by taking as an example a receiving apparatus that basically performs decoding using a concatenated decoding circuit in which a Viterbi decoding circuit and an RS decoding circuit are connected in series. The present invention may be applied to a receiving apparatus that uses a decoding method. In such a case, the likelihood adjusting unit is not limited to the likelihood, and it is only necessary to adjust the adjustment element according to the error correction decoding method used.

  In the above-described embodiment, the case where parallel decoding processing is arranged in the second stage has been described as an example, but such arrangement is not limited to the second stage. That is, the serial decoding process may be arranged in the first and second stages, and the parallel decoding process may be arranged in the third and subsequent stages.

  As described above, the receiving apparatus and the receiving method according to the present invention can obtain merits according to the circuit scale, and are useful when high-precision error correction is desired even in various environments. It is suitable for application to a vehicle-mounted receiving device in which the receiving environment constantly changes.

DESCRIPTION OF SYMBOLS 10 Reception apparatus 11 1st decoding part 11a FFT part 11b Demapping part 11c Viterbi decoding part 11d Byte deinterleaving part 11e RS decoding part 12 2nd decoding part 12-1 1st parallel part 12-1a Byte interleaving part 12-1b likelihood Degree adjustment unit 12-1c Viterbi decoding unit 12-1d Byte deinterleaving unit 12-1e RS decoding unit 12-2 Second parallel unit 12-3 Third parallel unit 12a Integrated selection unit 13 Third decoding unit 14 Storage unit 14- 1 first likelihood adjustment parameter 14-2 second likelihood adjustment parameter 14-3 third likelihood adjustment parameter 14a delay buffer

Claims (8)

A receiving device that performs error correction of received encoded data,
Based on the encoded data and error correction information generated by decoding the encoded data, parallel correction means for performing error correction in parallel in a plurality of systems on the received encoded data;
A receiving device comprising: adjusting means for individually adjusting the error correction information different for each system. 2. The reception according to claim 1, further comprising integration selection means for generating corrected data after error correction by integrating or selecting output results for each of the systems output by the parallel correction means. apparatus. An error correction means for correcting an error of the received encoded data before the parallel correction means,
The parallel correction means includes
The receiving apparatus according to claim 1, wherein error correction is performed based on error correction information generated by the error correction means. The integration selection means includes:
The corrected data is generated by taking a logical product of the output results for each of the systems when an error bit included in the output result is true and a normal bit is false. 4. The receiving device according to 3. The adjusting means includes
5. The error correction information of at least one of the systems is adjusted using a parameter prepared in advance so as to optimize a carrier-to-noise ratio in a non-stationary noise environment. The receiving device described in 1. The adjusting means includes
The error correction information of at least one of the systems is adjusted using parameters prepared in advance so as to optimize the carrier-to-noise ratio in a fading environment. The receiving device described. The adjusting means includes
7. The error correction information of at least one of the systems is adjusted using a parameter prepared in advance so as to optimize the carrier-to-noise ratio in a multipath environment. The receiving device described in 1. A reception method for performing error correction on received encoded data,
Based on the encoded data and error correction information generated by decoding the encoded data, a parallel correction step of performing error correction in parallel with a plurality of systems on the received encoded data;
An adjustment step of individually adjusting the error correction information that differs for each of the systems.

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