JP2012058502A - Gate signal line drive circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate signal line drive circuit improved in performance by suppressing an off current, and a display device equipped with the same.SOLUTION: A gate signal line drive circuit comprises a low voltage application switching circuit for applying low voltage on a gate signal line according to a signal low period, and a low voltage application off control circuit for applying low voltage on a switch of the low voltage application switching circuit according to a signal high period. The low voltage application off control circuit comprises an output voltage switching circuit for outputting to the switch of the low voltage application switching circuit, a low voltage application circuit for applying low voltage on an input end of the output voltage switching circuit in an off-state, and an intermediate voltage application circuit for applying intermediate voltage on the input end of the output voltage switching circuit in an on-state. According to the signal high period, the output voltage switching circuit and the low voltage application circuit are switched on.

Description

  The present invention relates to a gate signal line driving circuit and a display device including the same. In particular, the present invention relates to performance improvement of a gate signal line driving circuit and power consumption suppression.

  Conventionally, for example, in a liquid crystal display device, a shift register circuit provided in a gate signal line driving circuit that scans a gate signal line is a thin film transistor (hereinafter referred to as TFT) disposed in a pixel region of a display screen. ), That is, a shift register built-in method may be employed. Patent Documents 1 and 2 describe shift register circuits according to the prior art.

In each of a plurality of basic circuits constituting the shift register circuit provided in the gate signal line driver circuit, a gate scanning period (hereinafter referred to as a signal high level) of a gate signal line in which a gate signal is output from the basic circuit in one frame period. period and referred) only, it is outputted to the gate signal line as a high voltage gate signal G _out, the other period (hereinafter, referred to as a signal lOW period), the output low voltage to the gate signal line as a gate signal G _out Is done.

  FIG. 11 is a schematic diagram simply showing the configuration of a basic circuit of a shift register circuit according to the prior art. The basic circuit of the shift register circuit includes a low voltage application switching element SWA that outputs a low voltage to the gate signal line according to the signal low period, and a high voltage application switching that outputs a high voltage to the gate signal line according to the signal high period. An element SWG is provided.

A low voltage line _VGL is connected to an input terminal of the low voltage application switching element SWA. The low voltage application switching element SWA is turned on according to the signal low period so that the low voltage is stably output during the signal low period with respect to the corresponding gate signal line, and the low voltage that is the voltage of the low voltage line _VGL. The voltage is output as the gate signal _Gout . Further, the low voltage application switching element SWA is turned off according to the signal high period. A voltage applied to the switch of the low voltage application switching element SWA is a node N2. While the low voltage application switching element SWA is on, the node N2 is at a high voltage, and a high voltage is applied to the switch of the low voltage application switching element SWA. Further, while the low voltage application switching element SWA is turned off, the node N2 is at a low voltage, and the low voltage is applied to the switch of the low voltage application switching element SWA.

A low voltage application OFF control element SWC that supplies a low voltage is connected to the switch of the low voltage application switching element SWA, that is, to the node N2 in accordance with the signal high period. The low voltage line _VGL is connected to the input terminal of the low voltage application off control element SWC, and the low voltage application off control element SWC is turned on according to the signal high period, the node N2 becomes the low voltage, and the low voltage application A low voltage is applied to the switch of the switching element SWA. Further, the low voltage application off control element SWC is turned off according to the signal low period.

The basic clock signal CLK is connected to the input terminal of the high voltage application switching element SWG. The high voltage application switching element SWG is turned on according to the signal high period so that a high voltage is output to the corresponding gate signal line during the signal high period, and the voltage of the basic clock signal CLK is output as the gate signal _Gout. Is done. Here, the basic clock signal CLK is at a high voltage during the signal high period. Further, according to the signal low period, the high voltage application switching element SWG is turned off, and the basic clock signal CLK is cut off and not output. A voltage applied to the switch of the high voltage application switching element SWG is defined as a node N1. While the high voltage application switching element SWG is on, the node N1 is at a high voltage, and a high voltage is applied to the switch of the high voltage application switching element SWG. Further, while the high voltage application switching element SWG is turned off, the node N1 is at a low voltage, and the low voltage is applied to the switch of the high voltage application switching element SWG.

A high voltage application off control element SWB for supplying a low voltage is connected to the switch of the high voltage application switching element SWG, that is, to the node N1 according to the signal low period. The low voltage line _VGL is connected to the input terminal of the high voltage application off control element SWB, the high voltage application off control element SWB is turned on according to the signal low period, the node N1 becomes the low voltage, and the high voltage application A low voltage is applied to the switch of the switching element SWG. Further, the high voltage application off control element SWB is turned off according to the signal high period. The voltage applied to the switch of the high voltage application off control element SWB is electrically connected to the voltage applied to the switch of the low voltage application switching element SWA, and is the node N2. While the high voltage application off control element SWB is on, as described above, the node N2 is at a high voltage, and a high voltage is applied to the switch of the high voltage application off control element SWB.

FIG. 12 is a circuit diagram of a basic circuit of a shift register circuit according to the prior art. The transistor T6 provided in the low voltage application switching circuit 211 corresponds to the low voltage application switching element SWA shown in FIG. In accordance with the signal low period, the node N2 is maintained at a high voltage, and the low voltage of the low voltage line _VGL is output as the gate signal _Gn from the output terminal OUT.

Further, the transistor T5 provided in the high voltage application switching circuit 212 corresponds to the high voltage application switching element SWG shown in FIG. In response to the signal HIGH period, the node N1 becomes a high voltage, the voltage of the basic clock signal V _n which is inputted from the input terminal IN1, the output terminal OUT, and is output as a gate signal G _n.

Further, the transistor T2 provided in the node N1 low voltage supply circuit 213 corresponds to the high voltage application off control element SWB shown in FIG. The node N2 low voltage supply circuit 214 corresponds to the low voltage application off control element SWC shown in FIG. The node N2 low voltage supply circuit 214 includes two transistors T4 and T7. The input terminal IN3 is connected to the gate (switch) of the transistor T7, and the gate signal _Gn-2 output from the previous basic circuit is input to the input terminal IN3. The low voltage line _VGL is connected to the input terminal of the transistor T7, and the node N2 is connected to the output terminal. The transistor T7 is turned on according to the timing at which the voltage of the gate signal _Gn-2 changes to the high voltage, and the node N2 changes to the low voltage. Then, the transistors T2 and T6 are turned off. The node T1 is connected to the gate (switch) of the transistor T4, the low voltage line _VGL is connected to the input terminal, and the node N2 is connected to the output terminal. As the node N1 changes to the high voltage according to the signal high period, the transistor T4 is turned on and the node N2 is maintained at the low voltage.

  That is, the node N1 is maintained at a low voltage and the node N2 is maintained at a high voltage according to the signal low period, and the node N1 is changed to a high voltage and the node N2 is changed to a low voltage according to the signal high period.

JP 2007-95190 A JP 2008-122939 A

Depending on the signal low period, the low voltage of the node N1 is applied to the gate of the transistor T4, and the low voltage of the gate signal _Gn-2 is applied to the transistor T7, so that the two transistors T4 and T7 are both turned off. . While the two transistors T4 and T7 are turned off, the two transistors T4 and T7 are not completely turned off, and a small amount of current flows in each of the two transistors T4 and T7. Flowing. This is called off-current.

When an off-current flows through the two transistors T4 and T7, the node N2 falls below the high voltage. In particular, when the threshold voltage _{Vth of} either of the two transistors T4 and T7 is low, or when the shift register circuit is driven at a high temperature, the voltage drop at the node N2 becomes large. When the voltage at the node N2 drops, the two transistors T2 and T6 are not sufficiently turned on. When the transistor T6 is not sufficiently turned on, the low voltage is not stably output as the gate signal _Gn from the output terminal OUT according to the signal low period. Further, when the transistor T2 is not sufficiently turned on, the node N1 cannot be stably maintained at the low voltage according to the signal low period. As a result, the desired gate signal _Gn is not output from the output terminal OUT, and the performance as a gate signal line driving circuit is degraded.

Further, the off-state current flows through either of the two transistors T4 and T7, thereby increasing the power consumption. Furthermore, when an off-current flows through one of the two transistors T4 and T7, the charge stored in the storage capacitor C3 is discharged, and the voltage at the node N2 drops. Since the node N2 is maintained at a high voltage according to the signal low period, charges are periodically supplied from the basic clock signal Vn _{+ 4} to the storage capacitor C3 via the transistor T3, and the node N2 is set to the high voltage. Enhanced. Also at this time, the current consumption increases.

  In view of such a problem, the present invention provides a gate signal line driver circuit whose performance is improved by suppressing off-current and a display device including the gate signal line driver circuit.

  (1) In order to solve the above-described problem, the gate signal line driving circuit according to the present invention applies a high voltage to the gate signal line in the signal high period, and in the signal low period that is a period other than the signal high period. A gate signal line driving circuit for applying a low voltage to the gate signal line, a low voltage application switching circuit for applying the low voltage to the gate signal line according to the signal low period; and a signal high period And a low voltage application off control circuit that applies the low voltage to a switch of the low voltage application switching circuit so that the low voltage application switching circuit is turned off. An output voltage switching circuit having an output terminal connected to a switch of the low voltage application switching circuit, and the output voltage switching circuit A low voltage application circuit for applying the low voltage to the input terminal of the output voltage switching circuit in the on state, and a low voltage application circuit connected to the input terminal of the output voltage switching circuit in the on state; An intermediate voltage applying circuit that applies an intermediate voltage between the low voltage and the high voltage to an input terminal of the output voltage switching circuit, and the output voltage switching circuit is turned off according to the signal low period The low voltage application circuit is turned off, the intermediate voltage application circuit is turned on, the output voltage switching circuit is turned on according to the signal high period, the low voltage application circuit is turned on, and the intermediate voltage application circuit is turned on. The voltage application circuit is turned off.

  (2) In the gate signal line drive circuit according to (1), the switch of the intermediate voltage application circuit may be connected to the output terminal of the output voltage switching circuit.

  (3) In the gate signal line drive circuit according to (1) above, the intermediate voltage may be a ground voltage.

  (4) In the gate signal line drive circuit according to (1), the low voltage application circuit is connected in parallel to an input terminal of the output voltage switching circuit, and the output is in an on state, respectively. Two low voltage applying elements that apply the low voltage may be provided at an input terminal of the voltage switching circuit, and the two low voltage applying elements may be turned on according to the signal high period.

  (5) The gate signal line driving circuit according to (1), wherein the low voltage application switching circuit is connected in parallel to the gate signal line, and is placed in an ON state. A plurality of low voltage application switching elements for applying the low voltage to the signal line, and at least one of the plurality of low voltage application switching elements is turned on in accordance with the signal low period; Each may be turned on and off so that at least one is turned off in at least part of the signal low period.

  (6) The display device according to the present invention may be a display device including the gate signal line driving circuit according to any one of (1) to (5).

  According to the present invention, a gate signal line driver circuit whose performance is improved by suppressing off-state current and a display device including the gate signal line driver circuit are provided.

1 is an overall perspective view of a liquid crystal display device according to an embodiment of the present invention. It is a conceptual diagram of the equivalent circuit of the TFT substrate with which the liquid crystal display device which concerns on embodiment of this invention is equipped. 1 is a block diagram of a shift register circuit according to an embodiment of the present invention. 1 is a circuit diagram of a basic circuit of a shift register circuit according to a first embodiment of the present invention. It is a figure which shows the time change of the voltage of the input signal which concerns on the basic circuit of the shift register circuit which concerns on the 1st Embodiment of this invention, a node, and a gate signal. FIG. 6 is a circuit diagram of a basic circuit of a shift register circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram of a basic circuit of a shift register circuit according to a third embodiment of the present invention. It is a figure which shows the time change of the voltage of two pairs of alternating voltage lines which concern on the 3rd Embodiment of this invention. It is a circuit diagram which shows a part of basic circuit of the shift register circuit which concerns on the 4th Embodiment of this invention. It is a conceptual diagram of the equivalent circuit of the TFT substrate with which the liquid crystal display device which shows another example which concerns on embodiment of this invention was equipped. It is a schematic diagram which shows the structure of the basic circuit of the shift register circuit based on a prior art. It is a circuit diagram which shows an example of the basic circuit of the shift register circuit based on a prior art.

[First Embodiment]
The display device according to the first embodiment of the present invention is, for example, an IPS (In-Plane Switching) liquid crystal display device. FIG. 1 is an overall perspective view of the liquid crystal display device according to the embodiment. A TFT substrate 102 on which a gate signal line 105, a video signal line 107, a pixel electrode 110, a common electrode 111, and a TFT 109, which will be described later, are arranged, and a filter substrate 101 on which a color filter is provided opposite to the TFT substrate 102 A liquid crystal material sealed in a region sandwiched between the two substrates and a backlight 103 positioned in contact with the TFT substrate 102 on the side opposite to the filter substrate 101 side.

  FIG. 2 is a conceptual diagram of an equivalent circuit of the TFT substrate 102. In FIG. 2, on the TFT substrate 102, a large number of gate signal lines 105 connected to the gate signal line driving circuit 104 extend in the horizontal direction in the figure at equal intervals.

  The gate signal line driver circuit 104 includes a shift register control circuit 114 and a shift register circuit 112, and the shift register control circuit 114 outputs a control signal 115 to be described later to the shift register circuit 112. .

  The shift register circuit 112 includes a plurality of basic circuits 113 to be described later corresponding to the plurality of gate signal lines 105. For example, when 800 gate signal lines 105 are present, similarly, 800 basic circuits 113 are provided in the shift register circuit 112. By the control signal 115 input from the shift register control circuit 114, each basic circuit 113 becomes a high voltage during the corresponding gate scanning period (signal high period) in one frame period, and other periods (signal low period). ), A gate signal having a low voltage is output to the corresponding gate signal line 105.

  In addition, a large number of video signal lines 107 connected to the data driving circuit 106 extend in the vertical direction in the figure at equal intervals. The gate signal lines 105 and the video signal lines 107 divide pixel areas arranged in a grid pattern. Further, a common signal line 108 extends in the horizontal direction in the drawing in parallel with each gate signal line 105.

  TFTs 109 are formed at the corners of each pixel region defined by the gate signal line 105 and the video signal line 107 and are connected to the video signal line 107 and the pixel electrode 110. The gate electrode of the TFT 109 is connected to the gate signal line 105. In each pixel region, a common electrode 111 is formed facing the pixel electrode 110.

  In FIG. 2, the gate signal line drive circuit 104 and the data drive circuit 106 are shown as separate circuits, but the gate signal line drive circuit 104 and the data drive circuit 106 are integrated on a single chip. It may be a driver IC.

  In the above circuit configuration, the reference voltage is applied to the common electrode 111 of each pixel circuit via the common signal line 108. Further, a gate voltage is selectively applied to the gate electrode of the TFT 109 by the gate signal line 105, whereby the current flowing through the TFT 109 is controlled. The voltage of the video signal supplied to the video signal line 107 is selectively applied to the pixel electrode 110 through the TFT 109 in which the gate voltage is selectively applied to the gate electrode. As a result, a potential difference is generated between the pixel electrode 110 and the common electrode 111 to control the orientation of liquid crystal molecules, thereby controlling the degree of shielding light from the backlight 103 and displaying an image. Become.

  In FIG. 2, the shift register circuit 112 is shown only on the left side of FIG. 2 for the sake of simplicity, but in reality, the basic circuit 113 of the shift register circuit 112 is provided on both the left and right sides of the display area. For example, if there are 800 gate signal lines 105, the plurality of basic circuits 113 arranged on both sides, for example, the right basic circuit 113 is an odd-numbered signal line and the left basic circuit 113 is an even number. A gate signal is supplied to each of the second signal lines.

  FIG. 3 is a block diagram of the shift register circuit 112. Among the plurality of basic circuits 113 provided in the shift register circuit 112, the odd-numbered basic circuit 113 is arranged on the right side of FIG. 3, and the even-numbered basic circuit 113 is arranged on the left side of FIG. A gate signal is output to the display area 120 located in the center of FIG. In FIG. 3, the nth basic circuit is indicated as a basic circuit 113-n.

A control signal 115 output from the shift register control circuit 114 to the shift register circuit 112 is supplied to an odd-numbered basic circuit 113 located on the right side of FIG. 3 and an even-numbered basic circuit 113 located on the left side of FIG. Entered. Four-phase basic clock signals V _n , V _{n + 2} , V _{n + 4} , V _{n + 6} , a high voltage line V _GH , a low voltage line V _GL , an auxiliary signal V _ST1, etc. are input to the odd-numbered basic circuit 113. The Similarly, four-phase basic clock signals V _{n + 1} , V _{n + 3} , V _{n + 5} , V _{n + 7} , high voltage line V _GH , low voltage line V _GL , auxiliary signal V _ST2, etc. Is entered.

Each of the basic circuits 113 shown in FIG. 3 includes five input terminals IN1, IN2, IN3, IN4, IN5 and one output terminal OUT as shown in the basic circuit 113-1, and A high voltage line V _GH and a low voltage line V _GL are connected to each other.

The input terminals IN1 and IN2 of the nth basic circuit 113-n will be described. In the n-th basic circuit 113-n, the basic clock signals V _n and V _{n + 4} are input to the input terminals IN1 and IN2, respectively. Here, two sets of basic clock signals composed of four phases are connected, and even when the value of n is changed, V _{n + 8} = V _n = V _n−8 may be set.

A gate signal output from the output terminal OUT of the nth basic circuit 113- _n is defined as _Gn . The gate signal G _n-2 of the (n−2) th basic circuit 113- (n−2) is applied to the input terminal IN3 of the nth basic circuit 113-n, and the (n + 4) th basic circuit is also applied to the input terminal IN4. The gate signal G _{n + 4 of} 113− (n + 4) is input. Note that the auxiliary signals V _ST1 and V _ST2 are respectively input to the input terminals IN3 of the first basic circuit 113-1 and the second basic circuit 113-2 because there is no corresponding gate signal. Similarly, the 801th dummy circuit is connected to the input terminal IN4 of the 797th basic circuit 113-797, the 798th basic circuit 113-798, the 799th basic circuit 113-799, and the 800th basic circuit 113-800. Gate signal G ₈₀₁ , the gate signal G _{802 of the 802th} dummy circuit, the gate signal G _{803 of the 803th} dummy circuit, and the gate signal G ₈₀₄ of the _804th dummy circuit are inputted, respectively. The auxiliary signal V _ST1 is input to the input terminal IN4 of the dummy circuit, and the auxiliary signal V _ST2 is input to the input terminal IN4 of the 802th and 804th dummy circuits.

Further, the auxiliary signal V _ST1 is input to the input terminal IN5 of the nth basic circuit 113-n when n is an odd number, and the auxiliary signal V _ST2 is input when n is an even number.

FIG. 4 is a circuit diagram of the nth basic circuit 113-n of the shift register circuit 112 according to this embodiment. The auxiliary signal V _ST input to the input terminal IN5 represents the auxiliary signal V _ST1 when n is an odd number and the auxiliary signal V _ST2 when n is an even number.

The main difference between the basic circuit 113 according to this embodiment and the basic circuit according to the prior art shown in FIG. 12 is the configuration of the node N2 low voltage supply circuit 14 (low voltage application off control circuit). In the node N2 low voltage supply circuit 214 shown in FIG. 12, the input terminals of the two transistors T4 and T7 are both connected to the low voltage line _VGL . On the other hand, the node N2 low voltage supply circuit 14 according to this embodiment shown in FIG. 4 is parallel to the output voltage switching circuit whose output terminal is connected to the node N2 and the input terminal of the output voltage switching circuit. And an intermediate voltage application circuit and a low voltage application circuit.

  The output voltage switching circuit includes two transistors T4 and T7 connected in parallel to the node N2. A voltage applied to the input terminal of the output voltage switching circuit, that is, the input terminal of the transistors T4 and T7 is defined as a node N4. The intermediate voltage application circuit includes a transistor TL1, and the low voltage application circuit includes a transistor TL2.

The input terminal IN3 is connected to the gate (switch) of the transistor T7, and the gate signal G _{n−2 of the} (n−2) th basic circuit 113- (n−2) is input to the input terminal IN3. The input terminal of the transistor TL1 is connected to the intermediate voltage line, the output terminal is connected to the node N4, and the gate is connected to the node N2. The input terminal is at a low voltage line V _GL transistor TL2, output to the node N4, a gate to the node N1, are connected.

Here, the voltage of the intermediate voltage line is an intermediate voltage that is a voltage between the high voltage of the high voltage line _VGH and the low voltage of the low voltage line _VGL . In particular, the intermediate voltage is preferably the ground voltage GND. In FIG. 4, the voltage of the intermediate voltage line is shown as the ground voltage GND.

  12, in the basic circuit 113 according to the embodiment shown in FIG. 4, the transistor T6 provided in the low voltage application switching circuit 11 includes the low voltage application shown in FIG. 11. This corresponds to the switching element SWA. The transistor T5 provided in the high voltage application switching circuit 12 corresponds to the high voltage application switching element SWG shown in FIG. The transistor T2 provided in the node N1 low voltage supply circuit 13 (high voltage application off control circuit) corresponds to the high voltage application off control element SWB shown in FIG. The node N2 low voltage supply circuit 14 corresponds to the low voltage application off control element SWC shown in FIG.

  FIG. 5 shows temporal changes of the nodes N1, N2, and N4 of the nth basic circuit 113-n according to this embodiment, together with the basic clock signal that is the input signal and the gate signal of the neighboring basic circuit. Is. For node N2, the high voltage is shown as H and the low voltage as L. Similarly, for the node N4, the intermediate voltage is indicated as GND, and the low voltage is indicated as L.

Hereinafter, the driving method of the basic circuit 113 will be described along with the time change of each signal shown in FIG. Depending on the signal low period, the node N1 is maintained at a low voltage and the node N2 is maintained at a high voltage. The high voltage of the node N2 is applied to the gate of the transistor TL1, and the transistor TL1 is maintained in the on state. While the transistor TL1 is in the on state, the node N4 is electrically connected to the intermediate voltage line, and the ground voltage GND of the intermediate voltage line is applied to the node N4. That is, node N4 is maintained at ground voltage GND. Further, the low voltage of the node N1 is applied to the gate of the transistor TL2, and the transistor TL2 is maintained in the off state. At this time, the gate signal G _n−2 of the (n−2) th basic circuit 113- (n−2) applied to the gate of the transistor T7 is a low voltage, and the transistor T7 is maintained in the off state. The low voltage of the node N1 is applied to the gate of the transistor T4, and the transistor T4 is maintained in the off state.

Since the node N2 is maintained at the high voltage, the two transistors T2 and T6 are maintained in the ON state, respectively. By maintaining the transistor T6 in the on state, the low voltage is output as the gate signal _Gn from the output terminal OUT. By maintaining the transistor T2 in the on state, the node N1 is maintained at a low voltage. By maintaining the node N1 at the low voltage, the transistor T5 is maintained in the off state.

  The transistor T1 has a diode connection in which the gate and the input end are connected. An input terminal IN3 is connected to the gate and input terminal of the transistor T1. A node N1 is connected to the output terminal of the transistor T1.

A period P1 shown in FIG. 5, the gate signal _{G n-2} of the (n-2) th basic circuit 113- (n-2) becomes high voltage, the period P1, the transistors T1, T7 is turned on. When the transistor T7 is turned on, the node N2 is electrically connected to the node N4, and the node N2 changes to the ground voltage GND of the node N4. Further, when the transistor T1 is turned on, the node N1 is electrically connected to the high voltage of the gate signal _Gn-2 , and the node N1 changes to the high voltage. In response to the timing when the node N1 becomes a high voltage, the transistor T4 is turned on, and the transistor T4 further accelerates the change of the node N2 to the ground voltage GND.

The node N2 is connected to the gate of the transistor TL1, and the transistor TL1 is turned off in accordance with the timing at which the node N2 changes to the ground voltage GND. Further, the node N1 is connected to the gate of the transistor TL2, and the transistor TL2 is turned on according to the timing at which the node N1 changes to the high voltage. Transistor TL2 is by the ON state, the node N4 is low voltage electrically connected to the low voltage line V _GL, the node N4 is changed to the low voltage. As the node N4 changes to the low voltage, the node N2 changes to the low voltage via the two transistors T4 and T7. Therefore, as shown in FIG. 5, in the period P1, the node N1 changes to a high voltage, and the nodes N2 and N4 change to a low voltage.

The transistors T2 and T6 are turned off according to the timing at which the node N2 changes to the low voltage. By turning off the transistor T6, the output terminal OUT is electrically disconnected from the low voltage line _VGL . By turning off the transistor T2, the node N1 is electrically disconnected from the low voltage line _VGL . The transistor T5 is turned on according to the timing at which the node N1 changes to the high voltage. When the transistor T5 is turned on, the basic clock signal V _n which is input to the input terminal IN1 is output from the output terminal OUT.

In the period P2 shown in FIG. 5, the gate signal G _n−2 of the (n−2) th basic circuit 113- (n−2) becomes a low voltage, and the transistors T1 and T7 are turned off. Even after the transistor T1 is turned off, the node N1 is maintained at the high voltage, and the transistor T5 is maintained in the on state. In the period P2, since the basic clock signal V _n at the high voltage, the period P2 is a signal HIGH period, the output terminal OUT, and the gate signal G _n of the high voltage is output.

Even after the transistor T7 is turned off, the node N1 is maintained at the high voltage, and the two transistors T4 and TL2 are both maintained in the on state. Through the two transistors T4, TL2, the node N2 is connected to the low voltage line V _GL and electrically, the node N2 is maintained at the low voltage.

Here, in reality, since the threshold voltage V _th exists in the transistor T1, the node N1 subtracts the threshold voltage V _th of the transistor T1 from the high voltage of the gate signal G _n−2 in the period P1. It becomes a voltage. At this voltage, the transistor T5 may not be sufficiently turned on in the period P2 that is the signal high period. Therefore, the boost capacitor C1 is connected in parallel to the transistor T5 in the high voltage application switching circuit 12. ing. In the period P2, the gate signal G _n−2 changes to the low voltage and the transistor T1 is turned off, but the node N1 is maintained at the high voltage and the transistor T5 is maintained in the on state. During the period P2, the output terminal OUT, and the high voltage of the basic clock signal V _n which is inputted to the input terminal IN1 is applied, due to capacitive coupling of the boosting capacitor C1, node N1 is further boosted to a high voltage. This is called the bootstrap voltage. In the period P2, as shown in FIG. 5, the node N1 has a bootstrap voltage higher than the high voltage.

A period P3 shown in FIG. 5, the basic clock signal _{V n} is changed to the OFF voltage, the boosting capacitor C1, node N1 is maintained at a high voltage, three transistors T5, T4, TL2 are both in the on state Maintained. Therefore, even in the period P3, the basic clock signal V _n is output from the output terminal OUT, and the node N2 is maintained at the low voltage, the two transistors T2, T6 are both maintained in the OFF state.

As shown in FIG. 4, the low voltage line V _GL to an input terminal of the transistor T9 is, the node N1 to the output terminal, the input terminal IN4 to the gate are connected respectively. The gate signal G _{n + 4 of the} (n + 4) th basic circuit 113- (n + 4) is input to the input terminal IN4.

As shown in FIG. 5, the period P4, the gate signal G _{n + 4} becomes high voltage, the period P4, the transistor T9 is turned on, the low voltage of the low voltage line V _GL is applied to the node N1. The three transistors T5, T4, and TL2 are turned off according to the timing at which the node N1 changes to the low voltage.

As shown in FIG. 4, a storage capacitor C3 and a transistor T3 are connected in series between the low voltage line _VGL and the high voltage line _VGH . The output terminal of the transistor T3 and the positive electrode of the storage capacitor C3 are connected to the node N2. Moreover, the low voltage line V _GL is connected to the negative electrode of the C3 of the holding capacity, high voltage line V _GH to the input terminal of the transistor T3 is connected, respectively. The input terminal IN2 is connected to the gate of the transistor T3, and the basic clock signal Vn _{+ 4} is input to the input terminal IN2.

As shown in FIG. 5, since the basic clock signal V _{n + 4} becomes a high voltage during the period P4, the transistor T3 is turned on and the node N2 changes to the high voltage during the period P4. At the same time, the storage capacitor C3 is charged to a high voltage. In response to the timing when the node N2 changes to the high voltage, the transistor TL1 is turned on, and the node N4 changes to the ground voltage GND of the intermediate voltage line.

  In the periods P1, P2, and P3, the node N1 is maintained at a high voltage, the node N2 is maintained at a low voltage, and the node N4 is maintained at a low voltage. In the period P4, the node N1 is maintained at a low voltage, and the node N2 is maintained at a high voltage. In addition, the node N4 changes to an intermediate voltage.

After that, in the period P5, the basic clock signal V _{n + 4} becomes a low voltage, and the voltage of the node N2 is maintained at a high voltage by the storage capacitor C3 even after the transistor T3 is turned off. Furthermore, since the basic clock signal V _{n + 4} periodically becomes a high voltage and the storage capacitor C3 is periodically charged, the voltage of the node N2 is stably maintained at the high voltage. Therefore, also after the period P5, the node N1 is maintained at the low voltage, the node N2 is maintained at the high voltage, and the node N4 is maintained at the intermediate voltage.

Further, similarly to the basic circuit according to the related art shown in FIG. 12, the nth basic circuit 113-n shown in FIG. 4 includes a transistor T10 in parallel with the transistor T3. The gate of the transistor T10, the input terminal IN5 are connected, an auxiliary signal _{V ST} described above is input to the input terminal IN5. In addition to continuing to periodically charge the storage capacitor C3 by periodically turning on the transistor T3, the transistor T10 is turned on every time the auxiliary signal _VST becomes a high voltage. C3 is charged.

Here, as described above, the auxiliary signal V _ST represents the auxiliary signal V _ST1 when n is an odd number and the auxiliary signal V _ST2 when n is an even number. Therefore, the n-th basic circuit 113-n in which n is an odd number is the timing at which the auxiliary signal V _ST1 becomes a high voltage, and the n-th basic circuit 113-n in which n is an even number is the auxiliary signal V _ST2. The storage capacitor C3 is charged by the T10 provided in each of the basic circuits 113 at the same time when becomes a high voltage. By setting the auxiliary signal _VST to a high voltage in a blanking period that is a time other than a period in which data is written in the display region in one frame period, the node N2 is more stably set to a high voltage according to the signal off period. Can be maintained.

The above is the description of the configuration and the driving method of the nth basic circuit 113-n according to the embodiment. In the basic circuit according to the prior art shown in FIG. 12 and the nth basic circuit 113-n according to the embodiment shown in FIG. 4, the two transistors T4 and T7 are turned off according to the signal low period. Yes. In the basic circuit according to the prior art shown in FIG. 12, while the two transistors T4 and T7 are maintained in the off state, the low voltage of the low voltage line _VGL is applied to the input terminals of the two transistors T4 and T7. The high voltage of the node N2 is applied to the output terminal. That is, a potential difference between the high voltage and the low voltage is applied between the input terminal and the output terminal of each of the two transistors T4 and T7. On the other hand, in the n-th basic circuit 113-n according to the present embodiment, while the two transistors T4 and T7 are maintained in the off state, the input terminals of the two transistors T4 and T7 are connected to a node. The ground voltage GND of N4 is applied, and the high voltage of the node N2 is applied to the output terminal. That is, a potential difference between the high voltage and the ground voltage GND is applied between the input terminal and the output terminal of each of the two transistors T4 and T7. Compared with the basic circuit according to the prior art, the input terminal and The voltage applied between the output terminals is reduced.

  By reducing the voltage applied between the input terminal and the output terminal of each of the two transistors T4 and T7, the two transistors T4 and T7 are turned off according to the signal low period. The flowing off current is suppressed. By suppressing the off-current, the node N2 is prevented from being lowered from the high voltage, and the node N2 is more stably maintained at the high voltage. As a result, the performance as a gate line driving circuit is improved.

  Further, the power consumption is suppressed by suppressing the off-current flowing through the two transistors T4 and T7. Further, since the off-current flowing through the two transistors T4 and T7 is suppressed, the discharge of the charge stored in the storage capacitor C3 due to the off-current is suppressed, and the consumption for maintaining the node N2 at a high voltage. Electric power is also suppressed. In particular, by setting the intermediate voltage to the ground voltage GND, even when an off-current flows through the two transistors T4 and T7, a power source necessary for maintaining the intermediate voltage is not required, so that power consumption is further increased. It is suppressed.

In the basic circuit according to the prior art shown in FIG. 12, when the transistor T7 is turned on according to the signal high period, a current flows from the high voltage at the node N2 to the low voltage on the low voltage line _VGL . At that time, in order to maintain the low voltage line _VGL at a low voltage, the power supply of the low voltage line _VGL consumes power. On the other hand, in the n-th basic circuit 113-n according to this embodiment shown in FIG. 4, the node N4 connected to the input terminal of the transistor T7 is maintained at the intermediate voltage, and corresponds to the signal low period. Thus, the transistor T7 is turned on, and a current flows from the node N2 to the intermediate voltage line. In particular, when the intermediate voltage is set to the ground voltage GND, when this current flows, a power source necessary for maintaining the intermediate voltage is not required, so that power consumption is further suppressed.

Further, in the two transistors T4 and T7 according to this embodiment, the positive shift of the threshold voltage _Vth is suppressed. In accordance with the signal high period, the two transistors T4 and T7 are turned on. While the two transistors T4 and T7 are turned on, a high voltage is applied to the gate and a low voltage is applied to the input terminal and the output terminal. Therefore, the threshold voltage _Vth shifts to the positive side. That is, the threshold voltage _Vth is positively shifted. In particular, in the transistor T4, the threshold voltage _Vth is positively shifted during the periods P1, P2, and P3. On the other hand, according to the signal low period, the two transistors T4 and T7 are turned off, and while the two transistors T4 and T7 are turned off, a low voltage is applied to the gate, and the threshold voltage V _th Shifts to the negative side. That is, the threshold voltage _Vth is negatively shifted.

In the basic circuit according to the prior art shown in FIG. 12, while the two transistors T4 and T7 are turned off, the node N2 which is a high voltage is applied to the output terminals of the two transistors T4 and T7, and the input terminal The low voltage of the low voltage line V _GL is applied to. On the other hand, in the n-th basic circuit 113-n according to the embodiment shown in FIG. 4, the two transistors T4 and T7 are turned off while the two transistors T4 and T7 are turned off. Similarly, a node N2 that is a high voltage is applied, and an intermediate voltage that is higher than the low voltage is applied to the input terminal, unlike the case of the related art. When a voltage higher than the low voltage of the node N1 applied to the gate is applied to the input terminals of the transistors T4 and T7, the negative shift of the threshold voltage _Vth becomes larger, and the two transistors T4 and T7 are turned on. more counteract the positive shift in the threshold voltage V _th generated between being, as a whole, the two transistors T4, T7 threshold voltage V _th of the positive shift in can be suppressed.

In the two transistors T4 and T7, the positive shift of the respective threshold voltages _Vth is suppressed, so that the driving capability as the elements of the two transistors T4 and T7 is improved, and the node N2 is more stably transferred to the node N2. A voltage can be supplied. As a result, the performance of the gate line driving circuit is further improved.

  As described above, the transistor T1 is diode-connected. Since the transistor T1 is diode-connected, the off-current flowing through the transistor T1 is suppressed while the transistor T1 is turned off. While the transistor T1 is turned off, a low voltage is applied to the gate and input terminal of the transistor T1. Depending on the signal low period, the node N1 is maintained at a low voltage. That is, according to the signal low period, a low voltage is applied to both the input terminal and the output terminal of the transistor T1, almost no potential difference is generated between the input terminal and the output terminal, and the off current flows almost. Absent. By suppressing the off-current flowing through the transistor T1, the node N1 is stably maintained at a low voltage according to the signal off period. As a result, the performance of the gate line driving circuit is further improved.

  Even if the off-state current flows through either of the two transistors T4 and T7 while the two transistors T4 and T7 are turned off, unlike the basic circuit according to the prior art shown in FIG. Node N2 only drops to an intermediate voltage. Therefore, even when off-state current flows, the node N2 is maintained at a higher voltage, and the transistors T2 and T6 can be more controlled.

  The n-th basic circuit 113-n according to this embodiment shown in FIG. 4 includes a storage capacitor C3 in order to maintain the node N2 at a high voltage according to the signal low period. According to the present invention, the off-current flowing through the two transistors T4 and T7 is suppressed, and the node N2 is stably maintained. Therefore, the size of the storage capacitor C3 can be reduced. Similarly, since the off-current flowing through the two transistors T4 and T7 is suppressed, the transistors T3 and T10 provided for changing the node N2 to the high voltage according to the signal high period do not need high performance. The size of the transistors T3 and T10 can be reduced. Thereby, space saving of the gate line driving circuit is realized. When the gate line driving circuit is provided in the frame area of the display screen, narrowing of the frame is realized.

[Second Embodiment]
The display device according to the second embodiment of the present invention has basically the same configuration as the display device according to the first embodiment. The main difference from the display device according to the first embodiment is the configuration of the node N2 low voltage supply circuit 14 (low voltage application off control circuit) provided in the basic circuit 113 of the shift register circuit 112.

  FIG. 6 is a circuit diagram of the nth basic circuit 113-n of the shift register circuit 112 according to this embodiment. The node N2 low voltage supply circuit 14 according to this embodiment shown in FIG. 6 has an output terminal connected to the node N2, similarly to the node N2 low voltage supply circuit 14 according to the first embodiment shown in FIG. An output voltage switching circuit; and an intermediate voltage application circuit and a low voltage application circuit connected in parallel to an input terminal of the output voltage switching circuit.

The output voltage switching circuit includes two transistors T4 and T7 connected in parallel to the node N2. The voltage applied to the input terminal of the output voltage switching circuit is the node N4. The intermediate voltage application circuit includes a transistor TL1. Unlike the first embodiment shown in FIG. 4, the low voltage application circuit includes two transistors TL2 and TL3 connected in parallel to the node N4. The input terminal IN3 is connected to the gate (switch) of the transistor TL3, and the low voltage line _VGL is connected to the output terminal. The driving method of the nth basic circuit 113-n according to this embodiment is the same as the driving method according to the first embodiment shown in FIG.

In the period P1 shown in FIG. 5, the gate signal G _n-2 of the (n−2) th basic circuit 113- (n−2) becomes a high voltage, and in the period P1, the transistors T1 and T7 are turned on. TL3 is also turned on. When the transistor T7 is turned on, the node N2 is electrically connected to the node N4, and the node N2 changes to the voltage of the node N4. At this time, since the transistor TL3 is turned on, the node N4 is electrically connected to the low voltage of the low voltage line _VGL , and the node N4 changes from the ground voltage GND to the low voltage, so that the first embodiment Compared with, the node N2 changes to the low voltage more quickly. This is because the transistor TL3 is turned on prior to the timing when the transistor TL2 is turned on, so that the node N4 changes from the ground voltage GND to the low voltage more quickly. Further, after the transistor TL2 is turned on, the two transistors TL2 and TL3 that are parallel to the node N4 change the node N4 to the low voltage, so that the one transistor TL2 changes the first embodiment. In addition, the node N4 changes to the low voltage more rapidly. As a result, the node N2 changes to the low voltage more quickly. As a result, the performance of the gate line driving circuit is further improved.

[Third embodiment]
The display device according to the third embodiment of the present invention has basically the same configuration as the display device according to the second embodiment. The main difference from the display device according to the second embodiment is the configuration of the basic circuit 113 of the shift register circuit 112.

  FIG. 7 is a circuit diagram of the nth basic circuit 113-n of the shift register circuit 112 according to this embodiment. A main difference from the nth basic circuit 113-n according to the second embodiment shown in FIG. 6 is that in the basic circuit 113 according to the second embodiment, the low voltage application switching circuit 11 includes a low voltage. When one transistor T6 corresponding to the application switching element SWA is provided, the basic circuit 113 according to the present embodiment includes two transistors T6 and T6A connected in parallel to the low voltage application switching circuit 11. Is provided. Similarly, the node N1 low voltage supply circuit 13 (high voltage application off control circuit) according to the second embodiment includes one transistor T2 corresponding to the high voltage application off control element SWB. The node N1 low voltage supply circuit 13 (high voltage application off control circuit) according to the embodiment includes two transistors T2 and T2A connected in parallel.

Further, two pairs of AC voltage lines are further input to the nth basic circuit 113-n shown in FIG. Node N2 via the transistor TA1, TA2, TA3, TA4 to be controlled switching element, a pair of AC voltage line _{V GL_AC1,} is connected to the _{V GL_AC1B.} The input terminals of the transistors T2 and T2A are connected to another pair of AC voltage lines _{VGL_AC2} and _{VGL_AC2B,} respectively, and the output terminals of the transistors T2 and T2A are both connected to the node N1. Similarly, the input ends of the transistors T6 and T6A are connected to the pair of AC voltage lines _{VGL_AC2} and _{VGL_AC2B,} respectively, and the output ends of the transistors T6 and T6A are both connected to the output terminal OUT.

A pair of AC voltage lines _{VGL_AC1} and _{VGL_AC1B} are connected to the gates of the transistors TA1 and TA3, respectively. The node N2 is connected to nodes N2A and N2B via transistors TA1 and TA3 serving as control switching elements, respectively.

Similarly, a pair of AC voltage lines _{VGL_AC1} and _{VGL_AC1B} are connected to the gates of the transistors TA4 and TA2, respectively. Via the transistor TA2, AC voltage line _{V GL_AC1} and node N2A is, also, through the transistor TA4, the AC voltage line _{V GL_AC1B} and node N2B, are connected.

  Nodes N2A and N2B are connected to the gates of the transistors T2 and T2A, respectively. Similarly, nodes N2A and N2B are connected to the gates of the transistors T6 and T6A, respectively.

  FIG. 8 is a diagram showing a time change of voltages of two pairs of AC voltage lines. The horizontal axis direction represents time, and the vertical axis direction represents the high voltage (H) and the low voltage (L) of each of the two pairs of AC voltage lines. As shown in the figure, the voltages of the two pairs of AC voltage lines periodically change so as to alternately become a high voltage and a low voltage.

As shown in FIG. 8, the respective periods of the AC voltage line _{V GL_AC1, P1A, P2A, P3A} , and ..., and each period of the AC voltage line _{V GL_AC1B, P1B, P2B, P3B} , ··· And the times shown in the figure are defined as t ₁ and t ₂ , respectively. As shown in FIG. 8, the pair of AC voltage lines V _{GL_AC1} and V _{GL_AC1B} both have a longer period during which the high voltage is applied than a period during which the low voltage is applied. For example, the AC voltage line _{V GL_AC1,} high voltage and is the period P1A, P3A, ... the period is low voltage P2A, P4A, than ..., is longer. Then, a pair of AC voltage line _{V GL_AC2, V GL_AC2B,} respectively, a pair of AC voltage line _{V GL_AC1,} are opposite phases of _{V GL_AC1B.}

Thus, for example, AC voltage line _{V GL_AC1B} is low voltage in the period P1B, at time _{t 1,} changes to high voltage. Thereafter, the AC voltage line _{V GL_AC1} is high voltage in the period P1A is the time _{t 2, the} changes to the low voltage. That is, each of the pair of AC voltage lines V _{GL_AC1} and V _{GL_AC1B} changes from the low voltage to the high voltage for a while and changes from the high voltage to the low voltage in each period of the high voltage. There is an overlap period in which both the pair of AC voltage lines V _{GL_AC1} and V _{GL_AC1B} are at a high voltage for a short period of time immediately before.

Hereinafter, changes in the nodes N2A and N2B will be described in accordance with the time changes shown in FIG. In the period P1B, since the AC voltage line V _{GL_AC1} is a high voltage, the transistor TA1 is turned on, and since the AC voltage line V _{GL_AC1B} is a low voltage, the transistor TA2 is turned off, and the node N2A is connected to the node N2. Electrically connected. In the period P1B, since the AC voltage line V _{GL_AC1} is a high voltage, the transistor TA4 is turned on, and since the AC voltage line V _{GL_AC1B} is a low voltage, the transistor TA3 is turned off and the node N2B is low It is kept at voltage.

At the time _{t 1,} AC voltage line _{V GL_AC1B} to a high voltage from a low voltage, to change. Thus, the transistor TA3 is turned on, and the node N2B is electrically connected to the node N2. Moreover, by the AC voltage line _{V GL_AC1B} has changed to the high voltage, through a transistor TA4 is in the ON state, the node N2B is changed from the low voltage to high voltage. Due to these two points, the node N2B also changes to the same high voltage as the node N2. At this time, the node N2 is electrically connected to both the node N2A and the node N2B.

To time _{t 2, the} AC voltage line _{V GL_AC1} is in the low voltage from the high voltage, to change. Thereby, the transistor TA1 is turned off, and the node N2A is electrically disconnected from the node N2. Further, when the AC voltage line _{VGL_AC1} changes to the low voltage, N2A changes from the high voltage to the low voltage through the transistor TA2 that is in the on state.

As described above, when the AC voltage line _{VGL_AC1} is at a high voltage, the node N2A is electrically connected to the node N2, and becomes a high voltage according to the signal low period, so that the transistors T2 and T6 are turned on. . At this time, the AC voltage line _{V GL_AC1} opposite phase as going on AC voltage line _{V GL_AC2} is low voltage, the transistors T2, T6, respectively, to the node N1 and the output terminal OUT, and the low voltage of the AC voltage line _{V GL_AC2} Is applied. When the AC voltage line _{VGL_AC1} is at a low voltage, the node N2A is electrically disconnected from the node N2, the node N2A is at a low voltage, and the transistors T2 and T6 are turned off.

Similarly, when the AC voltage line _{V GL_AC1B} is high voltage, the node N2B are electrically connected to the node N2, at the high voltage in response to a signal LOW period, the transistors T2A, T6A are turned on. At this time, the AC voltage line _{V GL_AC2B} that is the AC voltage line _{V GL_AC1B} opposite phase is low voltage, the transistors T2A, T6A, respectively, to the node N1 and the output terminal OUT, and the AC voltage line _{V GL_AC2B} low voltage Is applied. Further, when the AC voltage line _{V GL_AC1B} is low voltage, the node N2B is interrupted in the node N2 electrically, node N2B becomes a low voltage, the transistors T2A, T6A are turned off.

Control switching device become transistors TA1, TA2, TA3, TA4, and the AC voltage line _{V GL_AC1,} the _{V GL_AC1B,} node N2A and the node N2B is, whether connected to the node N2 electrically is controlled. When the node N2A is electrically disconnected from the node N2, when the node N2A, which has been maintained at the low voltage, is electrically connected to the node N2, the node N2A is controlled to change from the low voltage to the high voltage. Therefore, it is possible to suppress a decrease in the voltage of the node N2 that occurs when the node N2 electrically connected to the node N2B is further electrically connected to the node N2A. The same applies when the node N2B is electrically connected to the node N2.

  Thus, by providing the low voltage application switching circuit 11 and the node N1 low voltage supply circuit 13 with a plurality of transistors, a high voltage was originally applied to the gate of one transistor for a long time. The time during which a high voltage is applied to the gate of one transistor can be assigned to each of the plurality of transistors. As a result, the time required for deterioration of the switching element can be delayed, and a longer life can be realized.

  Further, in the basic circuit 113 according to the present embodiment, it is possible to suppress a decrease in the node N2 that occurs at the time of switching the driving of the plurality of transistors. In such a basic circuit 113, the node N2 low voltage according to the present invention is suppressed. By providing the supply circuit 14, the effect of stabilizing the voltage at the node N2 is further enhanced. As a result, the performance of the gate line driving circuit is further improved. As the node N2 low voltage supply circuit 14 according to the present embodiment, FIG. 7 shows the same circuit as the node N2 low voltage supply circuit 14 according to the second embodiment shown in FIG. However, the present invention is not limited to this, and any node N2 low voltage supply circuit 14 according to the present invention such as the node N2 low voltage supply circuit 14 according to the first embodiment shown in FIG. 4 may be used.

  As described above, in the basic circuit 113 according to the present embodiment, the case where two switching elements are connected in parallel to the low voltage application switching circuit 11 and the node N1 low voltage supply circuit 13 has been described. However, it is not necessary that two switching elements are connected in parallel with each other, and only one of the low voltage application switching circuit 11 and the node N1 low voltage supply circuit 13 may be provided with two switching elements. . Although the basic clock signal has four phases here, it can be applied to five or more basic clock signals.

  Further, in the basic circuit 113 shown in FIG. 7, each of the low voltage application switching circuit 11 and the node N1 low voltage supply circuit 13 includes two transistors in parallel. However, the number of transistors is limited to two. Absent. The number may be further increased to three or four. In this case, the number of AC voltage lines connected to each node is increased by 3 and 4 pairs of AC voltage lines. The time during which the high voltage is applied to the transistors is shared by more transistors, and the time during which the high voltage is applied to each transistor can be further reduced.

[Fourth Embodiment]
The display device according to the fourth embodiment of the present invention has basically the same configuration as the display device according to any one of the first to third embodiments. The main difference from the display device according to any one of the first to third embodiments is the structure of the transistor T1 provided in the basic circuit 113 of the shift register circuit 112.

FIG. 9 is a circuit diagram showing a part of the nth basic circuit 113-n of the shift register circuit 112 according to this embodiment. The transistor T1 according to the first to third embodiments shown in FIGS. 4, 6, and 7 is diode-connected, and the gate and input terminal of the transistor T1 are connected to the input terminal IN3. On the other hand, the gate of the transistor T5 according to this embodiment shown in FIG. 9 is connected to the input terminal IN3, and the input terminal is connected to the high voltage line _VGH .

Since the transistor T1 has the structure shown in FIG. 9, when the transistor T1 is turned on in the period P1, the node N1 that has been maintained at the low voltage changes more quickly to the high voltage. This is because the high voltage of the high voltage line _VGH is applied to the input terminal of the transistor T1.

  As described above, in the shift register circuit 112 according to the embodiment of the present invention, as shown in FIG. 3, the case where a plurality of basic circuits 113 are arranged on both sides of the display area 120 has been described. Needless to say, the present invention is applied to the case of being arranged on one side of the case or in other cases.

  Further, in the display device according to the embodiment of the present invention, the IPS liquid crystal display device shown in FIG. 2 has been described. However, the display device according to the present invention may be a VA (Vertical Aligned) method or a TN (Twisted) method. It may be a liquid crystal display device of another driving method such as a Nematic method, or may be another display device such as an organic EL display device. FIG. 10 is a conceptual diagram of an equivalent circuit of the TFT substrate 102 provided in the VA mode and TN mode liquid crystal display devices. In the VA mode and TN mode liquid crystal display devices, a common electrode 111 is provided on a filter substrate 101 facing the TFT substrate 102.

11 low voltage application switching circuit, 12 high voltage application switching circuit, 13 node N1 low voltage supply circuit, 14 node N2 low voltage supply circuit, 15 node N1 high voltage supply circuit, 101 filter substrate, 102 TFT substrate, 103 backlight, 104 gate signal line drive circuit, 105 gate signal line, 106 data drive circuit, 107 video signal line, 108 common signal line, 109 TFT, 110 pixel electrode, 111 common electrode, 112 shift register circuit, 113 basic circuit, 114 shift register Control circuit, 115 control signal, 120 display area, 211 low voltage application switching circuit, 212 high voltage application switching circuit, 213 node N1 low voltage supply circuit, 214 node N2 low voltage supply circuit, C1 boosting capacity, C3 holding capacity CLK basic clock _{signal, G n,} G _out gate signal, IN1, IN2, IN3, IN4 , IN5 input terminals, N1, N2, N2A, N2B , N4 nodes, OUT an output terminal, SWA LOW voltage applying switching element, SWB high voltage Application OFF control element, SWC Low voltage application OFF control element, SWG High voltage application switching element, TA1, TA2, TA3, TA4, T1, T2, T2A, T4, T5, T6, T6A, T9, T10, TL1, TL2, TL3 _{transistor, V GH} high voltage _{line, V GL} low voltage _{line, V GL_AC1, V GL_AC1B, V} GL_AC2, V GL_AC2B AC voltage line, _{V n} basic clock _{signal, V ST, V ST1, V} ST2 auxiliary signal.

Claims (6)

A gate signal line driving circuit that applies a high voltage to the gate signal line during a signal high period and applies a low voltage to the gate signal line during a signal low period that is a period other than the signal high period;
A low voltage application switching circuit for applying the low voltage to the gate signal line according to the signal low period;
A low voltage application off control circuit that applies the low voltage to a switch of the low voltage application switching circuit so that the low voltage application switching circuit is turned off according to the signal high period,
The low voltage application off control circuit includes:
An output voltage switching circuit having an output terminal connected to the switch of the low voltage application switching circuit;
A low voltage application circuit that is connected to an input terminal of the output voltage switching circuit and applies the low voltage to an input terminal of the output voltage switching circuit in an ON state;
An intermediate voltage application circuit that is connected to an input terminal of the output voltage switching circuit and applies an intermediate voltage between the low voltage and the high voltage to the input terminal of the output voltage switching circuit in an on state. ,
In accordance with the signal low period, the output voltage switching circuit is turned off, the low voltage application circuit is turned off, the intermediate voltage application circuit is turned on,
According to the signal high period, the output voltage switching circuit is turned on, the low voltage application circuit is turned on, and the intermediate voltage application circuit is turned off.
A gate signal line driver circuit. The switch of the intermediate voltage application circuit is connected to the output terminal of the output voltage switching circuit.
2. The gate signal line driving circuit according to claim 1, wherein The intermediate voltage is a ground voltage.
2. The gate signal line driving circuit according to claim 1, wherein The low voltage application circuit is connected in parallel to the input terminal of the output voltage switching circuit, and two low voltage applications for applying the low voltage to the input terminal of the output voltage switching circuit in the ON state, respectively. With elements,
According to the signal high period, the two low voltage application elements are turned on,
2. The gate signal line driving circuit according to claim 1, wherein The low voltage application switching circuit is:
A plurality of low voltage application switching elements that are connected in parallel to the gate signal line and apply the low voltage to the gate signal line in an on state,
At least one of the plurality of low voltage application switching elements is turned on in accordance with the signal low period, and at least one of the plurality of low voltage application switching elements is turned off in at least a part of the signal low period. Each turned on and off,
The gate line driving circuit according to claim 1, wherein:   A display device comprising the gate signal line driving circuit according to claim 1.

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