JP2012044713A - Differential four phase deviation modulated light reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an identification characteristic for signals from light front-end parts of a plurality of systems.SOLUTION: A differential four phase deviation modulated light reception circuit comprises: photoelectric conversion parts 3-1, 4-1, 3-2, 4-2, 5-1, and 5-2 outputting a plurality of electric signals of which phase modulation components are intensity-modulated from received optical signals; a clock oscillator 11 generating a clock signal having a frequency corresponding to a control signal input; a plurality of phase comparison circuits 12-1 and 12-2 outputting signals having values corresponding to phase differences between the clock signal and the plurality of electric signals, respectively; and an average calculation circuit 15 supplying the clock oscillator 11 with a signal as the control signal which is an average calculation result of the values of the signals corresponding to the phase differences. The clock oscillator 11 supplies the clock signal generated according to the control signal as a common clock signal. The differential four phase deviation modulated light reception circuit further comprises data reproduction parts 6b and 6c reproducing a plurality of data signals synchronized with the common clock signal from the plurality of electric signals respectively.

Description

  The present invention relates to a differential quadrature phase shift keying optical receiver circuit, and more particularly to a differential quadrature phase shift keyed optical receiver circuit suitable for use in an optical receiver in an optical communication system.

  In recent years, as the use of networks has become widespread, there has been a demand for a wider bandwidth for optical communication networks. Since an optical communication network is used for a trunk line network or the like, it must be capable of long-distance communication and high-speed communication with a wide bandwidth. However, in the conventional method, it has been advocated that there is a limit to the possibility of further expanding the band due to the influence of chromatic dispersion of optical fibers and nonlinear effects.

Therefore, in order to solve this problem, an attempt has been made to widen the band by devising a modulation method of an optical signal rather than a method of directly suppressing such a physical effect (for example, the following) Patent Document 1). In this proposal, a method used as a modulation method of an optical signal is called differential M phase shift keying modulation where M = 2 ⁿ when n is an integer of 2 or more. In addition, the above-described method in which n is n = 2 (M = 4) is called a DQPSK (Differential Qadrature Phase Shift Keying) modulation method.

  FIG. 15 is a diagram showing a general configuration of the DQPSK optical receiving circuit 100 based on the above-described DQPSK modulation method. In the optical receiving circuit 100 shown in FIG. 15, the optical splitter 101 splits the optical signal modulated by the DQPSK modulation method into two branches, and the π / 4 delay interferometer 102-1 and the −π / 4 delay interferometer 102-2. Thus, each of the optical signals branched in two by the optical splitter 101 is subjected to delayed interference processing. Further, the balanced photodiodes 103-1 and 103-2 convert the light subjected to the delay interference processing by the delay interferometers 102-1 and 102-2 into an electric signal (current signal).

  That is, the DQPSK signal uses light phases of π / 4, 3π / 4, −π / 4, and −3π / 4 as relative phase values with respect to the signal one symbol before. The π / 4 delay interferometer 102-1 and the −π / 4 delay interferometer 102-2 give a relative delay difference of π / 2 to the optical signal from the optical splitter 101. Thus, in the # 1 balanced photodiode 103-1 provided with the π / 4 delay interferometer 102-1, the phase change of π / 4 and -3π / 4 of the optical signal is converted into an intensity change. Output a signal. On the other hand, in the # 2 balanced photodiode 103-2 provided with the -π / 4 delay interferometer 102-2, the phase change of the optical signal between -π / 4 and 3π / 4 (π / 4 and- An electric signal in which the orthogonal component with respect to the phase change of 3π / 4 is converted into an intensity change is output.

  Then, the transimpedance amplifiers (TIAs) 104-1 and 104-2 convert the current signals from the balanced photodiodes 103-1 and 103-2 into voltage signals, respectively. Then, the digitization processing unit 105 digitizes the electric signals from the TIAs 104-1 and 104-2, and the multiplexing unit (MUX) 106 performs logical processing and restores the original signal.

  Here, in the digitization processing unit 105, in synchronization with the clock recovery (CR) 105a for extracting the clock signal from the # 1 system input signal from the TIA 104-1, and the clock signal extracted by the clock recovery 105a, DFFs (D-FlipFlop) 105b and 105c for outputting # 1 and # 2 input signals from the TIAs 104-1 and 104-2 as high-level and low-level digital signals, respectively, are provided. Yes.

As described above, in the DQPSK optical receiving circuit 100 shown in FIG. 15, two input signals (# 1 system and # 2 system) are input to the digitization processing unit 105, and one of them is input to the # 1 system. A clock is extracted from the signal to identify the above-mentioned two systems of input signals.
US Patent Application Publication No. 2004/0081470

  However, in the DQPSK optical receiving circuit 100 shown in FIG. 15 described above, the gain of the optical front end unit (see reference numerals 102-1 and 103-1) in the # 1 system used for clock extraction is reduced, or delay interference is performed. When a delay in the delay characteristics in the total 102-1 occurs, the extracted clock may be deteriorated. Therefore, in the optical front end unit (reference numerals 102-2 and 103-2) in the # 2 system. Even if the gain characteristic, the delay characteristic, etc. are normal, there is a problem that the identification characteristic in the digitization processing unit 105 may deteriorate not only for the # 1 system signal but also for the # 2 system signal.

  Also, when the above-described decrease in gain characteristics or shift in delay characteristics occurs in the # 1 and # 2 optical front end sections, as shown in FIG. A phase shift t1 (that is, a shift from the above-described desired phase difference π / 2) occurs between the input signals of the 1st system and the # 2 system. This phase shift corresponds to a relative discrimination point shift t2 in the digitization processing unit 105. That is, the # 1 system signal from which the clock C is extracted from the signal of its own system can be identified by the DFF 105b at an appropriate identification timing, but the clock is not extracted from the signal of its own system. There is another problem that the effective identification phase margin in the DFF 105c is deteriorated with respect to the side signal, that is, the # 2 system signal.

The present invention has been devised in view of such problems, and an object of the present invention is to improve identification characteristics of signals from a plurality of series of optical front end units.
It is another object of the present invention to improve the effective phase margin for signals from a plurality of optical front end units.

  (1) Therefore, the differential quadrature phase shift keying optical receiver circuit of the present invention is a differential quadrature phase shift keyed optical receiver circuit that receives an optical signal that has been subjected to differential quadrature phase shift keying. In order to regenerate a plurality of data signals from a plurality of electrical signals output from the photoelectric conversion unit, and a plurality of electrical signals output from the photoelectric conversion unit A clock signal generator for generating a common clock signal to be used, and a plurality of data signals synchronized with the common clock signal generated by the clock signal generator from a plurality of electrical signals output from the photoelectric converter Each of which reproduces a clock signal having a frequency corresponding to an input control signal, and a clock generator that generates the clock signal. A plurality of phase comparators for detecting a phase difference between the signal and the plurality of electrical signals output from the photoelectric converter by phase comparison, and outputting a signal having a value corresponding to the phase difference, respectively. And an average calculation circuit that calculates an average of the signal values corresponding to the phase differences from the plurality of phase comparison units and supplies the signal as the calculation result to the clock oscillation unit as the control signal. The clock oscillating unit supplies a clock signal generated according to the control signal from the average arithmetic circuit to the data reproducing unit as the common clock signal.

  (2) In this case, the photoelectric conversion unit outputs two electric signals whose phase modulation components are intensity-modulated from the received optical signal, and the data recovery unit outputs from the photoelectric conversion unit The two data signals synchronized with a common clock signal are reproduced from the two electrical signals, and the clock signal generation unit uses the data reproduction unit to reproduce the two data signals. And a plurality of phase comparators that detect a phase difference between the clock signal generated by the clock oscillator and the two electrical signals output from the photoelectric converter by phase comparison. Two phase comparators each outputting a signal having a value corresponding to the phase, and the average arithmetic circuit has a value corresponding to the phase difference from the two phase comparators Average calculating the item, a signal having a value serving as the average of the calculation results may also be possible to supply to the clock oscillation unit as the control signal.

  As described above, according to the present invention, the average operation circuit calculates the average of the signal values corresponding to the phase differences from the plurality of phase comparison circuits, and supplies the operation result signal as a control signal to the clock oscillator. The clock generator can supply a clock signal generated according to the control signal from the average arithmetic circuit as a common clock signal to the data reproducing unit. In addition to improving the identification characteristics, it is possible to improve the effective phase margin of the identification timing for other series of electrical signals compared to the case where the clock signal is extracted from one series of electrical signals. There is also.

It is a figure which shows the DQPSK optical receiver circuit concerning 1st Embodiment of this invention. It is a flowchart for demonstrating an example of the control aspect with respect to the data switching circuit by the control signal output part in 1st Embodiment of this invention. It is a flowchart for demonstrating the other example of the control aspect with respect to the data switching circuit by the control signal output part in 1st Embodiment of this invention. It is a figure which shows the DQPSK optical receiver circuit concerning 2nd Embodiment of this invention. (A), (b) is a figure for demonstrating the waveform degradation which appears as a fluctuation | variation of a peak value, when there is a phase shift amount deviation. (A), (b) is a figure for demonstrating the waveform degradation which appears as a fluctuation | variation of a peak value, when there is a phase shift amount deviation. It is a flowchart for demonstrating an example of the control aspect with respect to the data switching circuit by a control signal output part. It is a figure which shows the DQPSK optical receiver circuit concerning 3rd Embodiment of this invention. It is a figure which shows the DQPSK optical receiver circuit concerning the 1st modification of 3rd Embodiment of this invention. It is a figure which shows the DQPSK optical receiver circuit concerning the 2nd modification of 3rd Embodiment of this invention. 11 is a flowchart for explaining an example of a selection control mode for a switch by a selection control unit of the DQPSK optical receiving circuit shown in FIG. 10; It is a figure which shows the DQPSK optical receiver circuit concerning 4th Embodiment of this invention. It is a figure which shows the DQPSK optical receiver circuit concerning the 1st modification of 4th Embodiment of this invention. It is a figure which shows the DQPSK optical receiver circuit concerning the 2nd modification of 4th Embodiment of this invention. It is a figure which shows the general structure of a DQPSK optical receiver circuit. It is a figure for demonstrating the subject which this invention should solve.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the present invention is not limited to the following embodiments. In addition to the above-described object of the present invention, other technical problems, means for solving the technical problems, and operational effects will become apparent from the disclosure of the following embodiments.
[A] Description of First Embodiment FIG. 1 is a diagram showing a DQPSK optical receiver circuit according to a first embodiment of the present invention. The DQPSK optical receiver circuit 1 shown in FIG. 1 receives a differential 4-phase shift key (DQPSK-modulated) optical signal in which n is set to 2 (M = 2 ² = 4). This is a transmodulation light receiving circuit. The DQPSK optical receiver circuit 1 shown in FIG. 1 includes a digitization processing unit 6 different from that shown in FIG. Reference numeral 8 denotes an electrical contact. The optical splitter 2, the delay interferometer 3-1, 3-2, the balanced photodiode 4-1, 4-2, the transimpedance amplifier (TIA) 5-1, 5-2, and the MUX 7 are respectively shown in the above-mentioned drawings. 15 (symbols 101, 102-1, 102-2, 103-1, 103-2, 104-1, 104-2, 106).

That is, the optical signals received by the optical splitter 2 by the two delay interferometers 3-1 and 3-2 and the balanced photodiodes 4-1 and 4-2 and the TIAs 5-1 and 5-2 forming the optical front end. Thus, the photoelectric conversion unit is configured to output two electric signals whose phase modulation components are intensity-modulated.
Also, the digitization processing unit 6 receives two systems (# 1 system and # 2 system) of input electrical signals from the TIAs 5-1 and 5-2 to determine a common clock signal, and to determine a predetermined clock signal. Are used to output two systems of digital signals with high and low levels identified. The digitization processing unit 6 includes clock recovery 6a, DFFs 6b and 6c having basically the same configuration as that shown in FIG. 15 (see reference numerals 105a to 105c), and a selection control unit 6d and a data switching circuit. 6e is provided.

The data switching circuit 6e selectively selects one of the two electric signals output from the TIAs 5-1 and 5-2 as the clock recovery 6a based on a selection control signal from the selection control unit 6d described later. Output. Therefore, the data switching circuit 6e constitutes a selection unit that selects an electrical signal used for generating the above-described common clock signal.
In addition, the selection control unit 6d is configured to monitor the signal characteristics of the two electric signals output from the TIAs 5-1 and 5-2 that constitute the photoelectric conversion unit, and to monitor results of the monitor unit 6da. Accordingly, the control signal output unit 6db outputs a signal (selection control signal) for controlling selection in the data switching circuit 6e to the data switching circuit 6e. Thereby, the selection control unit 6d monitors the signal characteristics of the two electric signals described above, and selects an electric signal for generating a common clock signal in the data switching circuit 6e according to the monitoring result. Can be controlled.

Further, in the clock recovery (CR) 6a, the clock signal is extracted from the electrical signal selected as described above by the data switching circuit 6e, and the DFFs 6b and 6c are used as a common clock signal for identifying the two systems of electrical signals. To output.
Therefore, the clock recovery 6a uses either one of the two electrical signals output from the TIAs 5-1 and 5-2 as the photoelectric conversion units to reproduce the two data signals in the DFFs 6b and 6c. A clock signal generation unit that generates a common clock signal to be used, extracts a clock signal component included in the electrical signal selected by the data switching circuit 6e, and outputs the extracted clock signal component to the DFFs 6b and 6c as a common clock signal. This is a clock signal extraction unit to be supplied.

  The DFFs 6b and 6c can output digital signals synchronized with the common clock signal extracted by the clock recovery 6a for the # 1 and # 2 signals from the TIAs 5-1 and 5-2, respectively. It can be done. Therefore, the DFFs 6b and 6c described above each reproduces two data signals synchronized with a common clock signal from the two electrical signals output from the TIAs 5-1 and 5-2 that constitute the photoelectric conversion unit. Configure.

  Note that the control signal output unit 6db of the selection control unit 6d described above may output a selection control signal to the data switching circuit 6e so as to extract a clock signal from a signal having a better monitoring result of signal characteristics. It is also possible to select either one (for example, # 1 system signal) by default, while the other signal (in this case) when the monitoring result of the signal characteristics of the selected signal falls below a predetermined standard. The selection control signal may be output to the data switching circuit 6e in order to select the # 2 system signal.

Further, as the monitor unit 6da of the selection control unit 6d described above, for example, power for monitoring the average power of two electric signals (# 1 system and # 2 system input signals from TIA5-1 and 5-2). It can be configured as a monitor 6da.
FIG. 2 is a flowchart for explaining an example of a control mode for the data switching circuit 6e by the control signal output unit 6db according to the monitoring result of the power monitor 6da when the monitor unit 6da is configured as a power monitor. is there.

In the control mode shown in FIG. 2, the control signal output unit 6db controls the data switching circuit 6e as a selection unit to select an electric signal that maximizes the average power based on the monitoring result of the average power. It is supposed to be.
Specifically, the power monitor 6da measures the average power POW1 of the # 1 system input signal from the TIA 5-1 and the average power POW2 of the # 2 system input signal from the TIA5-2 (steps A1 and A2), respectively. The control signal output unit 6db outputs a selection control signal to the data switching circuit 6e so as to select the larger signal among these measurement results.

  That is, when the average power POW1 of the # 1 system input signal is equal to or higher than the average power POW2 of the # 2 system input signal (POW1 ≧ POW2), the data switching circuit 6e selects the # 1 system input signal. When the selection control signal is output as much as possible (from the YES route of step A3 to step A4), the average power POW1 of the # 1 system input signal is smaller than the average power POW2 of the # 2 system input signal (POW1 <POW2). The control signal output unit 6db outputs a selection control signal for selecting the # 2 system input signal for clock signal extraction to the data switching circuit 6e (from the NO route of step A3 to step A5).

  Regarding the determination of the average power in the power monitor 6da, when the average power POW1 of the # 1 input signal is larger than the average power POW2 of the # 2 input signal (POW1> POW2), the data switching circuit. At 6e, a selection control signal is output to the data switching circuit 6e to select the # 1 system input signal, while the average power POW1 of the # 1 system input signal is equal to or lower than the average power POW2 of the # 2 system input signal. In this case (POW1 ≦ POW2), the data switching circuit 6e may output a selection control signal to the data switching circuit 6e so as to select the # 2 system input signal (see Z in FIG. 2).

FIG. 3 is a diagram for explaining another example of a control mode for the data switching circuit 6e by the control signal output unit 6db according to the monitoring result of the power monitor 6da when the monitor unit is configured as the power monitor 6da. It is a flowchart.
In the control mode shown in FIG. 3, one of the two electrical signals (for example, # 1 system electrical signal) is selected by default, and the average power of the selected electrical signal is determined based on a preset threshold value. Is smaller or less than or equal to the threshold value, the data switching circuit 6e is switched to switch the selection to an electric signal other than the selected electric signal (in this case, the # 2 electric signal). A selection control signal is output.

  Specifically, in the control signal output unit 6db, the average power of the input signals of the # 1 system and # 2 system that trigger the switching of the selection of the input signals of the # 1 system and the # 2 system in the data switching circuit 6e. The thresholds to be compared with POW1 and POW2 are set to Pth1 and Pth2, respectively (step B1). Then, the average power POW1 for the # 1 signal (step B2) selected by default in the data switching circuit 6e is measured by the power monitor 6da (step B3), and the control signal output unit 6db The corresponding threshold value Pth1 is compared (step B4).

  As a result of the comparison at the control signal output unit 6db, when the average power measurement result POW1 for the # 1 system signal is equal to or greater than the threshold Pth1 (POW1 ≧ Pth1), the measurement result is normal, It is appropriate to select the # 1 system signal for extracting the clock signal, and the control signal output unit 6db does not output a selection control signal for switching the selection to the data switching circuit 6e ( YES route of step B4).

  On the other hand, when the average power measurement result POW1 for the # 1 system signal is smaller than the threshold Pth1 (POW1 <Pth1), the optical front end (reference numerals 102-1, 103) that outputs the # 1 system signal. It can be assumed that the gain characteristics, delay characteristics, etc. in -1) are not within the appropriate ranges, and it is not appropriate to select the # 1 system signal for extracting the clock signal. Therefore, the data switching circuit 6e switches the clock signal extraction signal from the # 1 system electrical signal to the # 2 system electrical signal on the assumption that the average power of the # 2 system signal is normal.

  That is, the average power POW2 for the # 2 system signal is measured by the power monitor 6da (step B5), and the control signal output unit 6db compares the magnitude of the measurement result POW2 with the corresponding threshold value Pth2 (step B5). B6). At this time, when the average power measurement result POW2 for the # 2 system signal is equal to or greater than the corresponding threshold value Pth2 (POW2 ≧ Pth2), the optical front end (reference numerals 102-2, 102-2, # 2) outputs the # 2 system signal. Since the gain characteristic, delay characteristic, etc. in 103-2) are within appropriate ranges, the control signal output unit 6db outputs a selection control signal to the data switching circuit 6e, whereby an electric signal used for extracting the clock signal Is switched to the # 2 system electric signal (from the YES route of step B6 to step B7). However, when the average power measurement result for the # 2 system signal is smaller than the threshold value Pth2 (POW2 <Pth2), the optical front end (reference numerals 102-2 and 103-2) for outputting the # 2 system signal is used. It can be assumed that the gain characteristics, delay characteristics, etc. are not within the appropriate ranges. In this case, an alarm signal is output (from NO route of step B6 to step B8).

  When POW1 = Pth1, it is assumed that the clock signal extraction signal is switched from the # 1 electric signal to the # 2 electric signal on the assumption that the average power of the # 2 signal is normal. It may be. Further, when POW2 = Pth2, the selection control signal may be output to select the # 2 system signal without outputting the alarm signal. Further, the above-described Pth1 and Pth2 may be the same value or different values depending on the characteristics of the respective optical front ends.

In the DQPSK optical receiver circuit 1 according to the first embodiment configured as described above, the received DQPSK modulated light is demodulated by the # 1 and # 2 optical front ends.
That is, delay interference processing is performed in the delay interferometer 3-1, which is the # 1 optical front end, and photoelectric conversion detection is performed in the balanced photodiode 4-1, whereby π / 4 and -3π / 4 of the optical signal are detected. An electrical signal (# 1 system) in which the phase change is converted into an intensity change is output. On the other hand, delay interference processing is performed in the delay interferometer 3-2 which is the # 2 optical front end, and photoelectric conversion is detected in the balanced photodiode 4-2, so that -π / 4 and 3π / 4 of the optical signal are detected. An electrical signal (# 2 system) in which the phase change is converted into an intensity change is output.

  In the digitization processing unit 6, the digital signals synchronized with a common clock signal having a frequency corresponding to the bit rate for these # 1 and # 2 electric signals input through the TIAs 5-1 and 5-2. And output to MUX7. At this time, the data switching circuit 6e receives a selection control signal (selection control signal output from the control signal output unit 6db according to the monitoring result in the monitoring unit 6da) from the selection control unit 6d, and receives the TIA5-1, One of the electric signals from 5-2 is output to the clock recovery 6a for clock extraction.

  As described above, according to the first embodiment of the present invention, the data switching circuit 6e as the selection unit can select the electrical signal for generating the common clock signal in the clock recovery 6a. A clock signal used in common in the DFFs 6b and 6c for digitizing the # 1 system signal and the # 2 system signal can be extracted from the signal having the better characteristics, and the signals from the two series of optical front end units. There is an advantage that the identification characteristics can be improved.

[B] Description of Second Embodiment FIG. 4 is a diagram showing a DQPSK optical receiver circuit according to a second embodiment of the present invention. The DQPSK optical receiver circuit 1A shown in FIG. 4 has a selection control unit 6d 'different from that shown in FIG. 1, and between TIA5-1 and DFF6b, and between TIA5-2 and DFF6c. Limiter amplifiers (LIA) 6f-1 and 6f-2 for distinguishing between high level and low level are provided. Other configurations are the same as those in the first embodiment, and in FIG. 4, the same reference numerals as those in FIG. 1 indicate substantially the same parts. Reference numeral 8 denotes an electrical contact.

Here, the selection control unit 6d ′ includes a waveform monitor 6dc different from that in the first embodiment as a monitor unit, and a control signal output unit 6db similar to that in the first embodiment.
The waveform monitor 6dc monitors the waveform of each electrical signal output from the balanced photodiodes 4-1 and 4-2 forming the photoelectric conversion unit via the TIAs 5-1 and 5-2, respectively. Specifically, each electric signal is detected together with a power monitor that detects an average power of each electric signal output from each of the balanced photodiodes 4-1, 4-2 via the TIAs 5-1 and 5-2. It is comprised by the peak detection circuit which detects the peak value of.

  Here, each of the delay interferometers 3-1 and 3-2 interferes with a delay component of 1 bit time and a component in which phase control of π / 4 rad and −π / 4 rad is performed by a voltage applied to the electrode ( The interference result is 2 outputs. At this time, when a substantial error (phase shift amount deviation Δ) occurs in the phase control amount (phase shift amount), the error does not occur [FIGS. 5A and 5B]. Compared with the reference], waveform deterioration as shown in FIGS. 6A and 6B occurs. 5A and 6A show the waveforms of the electrical signals from the TIA 5-1 or 5-2 when there is no phase shift amount deviation Δ and when there is, respectively, FIG. ) And FIG. 6B are eye patterns of the waveforms in FIGS. 5A and 6A, respectively.

  That is, when the above-described phase shift amount deviation Δ occurs, the average power value measured in the case of the first embodiment has no substantial fluctuation, but the waveform deterioration is particularly shown in FIGS. It appears as a fluctuation of the peak value as shown in 6 (b). In FIGS. 5B and 6B, the peak value when no phase shift amount Δ has occurred is shown as Pe. It can be assumed that such waveform deterioration leads to deterioration of the extracted clock signal.

  Therefore, in the waveform monitor 6dc of the second embodiment, not only the average power similar to the case of the first embodiment but also the fluctuation of the peak value of each electric signal is detected. In the output unit 6db, when the clock signal is extracted from the electrical signal in which the phase shift amount has shifted based on the monitoring result from the waveform monitor 6dc, the clock signal is derived from the electrical signal in which the phase shift amount has not shifted. In order to extract, a selection control signal can be output to the data switching circuit 6e.

  Since the LIAs 6f-1 and 6f-2 are provided in the second embodiment, the clock signals used for digitizing the # 1 and # 2 electric signals in the DFFs 6b and 6c are LIA6f- It is preferable to extract from either of the outputs of 1 and 6f-2. However, when the waveform monitor 6dc is used to monitor the waveform, fluctuations in the peak value to be originally detected are detected in the outputs of LIA6f-1 and 6f-2. Since it is suppressed, it is preferable to detect the signal waveforms of the # 1 system and the # 2 system from the outputs of the TIAs 5-1 and 5-2, which are the previous stage of the LIAs 6f-1 and 6f-2.

Also in the DQPSK optical receiver circuit 1A according to the second embodiment configured as described above, the received DQPSK modulated light is demodulated by the # 1 system and # 2 system optical front ends.
That is, delay interference processing is performed in the delay interferometer 3-1, which is the # 1 optical front end, and photoelectric conversion detection is performed in the balanced photodiode 4-1, whereby π / 4 and -3π / 4 of the optical signal are detected. An electrical signal (# 1 system) in which the phase change is converted into an intensity change is output. On the other hand, delay interference processing is performed in the delay interferometer 3-2 which is the # 2 optical front end, and photoelectric conversion is detected in the balanced photodiode 4-2, so that -π / 4 and 3π / 4 of the optical signal are detected. An electrical signal (# 2 system) in which the phase change is converted into an intensity change is output.

  In DFFs 6b and 6c, the # 1 system electric signal input from balanced photodiode 4-1 through TIA5-1 and LIA6f-1, and balanced photodiode 4-2 to TIA5-2 and LIA6f, respectively. 2 is converted into a digital signal synchronized with a common clock signal having a frequency corresponding to the bit rate with respect to the # 2 system electric signal input through -2, and is output to the MUX 7. At this time, the data switching circuit 6e receives a selection control signal (selection control signal output from the control signal output unit 6db in accordance with the monitoring result in the waveform monitoring unit 6dc) from the selection control unit 6d ′, and receives the LIA 6f− One of the electrical signals from 1 and 6f-2 is output to the clock recovery 6a for clock extraction.

FIG. 7 shows an example of a control mode for the data switching circuit 6e by the control signal output unit 6db according to the monitoring result of the waveform monitor 6dc when the selection control unit 6d ′ is provided with the waveform monitor 6dc as described above. It is a flowchart for demonstrating.
Here, the waveform monitor 6dc detects average powers A1 and A2 and peak detection values P1 and P2 for the # 1 system and # 2 system input signals from the TIAs 5-1 and 5-2, and outputs them as monitoring results. can do. In the control signal output unit 6db, the threshold values to be compared for the monitoring results A1, A2, P1, and P2 are set as Ath1, Ath2, Pth1, and Ath2, respectively (step C1). In this case, the comparison using the peak values P1 and P2 is performed based on the ratio of the peak value to the average power, and the comparison result shows the amount of phase shift amount deviation due to the peak value fluctuation. It comes to judge.

  First, the control signal output unit 6db outputs a selection control signal to the data switching unit 6e, so that the data switching circuit 6e first selects (as a default) a # 1 system signal (step C2). Then, the average powers A1 and A2 and peak detection values P1 and P2 for the electrical signals from the TIAs 5-1 and 5-2 are measured by the waveform monitor 6dc (step C3).

  Next, the control signal output unit 6db receives the monitoring result from the waveform monitor 6dc, and measures the electrical signal from the LIA 5-1, which is a series of signals selected by the data switching circuit 6e for clock extraction. The result A1 is compared with the threshold value Ath1, and the value A1 / P1 of the ratio of the peak value P1 to the average power A1 is compared with the corresponding threshold value Pth1 (step C4).

  At this time, as a result of the comparison at the control signal output unit 6db, both the result of comparison of the average power measurement result A1 and the threshold value Ath1 for the # 1 system signal and the comparison of the threshold value Pth1 for A1 / P1 are both When the threshold is equal to or greater than (A1 ≧ Ath1 and A1 / P1 ≧ Pth1), it is appropriate that the measurement result is normal and the # 1 system signal is selected for extracting the clock signal. The control signal output unit 6db does not output a selection control signal for switching the selection to the data switching circuit 6e (from the YES route of Step C4 to Step C2).

  On the other hand, among the comparison results between the average power measurement result A1 and the threshold value Ath1 for the # 1 system signal and the threshold value Pth1 for A1 / P1, at least A1 <Ath1 or When A1 / P1 <Pth1 (A1 <Ath1 and / or A1 / P1 <Pth1), the gain characteristics in the optical front end (reference numerals 3-1 and 4-1) for outputting the # 1 system signal It can be assumed that the delay characteristic or the phase shift amount deviation Δ is not within an appropriate range, and it is not appropriate to select the # 1 system signal for extracting the clock signal. Therefore, in the data switching circuit 6e, assuming that the monitoring result for the # 2 system signal is normal (A2 ≧ Ath2, A2 / P2 ≧ Pth2), the clock signal extraction signal is used as the # 1 system electrical signal. Is switched to the # 2 system electric signal (NO route of step C4, YES route of step C5 to step C6).

  However, as a result of the comparison of the monitoring result for the # 2 system signal with the threshold value, A2 <Ath2 and / or A2 / P2 <Pth2, and the optical front end for outputting the # 2 system signal (reference numeral 3-2) , 4-2), if it is recognized that the gain characteristic, delay characteristic, phase shift amount deviation Δ, etc. are not within the proper range, an alarm signal is output (from NO route of step C5 to step C7).

  As described above, according to the second embodiment of the present invention, the data switching circuit 6e as the selection unit can control the selection of the electrical signal for generating the common clock signal in the clock recovery 6a. In addition to the same advantages as those of the first embodiment described above, the peak value detected by the waveform monitor 6dc is used for the control of the data switching circuit 6e, so that the delay interferometers 3-1, 3 are used. -2 phase control amount deviation can also be triggered by the switching of the clock signal, and the signal selected for clock signal extraction can be switched to the non-degraded side with high accuracy. There is an advantage that it is possible to improve the discrimination characteristics for signals from the optical front end portion of the sequence.

[C] Description of Third Embodiment FIG. 8 is a diagram showing a DQPSK optical receiver circuit 1B according to a third embodiment of the present invention. The DQPSK optical receiving circuit 1B according to the third embodiment includes a digitization processing unit 6B different from that shown in FIGS. 1, 4 and 15, but the other configuration is the case of the first embodiment. In FIG. 4, the same reference numerals as those in FIG. 1 denote almost the same parts. Here, the digitization processing unit 6B includes DFFs 6b and 6c and a selection control unit 6d similar to those in the above-described embodiments, a voltage controlled oscillator (VCO) 11, a phase comparison circuit (phase comparison unit) 12- 1 and 12-2 and a switch (SW) 13 are provided. In addition, 8 is an electrical contact.

  The voltage controlled oscillator 11 is a clock oscillating unit that generates a clock signal having a frequency corresponding to an input control voltage signal. The phase comparison circuit 12-1 converts the clock signal generated by the voltage controlled oscillator 11 and photoelectric conversion. A phase difference from the electrical signal (# 1 system electrical signal) output from the section 4-1 through the TIA 5-1 is detected by phase comparison, and a signal CONT # 1 corresponding to the phase difference is output. Similarly, the phase comparison circuit 12-2 has a phase difference between the clock signal generated by the voltage controlled oscillator 11 and the electrical signal (# 2 system electrical signal) output from the photoelectric conversion unit 4-2 through the TIA5-2. Are detected by phase comparison, and a signal CONT # 2 corresponding to the phase difference is output.

The switch 13 receives a selection control signal from the control signal output unit 6db constituting the selection control unit 6d, and receives a signal CONT # corresponding to the phase difference from the two phase comparison circuits 12-1 and 12-2. One of CONT # 2 is selectively output to the voltage controlled oscillator 11 as the control voltage signal VCONT.
In other words, the switch 13 is a selection unit that selects an electrical signal used for generating a common clock signal, and among the signals corresponding to the phase differences from the plurality of phase comparison circuits 12-1 and 12-2. Thus, a signal corresponding to the phase difference of the electrical signal selected under the control of the selection control unit 6d is supplied as a control voltage signal to the voltage controlled oscillator 11.

  As a result, the voltage controlled oscillator 11 can generate a clock signal having a frequency controlled according to the selected control voltage signal VCONT, and supply it to the DFFs 6b and 6c as a common clock signal. . Therefore, the voltage controlled oscillator 11 and the plurality of phase comparison circuits 12-1 and 12-2 constitute a PLL (Phase Locked Loop), and balanced photodiodes 4-1 and 4-2 forming an photoelectric conversion unit. A clock signal generation unit that generates a common clock signal used for reproduction of a plurality of data signals by the DFFs 6b and 6c is configured using any one of the plurality of electrical signals output from the DFF 6b.

In the DQPSK optical receiver circuit 1B according to the third embodiment configured as described above, the received DQPSK modulated light is demodulated by the # 1 system and # 2 system optical front ends.
That is, delay interference processing is performed in the delay interferometer 3-1, which is the # 1 optical front end, and photoelectric conversion detection is performed in the balanced photodiode 4-1, whereby π / 4 and -3π / 4 of the optical signal are detected. An electrical signal (# 1 system) in which the phase change is converted into an intensity change is output. On the other hand, delay interference processing is performed in the delay interferometer 3-2 which is the # 2 optical front end, and photoelectric conversion is detected in the balanced photodiode 4-2, so that -π / 4 and 3π / 4 of the optical signal are detected. An electrical signal (# 2 system) in which the phase change is converted into an intensity change is output.

  Then, in the digitization processing unit 6B, the digital signals synchronized with the common clock signal having the frequency corresponding to the bit rate for these # 1 system and # 2 system electric signals input through the TIAs 5-1 and 5-2. And output to MUX7. At this time, the switch 13 receives a selection control signal (selection control signal output from the control signal output unit 6db according to the monitoring result of the monitoring unit 6da) from the selection control unit 6d, and receives the phase comparison circuit 12-1. , 12-2, one of the phase comparison results is output as a control voltage signal to the voltage controlled oscillator 11.

As a result, voltage controlled oscillator 11 extracts a common clock signal from one of the above-described # 1 system or # 2 system electrical signals selected according to the monitoring result. Will be able to.
In the first or second embodiment described above, in the clock recovery 6a, one of the # 1 and # 2 electric signals is selected from the TIA5-1, 5-2 or LIA6f-1, 6f-2. The clock signal is extracted directly from the electrical signal. In other words, since the switching in the data switching circuit 6e is for the signal itself containing the data component, the switching response is also required to be performed at a high speed corresponding to the data bit rate. Assuming that the bit rate of DQPSK-modulated data is, for example, 20 Gb / s × 2, an element capable of switching the response speed corresponding to such a bit rate needs to be designed exclusively for the current situation. Yes, it is difficult to apply general-purpose switching elements.

  On the other hand, in the third embodiment, since the control voltage signal corresponding to the phase difference supplied to the voltage controlled oscillator 11 can be set to a frequency sufficiently lower than the frequency corresponding to the bit rate, the voltage controlled oscillator In addition to being able to generate a common clock signal substantially the same as in the first or second embodiment described above, the switching response performance of the switch 13 constituting the selection unit is also the first or second embodiment. The performance equivalent to the data switching circuit 6e in the case of the embodiment is not required, and it can be configured by a general-purpose switching element, and the switching performance can be stabilized.

  As described above, according to the third embodiment of the present invention, it is possible to select an electric signal used for generating a common clock signal through switching of the switch 13 as the selection unit. And the clock signal commonly used in the DFFs 6b and 6c for digitizing the # 2 system signal can be extracted from the signal having the better characteristics, and the discrimination characteristics for the signals from the two series of optical front end units There are advantages that can be improved.

  Further, the switch 13 selectively supplies one of the signals regarding the phase difference from the phase comparison circuits 12-1 and 12-2 as a control voltage signal to the voltage controlled oscillator 11. Therefore, since the signal to be switched can be set to a frequency sufficiently lower than the frequency corresponding to the bit rate, the function as the switch 13 can be configured by a general-purpose element, so that the switching performance is stabilized. There is also an advantage that can be achieved.

[C1] Description of Modification of Third Embodiment FIG. 9 is a diagram showing a DQPSK optical receiver circuit 1Ba according to a first modification of the third embodiment of the present invention. The DQPSK optical receiver circuit 1Ba shown in FIG. 9 differs from that shown in FIG. 8 described above in that selection control for the switch 13 is performed based on a selection control signal from the outside. In FIG. 9, the same reference numerals as those in FIG. 8 denote almost the same parts. That is, by this selection control signal, a common clock signal output from the voltage controlled oscillator 11 can be generated based on the phase comparison result for the electric signals of other series from the electric signals of the series whose characteristics are deteriorated. Thus, the same advantages as those of the third embodiment described above can be obtained.

  FIG. 10 is a diagram showing a DQPSK optical receiver circuit 1Bb according to a second modification of the third embodiment of the present invention. In the DQPSK optical receiver circuit 1Bb shown in FIG. 10, unlike the one shown in FIG. 8 described above, the selection control unit 14 that performs the selection control for the switch 13 performs the code error rate (BER) for the data reproduced by the DFFs 6b and 6c. ) Is input and the switch 13 is selectively controlled in accordance with the BER value. In FIG. 9, the same reference numerals as those in FIG. 8 denote almost the same parts.

  FIG. 11 is a flowchart for explaining an example of a selection control mode for the switch 13 by the selection control unit 14. As shown in FIG. 11, the selection control unit 14 first sets a threshold value Bth to be compared with respect to BER (step D1). As an initial setting, the phase difference signal from the phase comparison circuit 12-1 is a voltage. The switch 13 is selectively controlled so as to be output to the controlled oscillator 11 (step D2).

  Next, the measurement result of the code error rate BER is fetched for the data reproduced by the common clock signal generated by the voltage controlled oscillator 11 using the phase difference signal from the phase comparison circuit 12-1 (step D3). Then, the fetched BER value is compared with the threshold value Bth (step D4). At this time, if the fetched BER value is equal to or greater than the threshold value Bth, the phase difference signal used for clock extraction is left as it is (from the YES route in step D4 to “selection as it is” in step D5). ) When the fetched BER value is smaller than the threshold value Bth, a selection control signal for changing the phase difference signal used for clock extraction is output to the switch 13. As a result, the voltage controlled oscillator 11 generates a common clock signal from the phase difference signal from the phase comparison circuit 12-2 ("switching selection" from the NO route in step D4 to step D6). After that, BER is continuously taken in and compared with the same threshold value, and the switch 13 is selectively controlled to switch the phase difference signal according to the comparison result (steps D3 to D6).

  Therefore, the selection control unit 14 can switch and control the switch 13 as the selection unit according to the code error rate for the data reproduced by the DFFs 6b and 6c. The electric signal used for generating the signal can be selected, and the clock signal used in common in the DFFs 6b and 6c for digitizing the # 1 system signal and the # 2 system signal is selected from the signal having the better characteristics. The same advantage as in the case of the third embodiment described above can be obtained.

[D] Description of Fourth Embodiment FIG. 12 is a diagram showing a DQPSK optical receiver circuit 1C according to a fourth embodiment of the present invention. The DQPSK optical receiving circuit 1C shown in FIG. 12 includes a digitization processing unit 6C different from that shown in the third embodiment (see FIG. 8), but the other configuration is the case of the third embodiment. In FIG. 12, the same reference numerals as those in FIG. 8 denote almost the same parts. Here, the digitization processing unit 6C includes the DFFs 6b and 6c, the voltage controlled oscillator (VCO) 11 and the phase comparison circuits 12-1 and 12-2 similar to those in the third embodiment described above, and an averaging circuit. 15 is provided. In addition, 8 is an electrical contact.

  The averaging circuit 15 calculates an average [in this case, (CONT # 1 + CONT # 2) / 2] of a signal (voltage signal) corresponding to each phase difference from the phase comparison circuits 12-1 and 12-2. The average calculation circuit supplies a signal (voltage signal) as a calculation result to the voltage controlled oscillator 11 as a control voltage signal VCONT. As a result, the voltage controlled oscillator 11 can supply a clock signal generated according to the control voltage signal from the averaging circuit 15 to the DFFs 6b and 6c as a common clock signal.

Therefore, the above-described voltage-controlled oscillator 11, the phase comparison circuits 12-1, 12-2 and the averaging circuit 15 generate a clock signal for generating a common clock signal used for reproducing two data signals in the DFFs 6b, 6c. Parts.
Also in the DQPSK optical receiver circuit 1C according to the fourth embodiment configured as described above, the received DQPSK modulated light is demodulated by the # 1 system and # 2 system optical front ends.

  That is, delay interference processing is performed in the delay interferometer 3-1, which is the # 1 optical front end, and photoelectric conversion detection is performed in the balanced photodiode 4-1, whereby π / 4 and -3π / 4 of the optical signal are detected. An electrical signal (# 1 system) in which the phase change is converted into an intensity change is output. On the other hand, delay interference processing is performed in the delay interferometer 3-2 which is the # 2 optical front end, and photoelectric conversion is detected in the balanced photodiode 4-2, so that -π / 4 and 3π / 4 of the optical signal are detected. An electrical signal (# 2 system) in which the phase change is converted into an intensity change is output.

Then, in the digitization processing unit 6C, the digital signals synchronized with the common clock signal having the frequency corresponding to the bit rate for these # 1 system and # 2 system electric signals inputted through the TIAs 5-1 and 5-2. And output to MUX7. Here, the above-described common clock signal is generated in the voltage controlled oscillator 11.
In the voltage controlled oscillator 11, the clock is based on the average voltage signal VCONT of the control voltage signals CONT # 1 and CONT # 2 from the phase comparison circuits 12-1 and 12-2 calculated by the averaging circuit 15. The signal is generated. That is, the phase comparison circuit 12-1 outputs a voltage signal having a # 1 phase shift component, while the phase comparison circuit 12-2 outputs a voltage signal having a # 2 phase shift component. The averaging circuit 15 calculates the average of these voltage signals to obtain a voltage signal in which the relative phase shift components of the # 1 and # 2 electric signals are averaged. It is.

  In the voltage controlled oscillator 11, since the voltage signal whose phase shift component is averaged by the above-described calculation in the averaging circuit 15 can be taken in as the control voltage signal VCONT, the intermediate timing of the optimum identification timing in each of the DFFs 6b and 6c. Compared to the case where the clock signal is extracted from the electric signal of one series, the effective phase margin of the identification timing for the electric signal of the other series can be improved. it can.

  Thus, according to the fourth embodiment of the present invention, the averaging circuit 15 calculates the average of the signal values corresponding to the phase differences from the plurality of phase comparison circuits 12-1 and 12-2, and calculates The resulting signal is supplied to the voltage controlled oscillator 11 as the control voltage signal VCONT, and the voltage controlled oscillator 11 generates a clock signal generated according to the control voltage signal VCONT from the averaging circuit 15 to the DFFs 6b and 6c. Since it can be supplied as a clock signal, it can improve the discriminating characteristics of the signals from the two series of optical front-end units, and it can be compared with the case where the clock signal is extracted from one series of electrical signals. There is also an advantage that the effective phase margin of the identification timing for the electric signals of the series can be improved.

[D1] Description of Modification of Fourth Embodiment FIG. 13 is a diagram illustrating a DQPSK optical receiver circuit 1Ca according to a first modification of the fourth embodiment. The DQPSK optical receiver circuit 1Ca shown in FIG. 13 is in addition to the configuration of the fourth embodiment (see FIG. 12) described above, and weighting control units 16-1 and 16-2 and weighting circuits 17-1 and 17- 2 is provided. In FIG. 13, the same reference numerals as those in FIG. 12 denote almost the same parts.

  Here, the weighting circuits 17-1 and 17-2 are signals (voltage signals CONT # 1 and CONT #, which have values corresponding to the phase differences output from the phase comparison circuits 12-1 and 12-2, respectively. 2) is a weighting unit that individually assigns weights. The weighting control units 16-1 and 16-2 control the weighting given by the weighting circuits 17-1 and 17-2, respectively. Thereby, in the averaging circuit 15, an average is calculated about the voltage signal which has the value according to the phase difference to which the weighting is given by the weighting assigning units 17-1 and 17-2.

  Here, the weighting control unit 16-1 includes an electrical signal monitor unit 161a that monitors an electrical signal (# 1 system) output from the balanced photodiode 4-1 forming the photoelectric conversion unit through the TIA 5-1; A weighting control signal output unit 161b that outputs a control signal for controlling the weighting given to the weighting circuit 17-1 according to the monitoring result of the signal monitoring unit 161a is provided.

  Similarly, the weight control unit 16-2 includes an electric signal monitor unit 162a that monitors an electric signal (# 2 system) output from the balanced photodiode 4-2 that constitutes the photoelectric conversion unit through the TIA 5-2, and an electric signal monitor unit 162a. A weighting control signal output unit 162b that outputs a control signal for controlling weighting given to the weighting circuit 17-2 according to the monitoring result of the signal monitoring unit 162a is provided.

As a result, the weighting circuits 17-1 and 17-2 are converted into the phase difference signals from the phase comparison circuits 12-1 and 12-2 in amounts based on the control signals from the weighting control signal output units 161b and 162b, respectively. Weighting is given.
That is, the control signal output units 161b and 162b of the above-described weighting control units 16-1 and 16-2 cooperate with each other in accordance with the monitoring results of the electric signal monitoring units 161a and 162a. 17-2, a weighting control signal output unit that outputs a control signal for individually weighting signals having values corresponding to the phase differences output from the plurality of phase comparison circuits 12-1 and 12-2, respectively. Configure.

  Further, for example, when a failure is detected in either the # 1 system or the # 2 system electrical signal based on the monitoring results from the electrical signal monitoring units 161a and 162a in the weighting control units 16-1 and 16-2. By setting the weight on the side where the malfunction is detected to “0”, the control voltage signal supplied to the voltage controlled oscillator 11 has a phase difference from the phase comparison circuit on the side where the malfunction is detected. The signal can be substantially “0”. As a result, the influence of the detected defect on the generated common clock signal can be excluded.

  Therefore, the DQPSK optical receiver circuit 1Ca shown in FIG. 13 has the same advantages as in the case of the fourth embodiment described above, and the variation in the characteristics of the optical front ends of a plurality of series can be determined from the signal status of each series. By monitoring and changing the weight of the phase difference signal (voltage signal) for which the average value is flexibly calculated according to the characteristic variation, the influence of the characteristic variation can be suppressed.

As a second modification of the fourth embodiment, as shown in FIG. 14, weight control units 18-1 and 18-2 different from the case of FIG. 13 (reference numerals 16-1 and 16-2) are provided. It may be configured. In the DQPSK optical receiver circuit 1Cb shown in FIG. 14, the same reference numerals as those in FIG. 13 denote almost the same parts.
Here, the weighting control unit 18-1 includes a reproduction data monitoring unit 181a that monitors the data signal reproduced by the DFF 6b, and a phase comparison circuit in the weighting circuit 17-1 according to the monitoring result of the reproduction data monitoring unit 181a. A weighting control signal output unit 181b that outputs a control signal for controlling the weighting of a signal having a value corresponding to the phase difference output from 12-1.

  Similarly, the weighting control unit 18-2 includes a reproduction data monitoring unit 182a that monitors the data signal reproduced by the DFF 6c, and a phase comparison circuit in the weighting circuit 17-2 according to the monitoring result of the reproduction data monitoring unit 182a. A weighting control signal output unit 182b that outputs a control signal for controlling the weighting of the signal having a value corresponding to the phase difference output from 12-2.

As a result, the weighting circuits 17-1 and 17-2 respectively convert the phase difference signals from the phase comparison circuits 12-1 and 12-2 into amounts based on the control signals from the weighting control signal output units 181b and 182b. Weighting is given.
That is, the control signal output units 181b and 182b of the above-described weighting control units 18-1 and 18-2 cooperate with each other in accordance with the monitoring results of the reproduction data monitoring units 181a and 182a. 17-2, a weighting control signal output unit that outputs a control signal for individually weighting signals having values corresponding to the phase differences output from the plurality of phase comparison circuits 12-1 and 12-2, respectively. Configure.

  Similarly to the case of FIG. 13, for example, based on the monitoring results from the reproduction data monitoring units 181a and 182a in the weighting control units 18-1 and 18-2, any of the # 1 system and # 2 system reproduction data is selected. When a crab is detected, the weight on the side where the defect is detected is set to “0”, so that the control voltage signal supplied to the voltage controlled oscillator 11 has the side where the defect is detected. The phase difference signal from the phase comparison circuit can be substantially “0”. As a result, it is possible to eliminate the influence of the failure detected in the reproduction data on the common clock signal generated from the electric signal before reproduction (electric signal output from TIA5-1, 5-2). become.

  Therefore, according to the DQPSK optical receiver circuit 1Cb shown in FIG. 14, in addition to the same advantages as in the case of the fourth embodiment described above, variations in characteristics of the optical front ends of a plurality of sequences can be obtained from the signal states of each sequence. By monitoring and changing the weight of the phase difference signal (voltage signal) for which the average value is flexibly calculated according to the characteristic variation, the influence of the characteristic variation can be suppressed.

[E] Others In the above-described embodiments, the differential quadrature phase shift keying optical receiver circuit in which n = 2 (M = 4) has been described in detail. However, according to the present invention, the present invention is not limited to this, and n The same can be applied to the differential M phase shift keyed optical receiver circuit in which M = 2 ⁿ where is an integer of 3 or more.

Further, in each of the above-described embodiments, when the power monitor 6da and the waveform monitor 6dc are applied as the monitor units that respectively monitor the two electrical signals output from the TIAs 5-1 and 5-2 that constitute the photoelectric conversion unit. However, according to the present invention, the present invention is not limited to this, and other configurations can of course be applied.
(Appendix 1)
a differential M phase shift keyed optical receiver circuit that receives a differential M phase shift keyed optical signal with M = 2 ⁿ when n is an integer greater than or equal to 2;
A photoelectric conversion unit that outputs a plurality of electrical signals whose phase modulation components are intensity-modulated from the received optical signal;
A data reproduction unit for reproducing each of a plurality of data signals synchronized with a common clock signal from a plurality of electrical signals output from the photoelectric conversion unit;
A clock signal generation unit that generates the common clock signal used for reproducing the plurality of data signals in the data reproduction unit using any one of the plurality of electric signals output from the photoelectric conversion unit. When,
A selector for selecting an electrical signal used for generating the common clock signal;
A differential M phase shift keying optical receiver circuit comprising:

(Appendix 2)
The clock signal generation unit extracts a clock signal component included in the electrical signal selected by the selection unit, and supplies the extracted clock signal component to the data reproduction unit as the common clock signal The differential M-phase shift keyed optical receiver circuit according to appendix 1, wherein:

(Appendix 3)
The clock signal generator
A clock oscillation unit for generating a clock signal having a frequency according to an input control signal;
Detecting a phase difference between the clock signal generated by the clock oscillation unit and the plurality of electrical signals output from the photoelectric conversion unit by phase comparison, and outputting a signal corresponding to the phase difference, With a phase comparator,
The selection unit is configured to supply a signal corresponding to the phase difference of the electrical signal selected from the signals from the plurality of phase comparison units as the control signal to the clock oscillation unit. ,
The differential M phase according to appendix 1, wherein the clock oscillating unit supplies a clock signal generated according to the control signal from the selection unit to the data reproduction unit as the common clock signal. Shift modulation optical receiver circuit.

(Appendix 4)
The differential M phase according to any one of appendices 1 to 3, further comprising a selection control unit that controls selection of the electric signal for generation of the common clock signal in the selection unit. Shift modulation optical receiver circuit.
(Appendix 5)
The selection control unit monitors each of the plurality of electrical signals output from the photoelectric conversion unit, and controls the selection of the electrical signal in the selection unit according to the monitoring result of the monitoring unit. The differential M phase shift keying optical receiver circuit according to appendix 4, characterized by comprising a control signal output unit for outputting a control signal.

(Appendix 6)
6. The differential M phase shift keyed optical receiver circuit according to appendix 5, wherein the monitor unit is constituted by a power monitor that monitors an average power of each electric signal output from the photoelectric conversion unit. .
(Appendix 7)
The control signal output unit of the selection control unit outputs the control signal to the selection unit so as to select an electric signal that maximizes the average power based on the monitoring result of the average power. The differential M phase shift keyed optical receiver circuit according to appendix 6.

(Appendix 8)
The control signal output unit of the selection control unit selects any one of the plurality of electrical signals by an initial setting, and an average power of the selected electrical signal is smaller than a preset threshold value or the threshold value The differential signal according to appendix 6, wherein the control signal is output to the selection unit so as to switch the selection to another electrical signal other than the selected electrical signal when M phase shift keying optical receiver circuit.

(Appendix 9)
6. The differential M phase shift keyed optical receiver circuit according to appendix 5, wherein the monitor unit is configured by a waveform monitor that monitors a waveform of each electric signal output from the photoelectric conversion unit.
(Appendix 10)
The waveform monitor detects a peak value of each electrical signal output from the photoelectric conversion unit together with an average power of each electrical signal output from the photoelectric conversion unit. Differential M phase shift keying optical receiver circuit.

(Appendix 11)
The selection control unit selects one of the plurality of electric signals by default, and detects the selected electric signal by the average power monitored by the waveform monitor and the peak detection circuit. The selected unit is controlled to switch the selection to another electric signal other than the selected electric signal when each of the peak values is smaller than a preset threshold value or less than the threshold value. 11. The differential M phase shift keyed optical receiver circuit as set forth in appendix 10.

(Appendix 12)
The differential M phase shift according to appendix 4, wherein the selection control unit controls the selection in the selection unit in accordance with a code error rate for the data reproduced in the data reproduction unit. Modulated light receiving circuit.
(Appendix 13)
A differential quadrature phase shift keying optical receiver circuit in which n is 2 and M = 4,
The photoelectric conversion unit outputs two electrical signals whose phase modulation components are intensity-modulated from the received optical signal,
The data reproduction unit reproduces two data signals synchronized with a common clock signal from two electric signals output from the photoelectric conversion unit,
The common clock signal used by the data reproduction unit to reproduce the two data signals by using one of the two electric signals output from the photoelectric conversion unit by the clock signal generation unit Produces
The selector selectively outputs any one of the two electrical signals output from the photoelectric converter to the clock signal generator for generating the common clock signal. The differential M phase shift keyed optical receiver circuit as set forth in appendix 1, wherein:

(Appendix 14)
a differential M phase shift keyed optical receiver circuit that receives a differential M phase shift keyed optical signal with M = 2 ⁿ when n is an integer greater than or equal to 2;
A photoelectric conversion unit that outputs a plurality of electrical signals whose phase modulation components are intensity-modulated from the received optical signal;
A data reproduction unit for reproducing each of a plurality of data signals synchronized with a common clock signal from a plurality of electrical signals output from the photoelectric conversion unit;
A clock signal generation unit for generating the common clock signal used for reproducing the plurality of data signals in the data reproduction unit;
The clock signal generator
A clock oscillation unit for generating a clock signal having a frequency according to an input control signal;
A phase difference between the clock signal generated by the clock oscillation unit and the plurality of electrical signals output from the photoelectric conversion unit is detected by phase comparison, and a signal having a value corresponding to the phase difference is output. A plurality of phase comparison units;
An average calculation circuit that calculates the average of the signal values according to the phase difference from the plurality of phase comparison units, and supplies the signal as the calculation result to the clock oscillation unit as the control signal, and
The clock oscillation unit supplies a clock signal generated according to the control signal from the average arithmetic circuit to the data reproduction unit as the common clock signal, and differential M phase shift keying Optical receiver circuit.

(Appendix 15)
A differential quadrature phase shift keying optical receiver circuit in which n is 2 and M = 4,
The photoelectric conversion unit outputs two electrical signals whose phase modulation components are intensity-modulated from the received optical signal,
The data reproduction unit reproduces two data signals synchronized with a common clock signal from the two electric signals output from the photoelectric conversion unit,
The clock signal generation unit generates the common clock signal used for reproducing the two data signals in the data reproduction unit;
As the plurality of phase comparison units, a phase difference between the clock signal generated by the clock oscillation unit and the two electric signals output from the photoelectric conversion unit is detected by phase comparison, and the phase difference is determined. Two phase comparators for outputting signals having different values,
The average calculation circuit calculates an average of signals having a value corresponding to the phase difference from the two phase comparison units, and uses the signal having a value as the average calculation result as the control signal as the clock oscillation unit. 15. The differential M phase shift keyed optical receiver circuit according to appendix 14, wherein

(Appendix 16)
A weighting unit that individually weights signals having values corresponding to the phase differences respectively output from the plurality of phase comparison units;
A weighting control unit for controlling the weighting given by the weighting granting unit,
15. The differential M phase bias according to appendix 14, wherein the average calculation circuit calculates the average of signals having values corresponding to the phase differences, to which the weights are respectively given by the weight assigning unit. Shift modulation optical receiver circuit.

(Appendix 17)
The weight control unit
An electric signal monitoring unit for monitoring each of the plurality of electric signals output from the photoelectric conversion unit;
In order to individually assign the weights to signals having values corresponding to the phase differences respectively output from the plurality of phase comparison units, according to the monitoring result of the electrical signal monitoring unit. 15. The differential M phase shift keyed optical receiver circuit according to appendix 14, characterized in that a weighted control signal output unit for outputting the control signal is provided.

(Appendix 18)
The weight control unit
A reproduction data monitor unit for monitoring each of the plurality of data signals reproduced by the data reproduction unit;
In order to individually assign the weights to signals having values corresponding to the phase differences respectively output from the plurality of phase comparison units in the weighting provision unit in accordance with the monitoring result in the reproduction data monitoring unit 15. The differential M phase shift keyed optical receiver circuit according to appendix 14, characterized in that a weighted control signal output unit for outputting the control signal is provided.

1, 1A to 1C, 1Ba, 1Bb, 1Ca, 1Cb, 100 DQPSK optical receiver circuit (differential 4-phase shift keyed optical receiver circuit)
2,101 Optical splitter 3-1, 3-2, 102-1, 102-2 Delay interferometer 4-1, 4-2, 103-1, 103-2 Balanced photodiode 5-1, 5-2 104-1, 104-2 Transimpedance amplifier 6, 6B, 6C, 105 Digitization processing unit 6a, 105a Clock recovery 6b, 6c, 105b, 105c DFF
6d, 6d ', 14 Selection control unit 6da Power monitor (monitor unit)
6db control signal output unit 6dc waveform monitor 6e data switching circuit (selection unit)
6f-1, 6f-2 Limiter amplifier 7 MUX
8 Electrical contact 11 Voltage controlled oscillator (clock oscillator)
12-1, 12-2 Phase comparison circuit (phase comparison unit)
13 switch (selection part)
15 Averaging circuit (Average arithmetic circuit)
16-1, 16-2, 18-1, 18-2 Weighting control unit 161a, 162a Electric signal monitoring unit 161b, 162b, 181b, 182b Weighting control signal output unit 181a, 182a Reproduction data monitoring unit 17-1, 17- 2 Weighting circuit (weighting unit)

Claims (2)

A differential quadrature phase shift keying optical receiver circuit for receiving a differential quadrature phase shift keyed optical signal,
A photoelectric conversion unit that outputs a plurality of electrical signals whose phase modulation components are intensity-modulated from the received optical signal;
A clock signal generation unit that generates a common clock signal used for reproducing a plurality of data signals from a plurality of electrical signals output from the photoelectric conversion unit;
A data reproduction unit for reproducing each of a plurality of data signals synchronized with the common clock signal generated by the clock signal generation unit from a plurality of electrical signals output from the photoelectric conversion unit;
The clock signal generator
A clock oscillator that generates a clock signal having a frequency according to an input control signal;
A phase difference between the clock signal generated by the clock oscillator and the plurality of electrical signals output from the photoelectric conversion unit is detected by phase comparison, and a signal having a value corresponding to the phase difference is output. A plurality of phase comparison circuits;
An average calculation circuit that calculates an average of the signal values according to the phase difference from the plurality of phase comparison circuits and supplies the signal as the calculation result to the clock oscillator as the control signal, and
The clock oscillator supplies a clock signal generated according to the control signal from the average arithmetic circuit to the data recovery unit as the common clock signal. Receiver circuit. The photoelectric conversion unit outputs two electrical signals whose phase modulation components are intensity-modulated from the received optical signal,
The data reproduction unit reproduces two data signals synchronized with a common clock signal from the two electric signals output from the photoelectric conversion unit,
The clock signal generation unit generates the common clock signal used for reproducing the two data signals in the data reproduction unit;
As the plurality of phase comparison units, a phase difference between the clock signal generated by the clock oscillation unit and the two electric signals output from the photoelectric conversion unit is detected by phase comparison, and the phase difference is determined. Two phase comparators for outputting signals having different values,
The average calculation circuit calculates an average of signals having a value corresponding to the phase difference from the two phase comparison units, and uses the signal having a value as the average calculation result as the control signal as the clock oscillation unit. The differential quadrature phase shift keying optical receiver circuit according to claim 1, wherein

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