JP2012044554A - Solid-state imaging device and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device which can perform an A/D conversion at a high speed without being affected by performance of a VCO, can suppress dispersion of input/output characteristic of a PLL and can prevent generation of a vertical streak with gain property, and to provide a camera system.SOLUTION: A reading portion includes: a VCO 1411 generating a clock signal of a frequency corresponding to voltage of a reading signal; a pre-counter 1412 counting the clock signal generated by the VCO; and a counter 1416 counting an output of the pre-counter. In a first period, counting operations of the pre-counter and the counter operate in a first direction, while the counting operations of the pre-counter and the counter operate in an opposite second direction in a second period. Signals in different levels in the first period and the second period are applied to a gate of a dummy pixel, and a first processing for outputting a value held in the counter as a Kv value being a ratio of an input voltage and an output frequency of the VCO is performed.

Description

  The present invention relates to a solid-state imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a camera system.

  In a CMOS image sensor or the like, an analog signal read from a pixel circuit is converted into a digital signal (A / D conversion) (for example, Patent Document 1). A / D conversion is often performed by an ADC circuit in the column processing circuit.

The ADC circuit performs A / D conversion by comparing the reference voltage of the ramp waveform generated by the DAC circuit with the voltage of the analog signal read from the pixel circuit using a voltage comparator or the like. The column processing circuit is connected to the DAC circuit by thousands of wires.
For this reason, there is a problem that the layout area of the column processing circuit increases as the number of pixels increases.

  In addition to this, with the increase in the number of pixels, it is necessary to pass a larger amount of current through the DAC circuit to increase the drive capability of the DAC circuit. In this case, since the wiring is complicated, there is a problem that the load on the DAC circuit and the column processing circuit increases.

  As one method for solving such a problem, an ADC circuit that performs A / D conversion using a voltage controlled oscillator (hereinafter referred to as “VCO”) is disclosed (for example, see Patent Documents 2 to 4). ).

An image sensor that uses a VCO to count the clock and perform AD conversion takes advantage of the fact that the range of the VCO output clock is limited to the inside of the column, and can be expected to be used at high frequencies in the GHz band. .
Therefore, it is possible to AD-convert the pixel signal at a higher speed and higher accuracy than in the past.

For example, the circuits described in Patent Documents 2 and 3 perform an operation of performing AD conversion by performing conversion from voltage to frequency using a VCO and counting for a certain time.
Further, in Patent Document 4, conversion from voltage to frequency is performed using a VCO, and CDS (correlated double sampling) is also compared with the P-phase and D-phase differences of the VCO output (CDS is calculated by the difference in the count value of the VCO. There is a circuit to do.
In this circuit, the output from the VCO is used as an enable signal, not as a counter clock.

JP 2006-303752 A JP 2010-10742 A JP 2009-303012 A JP 2006-270293 A

As a problem when using an image sensor having an AD converter using a VCO, the ratio of the VCO input voltage to the output frequency (Kv value) varies due to temperature, power supply voltage, and process variations.
For this reason, even when the same input voltage is applied, the output of the VCO varies, and the output is offset, or the range that can be input to the VCO is narrowed.

The circuits disclosed in the above-mentioned Patent Documents 2 and 3 perform a CDS operation of an analog signal from a vertical signal using a switched capacitor, but in this method, the influence of noise due to variations in the Kv value of the VCO itself. Cannot be removed.
Also, Patent Document 4 does not describe a countermeasure for the influence due to the variation of the Kv value.

In order to solve the above output range and offset problems, a circuit described in Patent Document 5 has been proposed.
This circuit avoids an offset due to variations in output of the VCO by forming a PLL loop before executing AD conversion, thereby making the VCO output frequency a unique value regardless of variations in Kv.

However, in this circuit, the initial value of the output frequency of the VCO at the time of AD conversion can be made constant regardless of variations in the Kv value, but at the time of P-phase and D-phase counting after the PLL loop is released. , Kv value is not controlled.
For this reason, if no countermeasures are taken, there is a risk that the vertical stripe noise of gain characteristics due to variations in transistor (Tr) characteristics within the chip, or brightness variations between frames due to temperature and power supply voltage drifts. is there.

  The present invention is capable of performing A / D conversion at a high speed regardless of the performance of the VCO, and can suppress variations in the input / output characteristics of the PLL, thereby preventing the occurrence of vertical stripes having gain characteristics. It is an object of the present invention to provide a solid-state imaging device and a camera system that can perform the above-described processing.

  A solid-state imaging device according to a first aspect of the present invention includes a pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and a plurality of pixel units from the pixel unit in the first period and the second period. A readout unit including an AD conversion unit that performs readout of a pixel signal and performs analog-digital (AD) conversion, and a dummy pixel that supplies a dummy pixel signal corresponding to a signal level to the gate to the readout unit, The read unit counts a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to the voltage of the read signal, a precounter that counts the clock signal generated by the voltage-controlled oscillator, and an output of the precounter The pre-counter and the count operation of the counter operate in a first direction of down or up, and the first counter In this period, the pre-counter and the count operation of the counter operate in a second direction opposite to the first direction of up or down, and the first period and the second period are connected to the gate of the dummy pixel. A signal having a different level is applied in a period, and a first process of outputting a value held in the counter as a Kv value that is a ratio of an input voltage and an output frequency of the voltage controlled oscillator is performed.

  A camera system according to a second aspect of the present invention includes a solid-state imaging device, an optical system that guides incident light to a pixel region of the solid-state imaging device, and a signal processing unit that processes an output signal output from the solid-state imaging device. The solid-state imaging device includes a pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and readout of pixel signals from the pixel unit in a plurality of pixels in a first period and a second period And a read unit including an AD conversion unit that performs analog-digital (AD) conversion, and a dummy pixel that supplies a dummy pixel signal corresponding to a signal level to the gate to the read unit, and the read unit includes: A voltage controlled oscillator that generates a clock signal having a frequency corresponding to the voltage of the read signal, a precounter that counts the clock signal generated by the voltage controlled oscillator, and an output of the precounter. The pre-counter and the count operation of the counter operate in a first direction of down or up in the first period, and the pre-counter in the second period. The counting operation of the counter operates in a second direction opposite to the first direction of up or down, and signals having different levels are applied to the gates of the dummy pixels in the first period and the second period. Then, a first process of outputting the value held in the counter as a Kv value that is a ratio between the input voltage and the output frequency of the voltage controlled oscillator is performed.

In addition to being able to execute A / D conversion at a high speed regardless of the performance of the VCO, variations in the input / output characteristics of the PLL can be suppressed, and the generation of vertical stripes having gain characteristics can be prevented.

1 is a schematic block diagram illustrating a configuration example of a CMOS image sensor according to a first embodiment of the present invention. 1 is an equivalent circuit diagram illustrating a configuration example of a pixel circuit according to a first embodiment of the present invention. It is a schematic block diagram which shows the structural example of the column processing circuit which concerns on 1st Embodiment of this invention. FIG. 3 is an equivalent circuit diagram illustrating a configuration example of the VCO according to the first embodiment of the present invention. It is a figure of an example which shows the relationship between the input voltage-output frequency of VCO which concerns on 1st Embodiment of this invention. It is a figure which shows the outline | summary of the timing chart for 1H period for controlling the circuit of FIG. It is a figure which shows the relationship between the input voltage of VCO, and an output frequency. It is a figure which shows the relationship between the voltage of VSL and the output frequency of VCO at the time of fixing the reference point ( _VRST , _FAZ ) with PLL. It is a figure for demonstrating the 1st method which concerns on this embodiment. It is a figure for demonstrating the 2nd method which concerns on this embodiment. It is a figure which shows the principal part structure of the CMOS image sensor to which the 3rd method concerning this embodiment is applied. It is a figure which shows an example of the sequence which actually operates the circuit of FIG. It is a figure which shows the principal part structure of the CMOS image sensor to which the 4th method concerning this embodiment is applied. It is a figure which shows an example of the sequence which actually operates the circuit of FIG. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The description will be given in the following order.
1. 1. Configuration example of CMOS image sensor 2. Configuration example of pixel circuit 3. Configuration example of column processing circuit 4. Basic operation of the circuit of FIG. Explanation of the first method6. 6. Explanation of the second method 3. Explanation of the third method Description of the fourth method9. Configuration example of camera system

<1. Configuration example of CMOS image sensor>
FIG. 1 is a schematic block diagram showing a configuration example of a CMOS image sensor according to the first embodiment of the present invention. FIG. 1 shows a main part of the CMOS image sensor 1.

In this embodiment, a PLL loop that initializes the output frequency of the VCO is mounted so that the same output frequency (F _AZ ) is output under any condition with respect to the reference input voltage signal (V _AZ ). It is based on a CMOS image sensor.
When this CMOS image sensor or an image sensor using a VCO for AD conversion is used, it depends on temperature, power supply voltage, and process variations in the P-phase and D-phase periods.
This causes variations in the slope (Kv value) of the input voltage and output frequency of the VCO, which may result in gain noise.

The CMOS image sensor of this embodiment has a circuit configuration that employs the following method in order to suppress this gain noise.
The circuit is a circuit that prepares an all-black dummy pixel signal and a dummy pixel signal of an arbitrary known level in advance and obtains the Kv value of each column by taking the difference between the two pixels, and obtains the Kv value. As a method, the following two methods are applied.
First, as a method of reading out the dummy pixel signal of all black and the dummy pixel signal of all white, the input corresponding to all white and the signal corresponding to all black are input to the column at a specific timing to the gate of the dummy source follower circuit. This is a first method of reading.
Second, there is a second method for detecting a Kv value by putting a circuit for applying a specific voltage in the PLL loop and applying a voltage of any known level directly to the VCO as required. .
Also, an all black dummy pixel signal and an arbitrary known level (hereinafter, all white as a representative example) dummy pixel signal are read out at the head of the readout frame, a Kv value is calculated, and the result is calculated for the subsequent pixels. A third method of feeding back the readout signal is also applicable.
A Kv value obtained from the first method and the second method is held in a form that can be easily calculated in a line memory, and is multiplied by an image signal from the next readout line to remove gain noise. It is a method.
In addition to the third method, the average value, the median value, or any optimum value of the Kv value of each column obtained by the above method is obtained, and the value is supplied to the VCO of each column, or An appropriate value is fed back to other signals for controlling the VCO. As a result, the fourth method of removing the gain noise that aligns the Kv values of the VCOs in each column with the frame period is also applicable.

A CMOS image sensor 1 as a solid-state imaging device illustrated in FIG. 1 includes a pixel unit 10, a plurality of pixel circuits 11, a row selection circuit 12, a row driving circuit 13, a column processing circuit 14, and a horizontal scanning circuit 15.
The CMOS image sensor 1 includes a control circuit 16, a digital signal processing circuit (hereinafter “DPU”) 17, and an I / O unit 18.

  The pixel unit 10 is a pixel region that receives incident light. In the pixel portion 10, m (row direction) × n (column direction) pixel circuits 11 are arranged in a matrix.

Each pixel circuit 11 is arranged in a Bayer type in this embodiment. Each pixel circuit 11 is provided with any color filter of Gr (green), R (red), B (blue), and Gb (green), and detects a color corresponding to the color filter of each color.
At this time, the pixel circuit 11 converts incident light into charges (electrons) by photoelectric conversion, and outputs the charges as a voltage signal (read signal) to the output node ND1 on the vertical signal line LVSL (n).

  The row selection circuit 12 selects the pixel circuit 11 in the m-th row based on the row selection signal input from the control circuit 16.

  The row driving circuit 13 drives the m-th pixel circuit 11 based on the row selection signal input from the row driving circuit 13 and the reference clock CK input from the control circuit 16.

  The column processing circuit (reading unit) 14 has an ADC circuit 141 for each vertical column (column). The number of ADC circuits 141 is the same as the number (n) of pixel circuits 11 in the column direction.

  The ADC circuit 141 reads the voltage signal from the pixel circuit 11 for each column based on the control of the horizontal scanning circuit 15. Since the read voltage signal VSL is an analog signal, the ADC circuit 141 performs correlated double sampling (hereinafter referred to as “CDS”) processing. As a result, the analog signal is converted into a digital signal (A / D conversion).

  The horizontal scanning circuit 15 is configured by, for example, a shift register. The horizontal scanning circuit 15 sequentially selects the ADC circuit 141 of the column processing circuit 14 for each column based on the reference clock CK input from the control circuit 16.

The control circuit 16 (instruction unit) includes a control signal generation circuit (hereinafter “SG”) 161 and a PLL (Phase Locked Loop) circuit 162 for SG 161.
The SG 161 generates various control signals by phase control of the PLL circuit 162. The control signal includes a control signal SCTR (instruction signal), a count enable signal SCE (count start signal, hereinafter referred to as “CE signal SCE”), a reference clock CK, and the like, which will be described later.
The control circuit 16 outputs the reference clock CK to the row selection circuit 12, the row drive circuit 13, and the horizontal scanning circuit 15. The control circuit 16 outputs a control signal SCTR, a CE signal SCE, and the like to the column processing circuit 14.

  The DPU 17 obtains the original image data read from the pixel unit 10 by obtaining a difference between the count value in the P phase by the counter 1416 (see FIG. 3) and the count value by the counter 1416 in the D phase.

<2. Configuration example of pixel circuit>
A circuit configuration example of the pixel circuit 11 will be described with reference to FIG.
FIG. 2 is an equivalent circuit diagram showing a configuration example of the pixel circuit according to the first embodiment of the present invention. FIG. 2 shows a pixel circuit in the nth row and the mth column.

  A pixel circuit 11 illustrated in FIG. 2 includes a photoelectric conversion element 111 formed of, for example, a photodiode, a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115.

  The photoelectric conversion element 111 has the anode side grounded (GND) and the cathode side connected to the source of the transfer transistor 112. The photoelectric conversion element 111 photoelectrically converts incident light into electric charges (electrons) according to the amount of light, and accumulates the electric charges.

  As each transistor shown in FIG. 2, an n-channel insulated gate field effect transistor is employed as an example.

  The transfer transistor 112 is connected between the cathode side of the photoelectric conversion element 111 and the FD in order to transfer the charge accumulated in the photoelectric conversion element 111 to the floating diffusion FD. A transfer signal line LTRN (m) is connected to the gate of the transfer transistor 112. One end of the transfer signal line LTRN (m) is connected to the row drive circuit 13.

  The floating diffusion FD (hereinafter “FD”) is connected to the drain of the transfer transistor 112, the source of the reset transistor 113, and the gate of the amplification transistor 114.

  The reset transistor 113 is connected between the FD and the power supply voltage VDD in order to reset the potential of the FD to the power supply voltage VDD. A reset signal line LRST (m) is connected to the gate of the reset transistor 113. One end of the reset signal line LRST (m) is connected to the row drive circuit 13.

  The amplification transistor 114 has a drain connected to the power supply voltage VDD and a source connected to the drain of the selection transistor 115. The amplification transistor 114 amplifies the potential of the FD.

  The selection transistor 115 has a drain connected to the source of the amplification transistor 114, a source connected to the vertical signal line LVSL (n), and a gate connected to the selection signal line LSEL (m) so as to be connected in series with the amplification transistor 114. Has been. One end of the selection signal line LSEL (m) is connected to the row driving circuit 13.

  The source of the current source 19 and the dummy pixel transistor 20 is connected to the vertical signal line LVSL (n), and the source follower circuit is formed by the amplification transistor 114 and the current source 19. A column processing circuit 14 is connected to one end of the vertical signal line LVSL (n).

  The drain of the dummy pixel transistor 20 is connected to the signal line L20, and a dummy signal (voltage) Vdfs at a level at which a dummy pixel signal corresponding to all black or all white can be output to the vertical signal line LVSL at the gate is, for example, the control circuit 16 Supplied by

<3. Column processing circuit configuration example>
A configuration example of the column processing circuit 14 will be described with reference to FIG.
FIG. 3 is a schematic block diagram showing a configuration example of the column processing circuit according to the first embodiment of the present invention.
FIG. 3 shows the pixel circuit 11 in the m-th row connected to the vertical signal line LVSL (n), and the transfer signal line LTRN (m) and the like are omitted as appropriate.

In the column processing circuit 14 illustrated in FIG. 3, each ADC circuit 141 includes a VCO (clock signal generation unit) 1411, a pre-counter 1412, a phase comparator 1413, a charge pump (CP) 1414, and a low-pass filter (LPF) 1415. Have
Each ADC circuit 141 includes a counter (CNT) 1416 that counts the output of the pre-counter 1412, a capacitor C1, and a clamp switch SW1.

  The output node ND1 from which the voltage signal of the pixel circuit 11 is output is formed on the vertical signal line LVSL (n). The capacitor C1 is connected between the output node ND1 and the node ND2 in order to cut a DC (direct current) component of the voltage signal output to the output node ND1.

The control terminal of the VCO 1411 is connected to the node ND2 on the vertical signal line LVSL (n). The output terminal of the VCO 1411 is connected to the input terminal of the pre-counter 1412.
The output terminal of the pre-counter 1412 is connected to one input terminal of the phase comparator 1413 and the input terminal of the counter 1416. The output terminal of the counter 1416 is connected to the horizontal transfer signal line LHST.
The number N of horizontal transfer signal lines LHST is equal to the number of counters 1416. One end of each horizontal transfer signal line LHST is connected to the DPU 17 in common.

  The clamp switch SW1 is connected between the node ND2 and the node ND3 on the signal line L1.

[Configuration example of VCO 1411]
A configuration example of the VCO 1411 will be described.
FIG. 4 is an equivalent circuit diagram showing a configuration example of the VCO according to the first embodiment of the present invention.

  The VCO 1411 illustrated in FIG. 4 is a ring oscillator type VCO in the present embodiment. Specifically, the VCO 1411 includes three inverters 14111 to 14113, constant current sources 14114 to 14116 that can vary the amount of current, and a comparator 14117.

  The input terminal of the first stage inverter 14111 is connected to the control terminal CIN of the VCO 1411. This control terminal CIN is connected to a node ND2 (see FIG. 3) on the vertical signal line LVSL (n).

  Each of the inverters 14111 to 14113 is connected in a ring shape so that the output is input to the next-stage inverter. At this time, the node ND4 and the node ND5 are connected so that the output of the final-stage inverter 14113 is fed back to the first-stage inverter 14111.

  The first power supply connection terminals of the inverters 14111 to 14113 are connected to the power supply voltage VDD. The second power connection terminals of the inverters 14111 to 14113 are connected to the constant current sources 14114 to 14116.

  The input terminal of the comparator 14117 is connected to the node ND5, and the output terminal of the comparator 14117 is connected to the output terminal COUT of the VCO 1411.

[Operation example of VCO 1411]
An operation example of the VCO 1411 will be described.
When the voltage signal (analog signal) SVSL is supplied from the pixel circuit 11 to the control terminal CIN of the VCO 1411, the final-stage inverter 14113 outputs a signal having a phase opposite to that of the signal input to the first-stage inverter 14111. Since the output of the last-stage inverter 14113 is fed back to the input of the first-stage inverter 14111, the signal input to the first-stage inverter 14111 oscillates.

For example, the comparator 14117 compares the output of the inverter 14113 at the final stage with the ground potential, and outputs only a high level signal.
Accordingly, the comparator 14117 outputs the pulsed clock signal SCK to the output terminal COUT.

  The number of inverters may be an odd number in order to enable oscillation, and a suitable number (for example, five) of inverters can be connected in a ring shape.

  In this manner, the ring oscillator type VCO 1411 has a simple circuit configuration and can reduce the layout area of the VCO 1411. As a result, there is an advantage that the layout area of the column processing circuit is smaller than that using the voltage comparator.

  FIG. 5 is a diagram showing an example of the relationship between the input voltage and the output frequency of the VCO according to the first embodiment of the present invention.

As shown in FIG. 5, the VCO 1411 outputs a clock signal SCK (see FIG. 4) having a higher oscillation frequency F as the input voltage V is higher. When the input voltage V is in the range of voltages V1 to V2, the change rate KVCO (= ΔF / ΔV) of the output frequency F with respect to the input voltage V is constant.
That is, the VCO 1411 generates a clock signal SCK having a frequency F proportional to the input voltage V in the range of voltages V1 to V2.
Hereinafter, it is assumed that the input voltage V is in the range of voltages V1 to V2.

  The oscillation frequency F can be adjusted by controlling the current amount of the constant current sources 14114 to 14116 shown in FIG. In this case, the control circuit 16 outputs the control signal SCTRL to the constant current sources 14114 to 14116, whereby the current amount of the constant current sources 14114 to 14116 is varied.

As described above, the VCO 1411 outputs a clock having a frequency proportional to the voltage of the input signal. The proportionality constant becomes the Kv value (Hz / V).
The pre-counter 1412 operates with the output clock of the VCO 1411. The pre-counter 1412 also serves as a frequency divider when the switch SW1 is turned on to form a PLL loop.
The phase comparator 1413 detects the phase difference between the Ref clock signal Fref that supplies the reference frequency from the outside of the column and the output of the pre-counter 1412 and controls the charge pump 1414.
The charge pump 1414 adjusts the input voltage of the VCO 1411 according to the control of the phase comparator 1413.
The LPF 1415 converts the current value from the charge pump 1414 into a voltage.
The switch SW1 functions as a switch for selectively connecting and disconnecting the output of the LPF 1415 and the input of the VCO 1411 as necessary.
The counter 1416 receives the counter enable signal SCE and operates with the output clock from the pre-counter 1412.
The latch values in the pre-counter 1412 and counter 1416 are transferred to the DPU 17 for each column.

<4. Basic Operation of Circuit of FIG. 3>
FIG. 6 is a diagram showing an outline of a timing chart for a 1H period for controlling the circuit of FIG.
The control period shown in FIG. 6 is divided into <1> to <6>, and the operation in each period is as follows.

<1>: Pixel Reset Period The voltage Rx is applied to the reset transistor 113 to turn it on (Rx), and the gate voltage of the amplification transistor 114 is set to a specific voltage.
At this time, the voltage VSL of the vertical signal line LVSL (2-1) is also fixed to a specific value (V _P ) according to the gate voltage of the amplification transistor 114.

<2>: Pixel reset end The application of the voltage Rx is stopped, the reset transistor 113 is turned off, and switching noise at that time is mixed in the gate voltage of the amplification transistor 114.

<3> PLL Loop Period By turning on the switch SW1 and forming a PLL loop, the output frequency of the VCO 1411 converges to an arbitrarily set value (F _AZ ).
With this operation and the capacitor C1 which is a DC cut capacity, the next reset is performed regardless of the value of the vertical signal line LVSL after pixel reset (which varies from pixel to pixel due to switching noise of the reset gate), temperature, power supply voltage, and process variations. It becomes like.
That is, the output frequency of the VCO 1411 becomes a constant frequency F _AZ determined by the frequency division ratio of the pre-counter 1412 and the frequency of the Ref clock CKref.

<4>: P-phase count period The switch SW1 is turned OFF and the counter enable signal SCE is set to a high level. At this time, the value of the precounter 1412 is also reset at the same time, so that an error due to a deviation of the value of the precounter 1412 for each column does not occur.
When a certain time elapses, the counter enable signal SCE becomes low level, and the operations of the pre-counter 1412 and the counter 1416 are stopped. The count value of this time is C _P.

<5>: Transfer gate ON
The transfer gate 112 is turned on, and the charge accumulated in the photodiode 111 is transferred to the gate of the amplification transistor 114.
Since the gate voltage of the amplification transistor 114 varies due to the transferred charge, the voltage VSL of the vertical signal line LVSL also varies.

<6>: D-phase count period From the timing of <5>, wait until the voltage VSL of the vertical signal line LVSL has settled, and again set the count enable signal SCE to the high level state.
The D phase count period, the pre-counter 1412 and the counter 1416 is operated in the reverse direction to the _{C p.}
When a certain time elapses, the counter enable signal SCE becomes low level, and the operations of the pre-counter 1412 and the counter 1416 are stopped.
The count value of the time and _{C d,} the difference between _{C p} and _{C d,} the value of ΔC is held in the pre-counter 1412 and the counter 1416 internal latch circuit, according to the control of the horizontal scanning circuit 15, it is transferred to DPU17 sequentially The

FIG. 7 is a diagram showing the relationship between the input voltage and the output frequency of the VCO.
FIG. 7 shows that the ratio of the input voltage to the output frequency of the VCO 1411 varies greatly due to variations in power supply voltage, temperature, and transistor (Tr) characteristics in the chip.
Therefore, slow (Slow when range of the input signal which can be used for input in the case of not using a PLL loop for outputting a fast (Fast) frequency _{F MIN} is the lower limit that the input voltage can be used as VCO1411 condition when outputting the _{F AZ} ) Up to the input voltage of the condition.

FIG. 8 is a diagram showing the relationship between the VSL voltage and the VCO output frequency when the reference point (V _RST , F _AZ ) is fixed by the PLL.
FIG. 8 shows the relationship between the VSL voltage (not directly connected to the VCO due to the DC cut capacity) and the VCO output frequency when the PLL loop is implemented in the circuit of FIG.
The range of usable input signals is from the input voltage under the Fast condition when outputting _FAZ to the input voltage under the Fast condition when outputting the lower limit frequency _FMIN that can be used as the VCO. As shown in FIG. 7, it can be seen that the range of input signals that can be used is wider than in the case where the PLL is not used.

When the relationship between the VSL voltage and the VCO output frequency is linear, it is possible to detect the Kv value by detecting the VCO output frequency at two arbitrary VSL voltages and taking the ratio of the amount of change.
By feeding back the Kv value to the output value, it is possible to calculate the Kv value independent of temperature, power supply voltage, and process variation.
Hereinafter, characteristic first to fourth methods of the present embodiment will be described.

<5. Explanation of the first method>
9A to 9C are diagrams for explaining the first method according to the present embodiment.
9A is an equivalent circuit during the PLL loop period <3> in FIG. 6, FIG. 9B is an equivalent circuit during the P-phase count period <4> in FIG. 6, and FIG. 6 shows an equivalent circuit when the transfer gate is ON <5>.

In this first method, an arbitrary voltage is applied to the gate of the dummy pixel transistor 20 to operate as a Kv value detection circuit under the same conditions as when reading an effective pixel.
In the first method, known arbitrary signals V ′ _RST and V ′ _MIN are applied to the gate of the dummy source follower (dummy pixel transistor) 20 in each of the P-phase and D-phase count periods.
Then, according to the above-described AD conversion sequence, ΔC held in the counter is transferred as it is to the DPU 17 as a Kv value.

This first method has the following advantages.
The Kv value can be detected under the same conditions as the actual operation.
The circuit configuration inside the column can be simplified.
The Kv value between the actual pixel signal level and the VCO output frequency can be detected.

<6. Explanation of Second Method>
FIGS. 10A to 10C are diagrams for explaining the second method according to the present embodiment.
10A is an equivalent circuit during the PLL loop period <3> in FIG. 6, FIG. 10B is an equivalent circuit during the P-phase count period <4> in FIG. 6, and FIG. 6 shows an equivalent circuit when the transfer gate is ON <5>.

In the second method, the operation in the PLL loop period <3> in FIG. 6 is unnecessary.
In the second method, as shown in FIGS. 10B and 10C, the Kv value of the VCO is detected by adding the switch SW2 for applying the external voltage EV to the VCO 1411 with the switch SW1 being OFF. Is realized as a circuit.

The second method has the following advantages.
The method of FIG. 9 that passes through the DC cut capacitor C1 is not affected by switching noise or the like.
Therefore, it is not necessary to perform CDS, and by simply applying two external input voltages, the respective output frequencies can be detected directly, which is less time consuming than in the case of FIG. 9 where a PLL loop needs to be created.
Since it does not go through the dummy pixel transistor, the Kv value of the VCO alone can be detected.

  Regarding the method of feeding back the Kv value acquired by the first method and the second method to the actual output value, two methods, the third method and the fourth method, are shown below.

<7. Explanation of the third method>
FIG. 11 is a diagram showing a main configuration of a CMOS image sensor to which the third method according to the present embodiment is applied.
A CMOS image sensor 1A to which the third method is applied has a line memory (SRAM) 30 mounted inside or outside the sensor, and the Kv value obtained by the first and second methods can be easily calculated arbitrarily. (For example, in the form of several times the standard Kv value).
When an effective pixel row is read, variation due to the Kv value can be corrected by passing the output value of each column and the value held in the line memory through an arithmetic unit.

FIG. 12 is a diagram showing an example of a sequence for actually operating the circuit of FIG.
As shown in FIG. 12, in the third method, horizontal transfer is performed at the H timing next to the H timing for vertical transfer of the Kv detection signal, and the Kv detection signal is taken into the DPU 17.
Therefore, after taking the Kv value into the operator 31 and the line memory 30, the correction value (for example, the reference Kv value divided by the Kv value of each column) is applied to the signal from the pixel in the next line. By applying the correction, it is possible to correct the variation of the Kv value.

The third method has the following advantages.
Since the correction can be made for each column, the gain vertical stripe can be corrected.
Since it is a process inside the DPU, it can be reflected in the next frame in which the Kv value is detected.

<8. Explanation of the fourth method>
FIG. 13 is a diagram showing a main configuration of a CMOS image sensor to which the fourth method according to the present embodiment is applied.
As shown in FIG. 13, in the fourth method. On the premise that process variation for each column does not become a problem, an average value, a median value, or an arbitrary set value is calculated from the detected Kv value of the column array, and the VCO 1411 is controlled based on the calculated value.
Here, the VCO 1411 is controlled as follows.
For example, when the VCO is a ring oscillator composed of an odd number of inverters, the gm of the transistor Tr in the inverter is adjusted by controlling the bias current amount of each inverter or the size of the transistor Tr of the inverter.
Alternatively, the Kv value of the VCO can be adjusted by adjusting the value of the load capacity connected to the input / output of the inverter.

FIG. 14 is a diagram showing an example of a sequence for actually operating the circuit of FIG.
As shown in FIG. 14, in the fourth method, the control value of the Kv value of the VCO 1411 is calculated from a part (or all) of the 1-H array of Kv detection signals input up to the DPU 17.
By reflecting the control value on the Kv value control circuit 40 in the next line and directly correcting the Kv value of the VCO, correction can be applied when AD converting the pixel signal of this line.

The fourth method has the following advantages.
No line memory is required Since correction is applied at the stage of AD conversion by the column, it is not necessary to perform complicated arithmetic processing in the subsequent stage.

As described above, according to the present embodiment, the following effects can be obtained.
Temporal and spatial variations in kv values that can be considered as problems of an image sensor having an AD converter using a VCO can be suppressed.
Manufacturing an image sensor that produces an image with no noise or screen flicker, in which the vertical stripe noise in the output image, which seems to be generated by kv value variation, and the brightness variation of each frame is reduced. Can do.
According to the present embodiment, noise reduction can be realized at the stage of the image sensor, so that it is not necessary to separately install a correction circuit in a circuit or block subsequent to the chip, and the circuit configuration can be simplified. it can.
For this reason, it is possible to contribute to reduction of the chip area, power consumption, and time lag of signal processing in the signal processing system at the subsequent stage.
According to this embodiment, since the influence of the Kv value due to process variations is reduced, an improvement in yield can be expected.
Also. Since the influence of the Kv value due to variations in temperature and power supply voltage is reduced, it can be adapted to applications under severe conditions.
In addition, this embodiment is realized by a combination of circuits and an operation sequence that can be manufactured by a conventional technique, and it is easy to mount the present invention on a sensor in terms of circuit scale.
According to the present embodiment, an imaging device having an AD converter using a VCO capable of high-speed and high-precision AD conversion can be put into practical use rather than a successive approximation AD converter using a ramp wave and a comparator. I can expect.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

<9. Configuration example of camera system>
FIG. 15 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 15, the camera system 200 includes an imaging device 210 to which the solid-state imaging device 100 according to the present embodiment can be applied.
The camera system 200 includes, for example, a lens 220 that forms incident light (image light) on an imaging surface as an optical system that guides incident light to a pixel region of the imaging device 210 (forms a subject image).
The camera system 200 further includes a drive circuit (DRV) 230 that drives the imaging device 210 and a signal processing circuit (PRC) 240 that processes an output signal of the imaging device 210.

  The drive circuit 230 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 210, and drives the imaging device 210 with a predetermined timing signal. .

The signal processing circuit 240 performs predetermined signal processing on the output signal of the imaging device 210.
The image signal processed by the signal processing circuit 240 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. Further, the image signal processed by the signal processing circuit 240 is displayed as a moving image on a monitor including a liquid crystal display or the like.

  As described above, a high-precision camera can be realized by mounting the above-described solid-state imaging device 100 as the imaging device 210 in an imaging apparatus such as a digital still camera.

  DESCRIPTION OF SYMBOLS 1 ... CMOS image sensor, 10 ... Pixel part, 11 ... Pixel circuit, 12 ... Row selection circuit, 13 ... Row drive circuit, 14 ... Column processing circuit, 15 ... Horizontal scanning circuit, 16 ... Control circuit, 17 ... DPU, 19 DESCRIPTION OF SYMBOLS ... Current source, 20 ... Dummy pixel transistor, 111 ... Photoelectric conversion element, 112 ... Transfer transistor, 113 ... Reset transistor, 114 ... Amplification transistor, 115 ... Selection transistor, 141 ... ADC circuit, 1411 ... VCO, 1412 ... Pre-counter, 1413 ... Phase comparator, 1414 ... Charge pump, 1415 ... Low pass filter (LPF), 1416 ... Counter, 200 ... Camera system, 210 ... Imaging device, 320 ... Lens, 230 ... Drive circuit, 240: Signal processing circuit.

Claims (7)

A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A readout unit including an AD conversion unit that performs readout of pixel signals from the pixel unit in a plurality of pixel units in the first period and the second period and performs analog-digital (AD) conversion;
A dummy pixel that supplies a dummy pixel signal corresponding to the signal level to the gate to the readout unit,
The readout section is
A voltage controlled oscillator that generates a clock signal having a frequency according to the voltage of the read signal;
A pre-counter that counts the clock signal generated by the voltage-controlled oscillator;
A counter for counting the output of the pre-counter,
In the first period, the count operation of the pre-counter and the counter operates in a first direction of down or up, and in the second period, the count operation of the pre-counter and the counter is up or Operates in a second direction opposite to the first direction of down;
Signals having different levels are applied to the gates of the dummy pixels in the first period and the second period, and the value held in the counter is set as a Kv value that is a ratio of the input voltage to the output frequency of the voltage controlled oscillator. A solid-state imaging device that performs the first process of output. The readout section is
The solid-state imaging device according to claim 1, wherein a signal corresponding to all white and a signal corresponding to all black are applied to the gate of the dummy pixel. The readout section is
The solid-state imaging device according to claim 1, wherein the second process of obtaining the Kv value by directly applying a voltage of an arbitrary known level to the voltage-controlled oscillator is possible. The readout section is
4. A dummy pixel signal corresponding to all black and a dummy pixel signal of an arbitrary known level are read out at the beginning of a readout frame, a Kv value is calculated, and the calculation result is fed back to a subsequent pixel readout signal. The solid-state imaging device described. The readout section is
Signals having different levels are applied to the gates of the dummy pixels in the first period and the second period, and the value held in the counter is set as a Kv value that is a ratio of the input voltage to the output frequency of the voltage controlled oscillator. A first process to output;
A second process for obtaining the Kv value by directly applying a voltage of any known level to the voltage controlled oscillator;
5. The gain noise is removed by holding the Kv value obtained in the first process and the second process in a line memory, and then multiplying it with an image signal in the read row and thereafter. The solid-state image sensor as described in any one of these. The readout section is
Signals having different levels are applied to the gates of the dummy pixels in the first period and the second period, and the value held in the counter is set as a Kv value that is a ratio of the input voltage to the output frequency of the voltage controlled oscillator. A first process to output;
A second process for obtaining the Kv value by directly applying a voltage of any known level to the voltage controlled oscillator;
By obtaining the weapon value, median value, or any optimum value of the Kv value obtained in the first process and the second process, and feeding back the obtained value to the voltage-controlled oscillator in each column 5. The solid-state imaging device according to claim 1, wherein gain noise is removed by aligning the Kv values of the voltage-controlled oscillators in each column with a frame period. A solid-state image sensor;
An optical system for guiding incident light to the pixel region of the solid-state imaging device;
A signal processing unit that processes an output signal output from the solid-state imaging device,
The solid-state imaging device is
A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A readout unit including an AD conversion unit that performs readout of pixel signals from the pixel unit in a plurality of pixel units in the first period and the second period and performs analog-digital (AD) conversion;
A dummy pixel that supplies a dummy pixel signal corresponding to the signal level to the gate to the readout unit,
The readout section is
A voltage controlled oscillator that generates a clock signal having a frequency according to the voltage of the read signal;
A pre-counter that counts the clock signal generated by the voltage-controlled oscillator;
A counter for counting the output of the pre-counter,
In the first period, the count operation of the pre-counter and the counter operates in a first direction of down or up, and in the second period, the count operation of the pre-counter and the counter is up or Operates in a second direction opposite to the first direction of down;
Signals having different levels are applied to the gates of the dummy pixels in the first period and the second period, and the value held in the counter is set as a Kv value that is a ratio of the input voltage to the output frequency of the voltage controlled oscillator. A camera system that performs a first process of output.

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