JP2012043822A - Semiconductor device - Google Patents
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Abstract
Description
本発明は、半導体デバイスに関する。 The present invention relates to a semiconductor device.
半導体デバイスにおいては、これまで、基板上に半導体チップを平面的に配置し、その間を配線で接続する方法がとられてきた。しかし、この方法では、実装面積が半導体チップの数とともに増加するとともに、配線長も増加してしまうので、半導体デバイスの小型大容量化、高性能化及び低消費電力化を実現することが困難である。微細化技術が極限まで進んだ現状では、半導体チップの微細化、小型化をとおして、大容量化、高性能化及び低消費電力化を実現することは、限界に来ている。 Conventionally, in semiconductor devices, a method has been employed in which semiconductor chips are arranged in a plane on a substrate and connected between them by wiring. However, with this method, the mounting area increases with the number of semiconductor chips, and the wiring length also increases. Therefore, it is difficult to realize a small, large capacity, high performance and low power consumption of the semiconductor device. is there. Under the present circumstances where the miniaturization technology has advanced to the limit, it has reached the limit to realize large capacity, high performance and low power consumption through miniaturization and miniaturization of semiconductor chips.
そこで、半導体チップを積層し、チップ間を貫通電極で接続するいわゆるＴＳＶ（Through Silicon Via）方式に係る三次元配置の半導体デバイスの開発が進められている。ＴＳＶ技術を使えば、大量の機能を小さな占有面積の中に詰め込めるようになるし、また、素子同士の重要な電気経路が劇的に短く出来るために、処理の高速化が導かれる。 In view of this, development of a three-dimensionally arranged semiconductor device according to a so-called TSV (Through Silicon Via) method in which semiconductor chips are stacked and the chips are connected by through electrodes is underway. If TSV technology is used, a large amount of functions can be packed in a small occupied area, and an important electrical path between elements can be dramatically shortened, leading to high processing speed.
ＴＳＶ方式に係る三次元配置の半導体デバイスを実現する代表的な技術は、めっき技術を適用して貫通電極を形成するめっき方法、及び、例えば、特許文献１に開示されているように、微細孔を持つシリコン基板を、真空圧に減圧した真空チャンバー内で溶融金属槽に挿入し、シリコン基板が溶融金属とほぼ同じ温度に達した後、真空チャンバー内を例えば大気圧以上に加圧して、溶融金属を微細孔に充填し、硬化させて、溶融凝固導体でなる貫通導体を形成する溶融金属充填方法である。 Typical techniques for realizing a three-dimensionally arranged semiconductor device according to the TSV method are a plating method for forming a through electrode by applying a plating technique, and, for example, as disclosed in Patent Document 1, Insert a silicon substrate with a molten metal tank in a vacuum chamber that has been depressurized to a vacuum pressure. After the silicon substrate reaches almost the same temperature as the molten metal, the vacuum chamber is pressurized to, for example, atmospheric pressure or higher to melt it. This is a molten metal filling method in which a fine hole is filled and cured to form a through conductor made of a molten solidified conductor.
ところで、ＴＳＶ技術を採用して、貫通電極を形成するには、既に、半導体基板（ウエハ）に形成された半導体回路の特性に悪影響を与えるような応力を持たないことが、極めて重要である。 By the way, in order to form a through electrode by employing the TSV technique, it is extremely important that the semiconductor substrate (wafer) does not have a stress that adversely affects the characteristics of the semiconductor circuit formed on the semiconductor substrate (wafer).
ところが、上述した従来技術の何れも、縦導体における結晶成長などに伴う応力による半導体回路の特性変動について気づいておらず、検討もなされていない。このため、半導体基板に既に形成されている半導体回路の特性を劣化させることがあった。 However, none of the above-described prior arts has noticed or studied the characteristic fluctuation of the semiconductor circuit due to stress accompanying crystal growth in the vertical conductor. For this reason, the characteristics of the semiconductor circuit already formed on the semiconductor substrate may be deteriorated.
本発明の課題は、縦導体の応力による半導体回路の特性劣化を抑制した半導体デバイスを提供することである。 The subject of this invention is providing the semiconductor device which suppressed the characteristic deterioration of the semiconductor circuit by the stress of a vertical conductor.
上述した課題を解決するため、本発明に係る半導体デバイスは、半導体基板と、縦導体とを含み、前記縦導体は、前記半導体基板の厚み方向に設けられた微細孔を満たし、複数の金属／合金結晶組織からなる。前記金属／合金結晶組織の少なくとも一種は、ナノサイズの第１結晶組織である。この第１結晶組織は、前記貴金属／合金結晶組織の少なくとも他の一種である第２結晶組織と、ナノコンポジット結晶構造を構成する。 In order to solve the above-described problems, a semiconductor device according to the present invention includes a semiconductor substrate and a vertical conductor, and the vertical conductor fills a fine hole provided in the thickness direction of the semiconductor substrate, and a plurality of metal / It consists of an alloy crystal structure. At least one of the metal / alloy crystal structures is a nano-sized first crystal structure. This first crystal structure constitutes a nanocomposite crystal structure with a second crystal structure which is at least another kind of the noble metal / alloy crystal structure.
上述したように、本発明では、縦導体が、ナノコンポジット結晶構造を有し、ナノコンポジット結晶構造を構成する第１結晶組織及び第２結晶組織の少なくとも一方は、ナノサイズであるから、大きさが、ナノレベルに制限された組織（結晶）を含むことの効果として、縦導体に発生する応力が小さくなる。しかも、ナノコンポジット結晶構造には、縦導体の等軸晶化を促進する働きある。 As described above, in the present invention, the longitudinal conductor has a nanocomposite crystal structure, and at least one of the first crystal structure and the second crystal structure constituting the nanocomposite crystal structure is nano-sized. However, as an effect of including a structure (crystal) restricted to the nano level, the stress generated in the vertical conductor is reduced. Moreover, the nanocomposite crystal structure has a function of promoting equiaxed crystallization of the vertical conductor.
上述したナノコンポジット結晶構造の有する特有の特性により、半導体基板（ウエハ）に形成された半導体回路の特性劣化が抑制される。また、半導体基板に亀裂・クラックが入るのを抑制することもできる。 The characteristic characteristic of the nanocomposite crystal structure described above suppresses the characteristic deterioration of the semiconductor circuit formed on the semiconductor substrate (wafer). Moreover, it can also suppress that a semiconductor substrate cracks.
本発明において、ナノコンポジット結晶構造とは、基本的には、結晶粒内にナノ粒子を分散（粒内ナノコンポジット結晶構造）させるか、粒界にナノ粒子を分散（粒界ナノコンポジット結晶構造）させたものをいう。本発明において、「ナノ」とは、１μｍ未満のサイズをいう。 In the present invention, the nanocomposite crystal structure basically means that nanoparticles are dispersed in crystal grains (intragranular nanocomposite crystal structure) or nanoparticles are dispersed in grain boundaries (grain boundary nanocomposite crystal structure). This is what I let you do. In the present invention, “nano” means a size of less than 1 μm.
本発明の他の目的、構成及び利点については、添付図面を参照し、更に詳しく説明する。但し、添付図面は、単なる例示に過ぎない。 Other objects, configurations and advantages of the present invention will be described in more detail with reference to the accompanying drawings. However, the attached drawings are merely examples.
図１を参照すると、縦導体３は半導体基板１の一面からその厚み方向に延びる微細孔３０の内部に充填されている。半導体基板１は、Ｓｉ、ＳｉＣ又はＳＯＩ等で構成され、その内部に半導体回路２が形成されている。半導体回路２は、縦導体３の側方に微小間隔をおいて備えられている。 Referring to FIG. 1, the vertical conductor 3 is filled in a fine hole 30 extending from one surface of the semiconductor substrate 1 in the thickness direction. The semiconductor substrate 1 is made of Si, SiC, SOI, or the like, and a semiconductor circuit 2 is formed therein. The semiconductor circuit 2 is provided on the side of the vertical conductor 3 at a minute interval.
半導体基板１に設けられた微細孔３０の内側面の全面に、絶縁膜５が付着されており、絶縁膜５によって囲まれた微細孔３０の内側に、縦導体３が配置されている。絶縁膜５は、微細孔３０の内壁面を酸化又は窒化して得られた絶縁膜であってもよいし、無機絶縁材料、例えばガラスを主成分とし、必要に応じてセラミック成分を含有させたものによって形成してもよい。 The insulating film 5 is attached to the entire inner surface of the micro hole 30 provided in the semiconductor substrate 1, and the vertical conductor 3 is disposed inside the micro hole 30 surrounded by the insulating film 5. The insulating film 5 may be an insulating film obtained by oxidizing or nitriding the inner wall surface of the fine hole 30, or an inorganic insulating material such as glass as a main component, and a ceramic component as necessary. You may form by things.
図１には、簡単な構成の半導体基板が示されているのみであるが、実際には、半導体デバイスの種類に応じた機能、及び、構造を満たすべく、より複雑な構造がとられる。半導体基板１は、ウエハであってもよいし、ウエハから切り出されたチップであってもよい。更に、単板であってよいし、複数枚を積層した積層体であってもよい。 Although only a semiconductor substrate having a simple configuration is shown in FIG. 1, a more complicated structure is actually taken to satisfy the function and structure according to the type of semiconductor device. The semiconductor substrate 1 may be a wafer or a chip cut out from the wafer. Furthermore, it may be a single plate or a laminate in which a plurality of sheets are laminated.
縦導体３は、μｍ単位の間隔をおいて、例えばマトリクス状などに多数設けられる。縦導体３によって満たされた微細孔３０は、一般には、貫通孔、非貫通孔（盲孔）又はビア・ホールと称される。この微細孔３０は、限定するものではないが、例えば、孔径６０μm以下である。 A large number of vertical conductors 3 are provided, for example, in a matrix at intervals of μm. The fine hole 30 filled with the vertical conductor 3 is generally referred to as a through hole, a non-through hole (blind hole), or a via hole. The fine holes 30 are not limited, but have a hole diameter of 60 μm or less, for example.
縦導体３は、複数種の金属／合金結晶組織からなり、この金属／合金結晶組織の少なくとも一種は、図２に模式的に示すように、ナノサイズの第２結晶組織３０２であり、貴金属／合金結晶組織の少なくとも他の一種である第１結晶組織３０１と、ナノコンポジット結晶構造を構成する。 The vertical conductor 3 is composed of a plurality of types of metal / alloy crystal structures, and at least one of the metal / alloy crystal structures is a nano-sized second crystal structure 302 as schematically shown in FIG. The first crystal structure 301 which is at least another kind of the alloy crystal structure and the nanocomposite crystal structure are configured.
上述したように、本発明では、縦導体３が、ナノコンポジット結晶構造を有し、第１結晶組織３０１及び第２結晶組織３０２の少なくとも一方、例えば、第２結晶組織３０２は、ナノサイズであるから、大きさが、ナノレベルに制限された組織（結晶）を含むことの効果として、縦導体３に発生する応力が小さくなる。しかも、ナノコンポジット結晶構造には、縦導体３の等軸晶化を促進する働きもある。等軸晶は、均一な等軸結晶であって、その特性が等方的であるゆえに、応力低減に資する。 As described above, in the present invention, the vertical conductor 3 has a nanocomposite crystal structure, and at least one of the first crystal structure 301 and the second crystal structure 302, for example, the second crystal structure 302 is nano-sized. Therefore, the stress generated in the vertical conductor 3 is reduced as an effect of including a structure (crystal) whose size is limited to the nano level. Moreover, the nanocomposite crystal structure also has a function of promoting equiaxed crystallization of the vertical conductor 3. An equiaxed crystal is a uniform equiaxed crystal, and its characteristics are isotropic, which contributes to stress reduction.
ナノコンポジット結晶構造の上述した特性により、半導体基板１（ウエハ）に形成された半導体回路２の特性劣化が抑制される。また、半導体基板１における亀裂・クラックの発生なども抑制される。 Due to the above-described characteristics of the nanocomposite crystal structure, deterioration of characteristics of the semiconductor circuit 2 formed on the semiconductor substrate 1 (wafer) is suppressed. In addition, the occurrence of cracks and cracks in the semiconductor substrate 1 is also suppressed.
図２に示す形態は、第１結晶組織３０１の内部に、ナノサイズである第２結晶組織３０２を分散させたものである。このほか、図３〜図５に模式的に示すように、第１結晶組織３０１の粒界に、ナノサイズである第２結晶組織３０２を分散させたもの（図３）、これとは逆に、第２結晶組織３０２の粒界に、ナノサイズである第１結晶組織３０１を分散させたもの、第１結晶組織３０１の内部に、ナノサイズである第２結晶組織３０２を分散させるとともに、第１結晶組織３０１の粒界に、ナノサイズである第２結晶組織３０２を分散させたもの（図４）、第１結晶組織３０１及び第２結晶組織３０２の両者がナノサイズであるもの（図５）などの形態をとることができる。図示は省略するけれども、図２〜図５の形態を組み合せたものであってもよい。さらに、縦導体３を構成する複数種の金属／合金結晶組織において、上述した第１結晶組織３０１及び第２結晶組織３０２によるナノコンポジット結晶構造とは、異なる他種のナノコンポジット結晶構造を形成させてもよい。 In the form shown in FIG. 2, the second crystal structure 302 having a nano size is dispersed inside the first crystal structure 301. In addition, as schematically shown in FIGS. 3 to 5, a nano-sized second crystal structure 302 is dispersed in the grain boundaries of the first crystal structure 301 (FIG. 3), on the contrary. The first crystal structure 301 having a nano size is dispersed in the grain boundaries of the second crystal structure 302, the second crystal structure 302 having a nano size is dispersed in the first crystal structure 301, and the first A nano-sized second crystal structure 302 is dispersed in the grain boundary of one crystal structure 301 (FIG. 4), and both the first crystal structure 301 and the second crystal structure 302 are nano-sized (FIG. 5). ) And the like. Although illustration is omitted, it may be a combination of the forms shown in FIGS. Further, in the plurality of types of metal / alloy crystal structures constituting the vertical conductor 3, another type of nanocomposite crystal structure different from the nanocomposite crystal structure formed by the first crystal structure 301 and the second crystal structure 302 described above is formed. May be.
第１結晶組織３０１及び第２結晶組織３０２は、金属成分が部分的に重なっていてもよいし、全く異なっていてもよい。第１結晶組織３０１及び第２結晶組織３０２の別は、含まれている金属元素の融点の違いや、共晶化や合金化の有無などによって生まれる。また、このナノコンポジット結晶構造は、ナノ金属／合金粒子の溶融充填方法や、スパッタ併用めっき法などによって実現することができる。 The first crystal structure 301 and the second crystal structure 302 may partially overlap with each other or may be completely different. The distinction between the first crystal structure 301 and the second crystal structure 302 is caused by the difference in melting point of the contained metal elements, the presence or absence of eutecticization or alloying, and the like. Moreover, this nanocomposite crystal structure can be realized by a melt-filling method of nanometal / alloy particles, a sputtering combined plating method, or the like.
第１結晶組織３０１及び第２結晶組織３０２の代表的な例は、非共晶組織と共晶組織の組み合わせである。共晶は、合金などの結晶組織の１つであって、たとえば２種類の金属Ａと金属Ｂを溶解して合金をつくる場合、金属Ａと金属Ｂの比率が金属Ａに対する金属Ｂの固溶限（固溶体をつくる限界）までの範囲や、金属Ｂに対する金属Ａの固溶限までの範囲にないと、合金は、それぞれ違った成分比の固溶体の結晶がまじりあったものになり、共晶組織を構成する。金属Ａと金属Ｂとが、上記条件を満たさない場合や、溶解温度が共晶点まで達しなかった場合には、本来、共晶となりえる金属Ａ，Ｂであっても、非共晶組織となる。非共晶組織は、共晶化のための金属元素とは異なる第３の金属元素を添加することによっても得られる。 A typical example of the first crystal structure 301 and the second crystal structure 302 is a combination of a non-eutectic structure and a eutectic structure. A eutectic is one of crystal structures of an alloy or the like. For example, when an alloy is formed by melting two types of metal A and metal B, the ratio of metal A to metal B is a solid solution of metal B to metal A. If it is not within the range up to the limit (the limit for forming a solid solution) or the range up to the solid solution limit of metal A relative to metal B, the alloy will be a mixture of solid solution crystals with different component ratios. Configure the organization. When the metal A and the metal B do not satisfy the above conditions, or when the melting temperature does not reach the eutectic point, even if the metals A and B are originally eutectic, Become. The non-eutectic structure can also be obtained by adding a third metal element different from the metal element for eutecticization.
第１結晶組織３０１を非共晶組織とした場合、第２結晶組織３０２は共晶組織である。この組み合わせを前提としたナノコンポジット結晶構造には、図２〜図５を参照すると明らかなように、
（ａ）非共晶組織の内部に共晶組織でなるナノ粒子を分散させたもの、（ｂ）非共晶組織の粒界に共晶組織でなるナノ粒子を分散させたもの、（ｃ）共晶組織の粒界に非共晶組織でなるナノ粒子を分散させたもの、（ｄ）非共晶組織の内部に共晶組織でなるナノ粒子を分散させるとともに、非共晶組織の粒界に共晶組織でなるナノ粒子を分散させたもの、（ｅ）共晶組織及び非共晶組織が、共にナノサイズであるもの
などが含まれる。
When the first crystal structure 301 is a non-eutectic structure, the second crystal structure 302 is a eutectic structure. As shown in FIGS. 2 to 5, the nanocomposite crystal structure based on this combination is clearly shown.
(A) A nanoparticle having a eutectic structure dispersed inside a non-eutectic structure, (b) A nanoparticle having a eutectic structure dispersed in a grain boundary of the non-eutectic structure, (c) Nanoparticles having non-eutectic structures dispersed in eutectic grain boundaries, (d) Nanoparticles having eutectic structures dispersed inside non-eutectic structures, and grain boundaries of non-eutectic structures (E) those in which both the eutectic structure and the non-eutectic structure are nano-sized.
ナノコンポジット結晶構造は、縦導体３の全体にわたっていてもよいし、部分的に存在してもよい。例えば、微細孔３０の内壁面又は絶縁膜５の内壁面と接触する縦導体３の外周に部分的に存在していてもよい。 The nanocomposite crystal structure may extend over the entire longitudinal conductor 3 or may exist partially. For example, it may be partially present on the outer periphery of the vertical conductor 3 in contact with the inner wall surface of the fine hole 30 or the inner wall surface of the insulating film 5.
縦導体３が、共晶組織と、非共晶組織とによるナノコンポジット結晶構造を有し、共晶組織及び非共晶組織の少なくとも一方はナノサイズである場合も、結晶の大きさが、ナノレベルに制限された結晶を含むことの効果として、縦導体３に発生する応力が小さくなるから、半導体回路２の特性に悪影響を与える不具合を抑制する方向に働く。半導体基板１に亀裂・クラックが発生するのを抑制する働きも生じる。 Even when the longitudinal conductor 3 has a nanocomposite crystal structure of a eutectic structure and a non-eutectic structure, and at least one of the eutectic structure and the non-eutectic structure is nano-sized, the size of the crystal is nano As an effect of including a crystal limited in level, since the stress generated in the vertical conductor 3 is reduced, it works in the direction of suppressing a problem that adversely affects the characteristics of the semiconductor circuit 2. The function of suppressing the generation of cracks or cracks in the semiconductor substrate 1 also occurs.
しかも、縦導体３を構成するナノコンポジット結晶構造が、共晶組織を含んでいるから、縦導体３と、μｍオーダの微細孔３０の内壁面との間に空隙や空洞を生じにくくなるし、縦導体３に金属成分の偏析も生じにくい。 Moreover, since the nanocomposite crystal structure constituting the vertical conductor 3 includes a eutectic structure, it becomes difficult to generate voids and cavities between the vertical conductor 3 and the inner wall surface of the micropore 30 on the order of μm. Segregation of metal components hardly occurs in the vertical conductor 3.
縦導体３は、好ましくは、Ｂｉを含むことができる。更に、Ｂｉに対して共晶組成を構成しえるもの、例えば、Ｓｎ、Ｃｕ、Ａｇ、Ａｌ、Ｚｎ又はＡｕの群から選択された少なくとも１種を含むことができる。 The vertical conductor 3 can preferably contain Bi. Furthermore, it can include at least one selected from the group consisting of Sn, Cu, Ag, Al, Zn or Au, which can constitute a eutectic composition with respect to Bi.
上述した金属元素の組み合わせにより、二元以上の多元共晶組織を実現することができる。そのような共晶組成は、すでに知られている。例えば、二元共晶組成としては、Ｂｉ：９７．５質量％、Ａｇ：２．５質量％、共晶温度２６２℃のＢｉ−Ａｇ系や、Ｂｉ：８９質量％、Ａｇ：１１質量％、共晶温度２４１℃のＢｉ−Ａｇ系が知られている。また、三元共晶組成としては、Ｓｎ−１Ａｇ−５７Ｂｉ共晶(融点：１３８℃)などが知られている。その他の二元以上の金属を用いた場合の共晶組成及び融点についても、既に知られているものが、多数存在する。知られていないものであっても、既に確立しているCALPHAD（Computer Calculation of Phase Diagram）法等を用いて算出することができる。そのための具体的なソフトウエアも知られている（例えば、JMatPro）。 By combining the above-described metal elements, a binary or higher multi-eutectic structure can be realized. Such eutectic composition is already known. For example, as the binary eutectic composition, Bi: 97.5% by mass, Ag: 2.5% by mass, Bi-Ag system having a eutectic temperature of 262 ° C., Bi: 89% by mass, Ag: 11% by mass, A Bi-Ag system having a eutectic temperature of 241 ° C. is known. Moreover, as a ternary eutectic composition, Sn-1Ag-57Bi eutectic (melting point: 138 degreeC) etc. are known. There are many known eutectic compositions and melting points when other two or more metals are used. Even if it is not known, it can be calculated by using an already established CALPHAD (Computer Calculation of Phase Diagram) method or the like. Specific software for this purpose is also known (for example, JMatPro).
上述したような金属元素の組み合わせであっても、共晶組成から外れた領域、共晶点を履歴しない温度条件では、非共晶組成が生じるので、共晶組織及び非共晶組織を同時に実現することができる。 Even in the combination of metal elements as described above, a non-eutectic composition occurs at a temperature that does not record the eutectic point in a region that is out of the eutectic composition. can do.
図６は、半導体デバイスの別の実施形態を示している。図６を参照すると、絶縁膜５の内側面に、第１縦導体３１が付着されている。そして、第１縦導体３１によって囲まれた空間内に、第１縦導体３１と共に縦導体３を構成する第２縦導体３２が配置されており、第１縦導体３１及び第２縦導体３２の少なくとも一方が、ナノコンポジット結晶構造を有する。 FIG. 6 illustrates another embodiment of a semiconductor device. Referring to FIG. 6, the first vertical conductor 31 is attached to the inner surface of the insulating film 5. A second vertical conductor 32 that constitutes the vertical conductor 3 together with the first vertical conductor 31 is disposed in a space surrounded by the first vertical conductor 31, and the first vertical conductor 31 and the second vertical conductor 32 At least one has a nanocomposite crystal structure.
図７及び図８は、本発明に係る半導体基板１のＳＥＭ像であり、半導体基板１に穿孔された微細孔３０の内部に、縦導体３が充填されている。図７及び図８をみると明らかなように、第１結晶組織３０１に、ナノサイズを有する第２結晶組織３０２が分散されて、ナノコンポジット結晶構造を構成していることが分かる。 7 and 8 are SEM images of the semiconductor substrate 1 according to the present invention, in which the vertical conductors 3 are filled in the fine holes 30 formed in the semiconductor substrate 1. As is apparent from FIGS. 7 and 8, it can be seen that the second crystal structure 302 having a nano size is dispersed in the first crystal structure 301 to form a nanocomposite crystal structure.
次に、図９を参照すると、任意数の半導体デバイスＡ１〜Ａ６を、順次に積層した三次元配置半導体デバイスが図示されている。半導体デバイスＡ１〜Ａ６のそれぞれは、積層界面において接合されている。図では、縦導体３は、半導体デバイスＡ１〜Ａ６の間において、全て連なっているが、回路構成によっては連ならない場合もあり得る。最外側の半導体デバイスＡ１、Ａ６には、バンプ（取出電極）６０〜６９が設けられる。この多層積層構造は、ＴＳＶ技術を適用した三次元半導体デバイスの一種である
更に、図１０は、集積回路ＬＳＩ１、ＬＳＩ２と、本発明に係る半導体デバイスＡ１〜Ａ６とを組み合せた三次元半導体デバイスを示している。本発明において、集積回路ＬＳＩと称する場合、小規模集積回路、中規模集積回路、大規模集積回路、超大規模集積回路ＶＬＳＩ、ＵＬＳＩ等の全てを含む。
Next, referring to FIG. 9, a three-dimensionally arranged semiconductor device in which an arbitrary number of semiconductor devices A1 to A6 are sequentially stacked is illustrated. Each of the semiconductor devices A1 to A6 is bonded at the stacked interface. In the drawing, the vertical conductors 3 are all connected between the semiconductor devices A1 to A6, but may not be connected depending on the circuit configuration. Bumps (extraction electrodes) 60 to 69 are provided on the outermost semiconductor devices A1 and A6. This multilayer stacked structure is a kind of three-dimensional semiconductor device to which the TSV technology is applied. Further, FIG. 10 shows a three-dimensional semiconductor device in which the integrated circuits LSI1 and LSI2 and the semiconductor devices A1 to A6 according to the present invention are combined. Show. In the present invention, the term “integrated circuit LSI” includes all of small scale integrated circuits, medium scale integrated circuits, large scale integrated circuits, ultra large scale integrated circuits VLSI, ULSI, and the like.
図１０を参照すると、第１集積回路ＬＳＩ１と、第２集積回路ＬＳＩ２との間に、本発明に係る半導体デバイスＡ１〜Ａ６が実装されている。この実施の形態では、半導体デバイスＡ１〜Ａ６のうち、半導体デバイスＡ１はインターポーザとして用いられている。 Referring to FIG. 10, semiconductor devices A1 to A6 according to the present invention are mounted between a first integrated circuit LSI1 and a second integrated circuit LSI2. In this embodiment, of the semiconductor devices A1 to A6, the semiconductor device A1 is used as an interposer.
以上、好ましい実施例を参照して本発明の内容を具体的に説明したが、本発明の基本的技術思想及び教示に基づいて、当業者であれば、種々の変形形態及び説明されない他の適用技術分野を想到しえることは自明である。 Although the contents of the present invention have been specifically described with reference to the preferred embodiments, various modifications and other applications not described will be apparent to those skilled in the art based on the basic technical idea and teachings of the present invention. It is obvious that the technical field can be conceived.
１ 半導体基板
２ 半導体回路
３ 縦導体
1 Semiconductor substrate
2 Semiconductor circuit
3 Vertical conductor
上述した課題を解決するため、本発明に係る半導体デバイスは、半導体基板と、縦導体とを含み、前記縦導体は、前記半導体基板の厚み方向に設けられた微細孔を満たし、成分の異なる少なくとも２種の金属／合金結晶組織からなる溶融凝固体であり、前記金属／合金結晶組織の少なくとも一方は、共晶組織または非共晶組織のナノサイズの結晶組織であって、前記金属／合金結晶組織の他方の共晶組織または非共晶組織と、共晶組織及び非共晶組織によるナノコンポジット結晶構造を構成する。 In order to solve the above-described problem, a semiconductor device according to the present invention includes a semiconductor substrate and a vertical conductor, and the vertical conductor fills a fine hole provided in the thickness direction of the semiconductor substrate and has at least different components. a melt solidified body consisting of two metal / alloy crystal structure, at least one of the metal / alloy crystal structure, a eutectic or non-eutectic structure nano-sized crystal structure of the metal / alloy crystal The other eutectic structure or non- eutectic structure of the structure and a nanocomposite crystal structure composed of the eutectic structure and the non-eutectic structure are formed.
上述したように、本発明では、縦導体が、ナノコンポジット結晶構造を有し、ナノコンポジット結晶構造を構成する結晶組織の少なくとも一方は、ナノサイズであるから、大きさが、ナノレベルに制限された組織（結晶）を含むことの効果として、縦導体に発生する応力が小さくなる。しかも、ナノコンポジット結晶構造には、縦導体の等軸晶化を促進する働きある。
As described above, in the present invention, the vertical conductor has a nanocomposite crystal structure, at least one of the crystal structure constituting the nanocomposite crystal structure, because it is nano-sized, the size is limited to the nano level As an effect of including a texture (crystal), the stress generated in the vertical conductor is reduced. Moreover, the nanocomposite crystal structure has a function of promoting equiaxed crystallization of the vertical conductor.
Claims (12)
前記縦導体は、前記半導体基板の厚み方向に設けられた微細孔を満たし、複数種の金属／合金結晶組織からなり、前記金属／合金結晶組織の少なくとも一種は、ナノサイズの第1結晶組織であり、前記金属／合金結晶組織の少なくとも他の一種である第２結晶組織と、ナノコンポジット結晶構造を構成する、
半導体デバイス。 A semiconductor device including a semiconductor substrate and a vertical conductor,
The vertical conductor fills the fine holes provided in the thickness direction of the semiconductor substrate and is composed of a plurality of types of metal / alloy crystal structures, and at least one of the metal / alloy crystal structures is a nano-sized first crystal structure. A second crystal structure which is at least another kind of the metal / alloy crystal structure, and a nanocomposite crystal structure;
Semiconductor device.
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