JP2012043514A - Semiconductor circuit device and error detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit device, which is suitable to perform an error detection of read out data row, in the semiconductor circuit device capable of reading out sequentially, per data row, data row stored in a series of memory cells arranged in a direction which is orthogonal to a direction when writing data.SOLUTION: An error detection circuit 43 of a semiconductor circuit device 1 includes line error detection circuits 50_0 to 50_n, and an error detection OR circuit 51. Each line error detection circuit reads out parity data PTD in a same cycle when reading out a first line of display data LCD_RD which synchronizes with a clock signal LCD_CK from an LCD and is sequentially read out from a memory cell array 21 per line, and sequentially performs exclusive OR operation between each bit data which is written in a row direction of each line sequentially read out per line and a last operation result, and outputs a final operation result for display data CPU_WD to the error detection OR circuit 51.

Description

  The present invention provides a memory having an access port for writing a bit data string including parity bits and an access port for sequentially reading bit data strings written in a direction orthogonal to the plurality of written bit data strings in units of columns. The present invention relates to a technique for detecting an error in data read from a cell array.

Conventionally, a dual port RAM is known as a RAM (Random Access Memory) for image processing.
Such a RAM has a memory cell array having a plurality of memory cells arranged in a matrix, at least a first access port for writing data, and a second access port for reading data at least. Thus, data can be written and read simultaneously.

Further, a technique for adding a parity bit to data read via a second access port inside the RAM when reading data from the dual port RAM is disclosed (Patent Document 1).
In addition, when writing information data to the dual port RAM, a parity bit is added to the information data, and when reading the information data, the parity data corresponding to the information data is also read and a parity check is performed. A technique for performing error detection is disclosed (Patent Document 2).

JP 63-239684 A JP-A-8-305636

  However, the technique disclosed in Patent Document 1 adds a parity bit to a bit data string output from a memory cell array. For this reason, when an error occurs due to a change in data when data is written to the memory cell array or a change in data written to the memory cell, a parity bit is added to the bit data string having an error. It will be. Therefore, in the subsequent system, even if a parity check is performed, a data error cannot be detected and the system may malfunction.

As a dual port RAM, as shown in FIG. 11, a bit data string composed of a plurality of bit data is provided via a first port composed of a bit line 1BL and a word line 1WL of each memory cell. Data is written in memory cells continuous in the column direction of the memory cell array. Then, there is a configuration in which the written bit data string is read as it is through the second port constituted by the bit line 2BL and the word line 2WL of each memory cell.
Also, as a dual port RAM, as shown in FIG. 12, a bit data string composed of a plurality of bit data is written to memory cells continuous in the row direction of the memory cell array via the first port. There is a configuration in which the written bit data string is read as it is through the second port.

  On the other hand, as disclosed in Patent Document 1, the dual port SRAM used for image display stores a bit data string in the column direction of image data via the first port as shown in FIG. It is configured to write to memory cells that are continuous in the column direction of the cell array. Further, a plurality of bit data columns written in the column direction from the memory cell array via the second port in accordance with the operation of the output destination of the image data such as a CRT display (raster scan operation, etc.) It is the structure which reads sequentially.

When applying the technique of Patent Document 2 to the SRAM having the configuration shown in FIGS. 11 to 13, first, a parity bit is added to a bit data string to be written in the column direction or row direction of the memory cell array. It will be.
In the case of the SRAM having the configuration shown in FIGS. 11 and 12, the data written in the column direction or the row direction can be read as it is. Therefore, the parity check can be immediately performed by reading the bit data string and the parity bit data corresponding to the bit data string.

  On the other hand, in the case of the SRAM having the configuration shown in FIG. 13, a plurality of bit data columns written in memory cells continuous in the column direction and continuous in the row direction are composed of bit data corresponding to the number of columns continuous in the row direction. The data string to be read is one row, and the data is sequentially read out one row at a time via the second port. Therefore, in order to perform a parity check, it is necessary to read all data corresponding to “the number of bits for one row (number of columns) × the number of bits in a bit data string at the time of writing (including parity bits)”. That is, since the parity check cannot be performed until all the row data for the data string to which the parity bit is added is read, it is necessary to temporarily hold the read data in a buffer register, for example.

  Further, as disclosed in Patent Document 2, when the parity data area is provided in the SRAM and the parity data is stored separately from the information data, the CPU is used for reading the information data. In addition, it is necessary to have a dedicated address for reading the parity data. Providing the CPU with this dedicated address complicates the system specifications of the CPU and increases the area of the CPU.

Therefore, one of the objects of the present invention is to perform error detection of data to which an error detection code read from the memory cell array is added in the SRAM configuration for writing and reading data disclosed in Patent Document 1. An object of the present invention is to provide a semiconductor circuit device having an error detection circuit suitable for the above and an error detection circuit.
In addition, the present invention is not limited to the above-described object, and other effects of the present invention can be achieved by the functions and effects derived from the respective configurations shown in the embodiments for carrying out the invention which will be described later. It can be positioned as one of

[Mode 1] In order to achieve the above object, a semiconductor circuit device of mode 1 includes a memory cell array having a configuration in which a plurality of memory cells are arranged in a matrix,
A first access port for accessing data to the memory cell array;
A second access port for accessing data to the memory cell array;
A data writing circuit for writing a first data string including a plurality of bit data and parity bit data corresponding to the plurality of bit data to the memory cell array via the first access port;
A data read circuit for reading a second data string, which is a data string orthogonal to the first data string, from the memory cell array via the second access port;
An error detection circuit for detecting an error in data read from the memory cell array by the data read circuit,
The error detection circuit includes:
With column error detection circuit,
The error detection circuit acquires a plurality of the second data strings read by the data reading unit,
The column error detection circuit performs a parity check based on the first data string included in the plurality of second data strings.

With such a configuration, the error detection circuit can acquire a plurality of second data strings including a plurality of first data strings read by the data reading circuit. In the column error detection circuit, the parity check of each first data string read from the memory cell array is performed based on each first data string included in the plurality of acquired second data strings. it can.
Therefore, for example, in the dual port memory disclosed in the above-mentioned Patent Document 1 in which data is written in the column direction and data is read out in units of rows, error detection of the read data can be performed.

  Here, the parity check is one type of error detection method that can be performed by adding parity bit data (parity code) to an information bit data string, such as a vertical parity method and a horizontal parity method. In the case of the vertical parity method, parity bit data is added so that the total number of “1” s in the information bits is odd or even, and the total number of “1” s in the information bits is calculated when an error is detected. Error detection can be performed by checking whether the total number is odd or even.

[Mode 2] Furthermore, the semiconductor circuit device according to mode 2 is the semiconductor circuit device according to mode 1, wherein the column error detection circuit performs a parity check on the plurality of second data columns acquired in time series. .
With such a configuration, in the column error detection circuit, parity check can be sequentially performed on a plurality of second data columns acquired in time series in units of columns.

  [Mode 3] Furthermore, the semiconductor circuit device according to mode 3 is the semiconductor circuit device according to mode 2, wherein the column error detection circuit has the parity of the first data sequence corresponding to the plurality of acquired second data sequences. For each bit data including bit data, an operation related to a parity check using the acquired bit data and the previous operation result is sequentially performed in the order of acquisition of each bit data, and the read second plurality of second data An operation result for each first data string corresponding to the data string is output as a parity check result.

With such a configuration, the first data string to which the parity bit data is added is parity-checked using the bit data sequentially read out and the previous calculation result in the order of acquisition of the second data string. Operations related to checking can be executed sequentially. Therefore, a register that holds at least the previous calculation result is necessary, but registers corresponding to “the number of bits of the first data column × the number of columns” can be omitted.
Here, the calculation related to the parity check is a calculation process for calculating the sum of “1” in the first data string in the case of the odd parity method and the even parity method. In the case of the even parity method, a parity check can be easily performed by exclusive OR operation.

[Mode 4] Further, in the semiconductor circuit device of mode 4, the semiconductor circuit device of mode 4 is characterized in that the parity bit data is data corresponding to a parity code,
The column error detection circuit performs an exclusive OR operation as the operation related to the parity check.
With such a configuration, the first bit data sequence to which the parity bit data is added is sequentially used in the acquisition order of the second data sequence, using the bit data that is sequentially read and the previous calculation result. Exclusive OR operations can be performed sequentially.
Therefore, error detection can be performed with a simpler configuration.

  Here, in error detection using parity bit data (parity code), the parity code is generated by performing an exclusive OR operation on information data composed of a plurality of bit data. At the time of error detection, an error can be detected from the calculation result by performing an exclusive OR operation on the bit data string in which the parity bit data and the information data are combined. Specifically, in the case of even parity, the result of the exclusive OR operation is “0” when there is no error or the number of errors is an even number, and when the number of errors is an odd number, 1 ". In the case of odd parity, the result of the exclusive OR operation is “1” when the number of errors is an even number, and “0” when there are an odd number of errors. Therefore, both even parity and odd parity can be supported.

[Mode 5] Furthermore, the semiconductor circuit device according to mode 5 is the semiconductor circuit device according to any one of modes 3 or 4, wherein the data read circuit is a reference clock signal supplied from a read destination of the second data string. The second data string is read out in time series in units of columns in synchronization with
The column error detection circuit is configured to acquire the second data string in time series in units of columns in synchronization with the reference clock signal, and the reference clock when acquiring the second data string The parity bit data is obtained within the same period as one period of the signal.
With such a configuration, when reading the second data string (parity line) composed only of parity bit data, one period (cycle) for reading the parity line is added to the reference clock. The parity line can also be read out with the normal number of cycles.

[Mode 6] On the other hand, in order to achieve the above object, the error detection circuit according to mode 6 accesses a memory cell array having a configuration in which a plurality of memory cells are arranged in a matrix and data access to the memory cell array. A first access port, a second access port for accessing data to the memory cell array, and a plurality of bit data and a parity bit corresponding to the plurality of bit data via the first access port A second data string which is a data string orthogonal to the first data string via a data write circuit for writing the first data string including data to the memory cell array and the second access port Read out from the memory cell array by a data read circuit. An error detection circuit for detecting an error in data,
Obtaining a plurality of the second data strings read by the data reading means;
A column error detection circuit is provided that performs a parity check based on each of the first data sequences included in the acquired second data sequences.
With such a configuration, it is possible to obtain the same operations and effects as those of the semiconductor circuit device according to the first aspect.

1 is a block diagram showing a configuration example of a semiconductor circuit device 1 according to the present invention. 3 is a diagram illustrating a circuit configuration example of a memory cell 20. FIG. FIG. 4 is a diagram schematically illustrating a CPU side data reading and writing method and a LCD side data reading method for the memory unit 2. 3 is a block diagram illustrating a configuration example of an error detection circuit 43. FIG. 3 is a block diagram illustrating a configuration example of a column error detection circuit 50_0 in the error detection circuit 43. FIG. It is a figure which shows the specific circuit structural example of the column error detection circuit 50_0. 3 is a diagram illustrating a circuit configuration example of an error detection OR circuit 51. FIG. 3 is a diagram showing an example of the internal configuration of an LCD side control circuit 40. FIG. 6 is a diagram illustrating an example of a timing chart of various signals generated in an LCD-side control circuit 40. FIG. It is a figure which shows the timing chart of the various signals in the column error detection operation | movement of the column error detection circuit 50_0 when display data CPU_WD is a 9-bit data string. It is a figure which shows the 1st prior art example of dual port SRAM. It is a figure which shows the 2nd prior art example of dual port SRAM. It is a figure which shows the 3rd prior art example of dual port SRAM.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 10 are diagrams showing an embodiment of a semiconductor circuit device and an error detection circuit according to the present invention.
(Configuration example of semiconductor circuit device)
First, the configuration of a semiconductor circuit device according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration example of a semiconductor circuit device 1 according to the present invention.
As shown in FIG. 1, the semiconductor circuit device 1 includes a memory unit 2, a CPU side data read / write (R / W) unit 3, and an LCD side data read unit 4.
The memory unit 2 includes a memory cell array 21 having a configuration in which a plurality of memory cells 20 (details will be described later) having a dual-port SRAM configuration are arranged in a matrix, a first access port 22, and a second access port 23. It is configured to include.

The first access port 22 is used to write display data requested to be written from a CPU (not shown) to the memory cell 20 and to read display data requested to be read from the CPU from the memory cell 20. It is an access port used for.
The second access port 23 is an access port used when reading display data to be output to an LCD (Liquid Crystal Display) (not shown) from the memory cell 20.

The CPU side data R / W unit 3 includes a CPU side control circuit 30, a CPU side row address decoder (ADC) circuit 31, a CPU side column address decoder (ADC) circuit 32, and a CPU side data read / write (R / W). W) and a circuit 33.
The CPU side control circuit 30 receives the CPU_CK which is a clock signal from the CPU, and operates the CPU side row ADC circuit 31, the CPU side column ADC circuit 32, and the CPU side data R / W circuit 33 in synchronization with the received CPU_CK. Control timing.

The CPU side row ADC circuit 31 receives the row address signal CPU_RAD from the CPU in synchronization with the control signal from the CPU side control circuit 30, and the bit line of the memory cell 20 corresponding to the row address indicated by the received CPU_RAD. Perform the selection operation.
The CPU side column ADC circuit 32 receives the column address signal CPU_CAD from the CPU in synchronization with the control signal from the CPU side control circuit 30, and the word line of the memory cell 20 corresponding to the column address indicated by the received CPU_CAD. Perform the selection operation.

  The CPU side data R / W circuit 33 receives a display data signal CPU_WD which is a display data signal requested to be written from the CPU in synchronization with the control signal from the CPU side control circuit 30. Further, the display data indicated by the display data signal CPU_WD received via the first access port 22 is sent to the memory cell in which the bit line and the word line are selected by the CPU side row ADC circuit 31 and the CPU side column ADC circuit 32. Write to 20. Further, in response to a display data read request from the CPU, the CPU side row ADC circuit 31 and the CPU side column ADC circuit 32 set the first access port 22 from the memory cell 20 whose bit line and word line are selected. The display data is read out and a display data signal CPU_RD indicating the read display data is output.

The display data written to and read from the CPU is m bit data (m is a natural number of 2 or more) in the column direction of image data displayed on the LCD, and error detection of the bit data. 1-bit parity data. That is, the display data is composed of a bit data string (first data string) of (m + 1) bits.
The LCD data read unit 4 includes an LCD control circuit 40, an LCD address decoder (ADC) circuit 41, an LCD read circuit 42, and an error detection circuit 43.

The LCD control circuit 40 receives LCD_CK, which is a reference clock signal for reading data from the LCD, and controls the operation timing of the LCD ADC circuit 41 and the error detection circuit 43 in synchronization with the received LCD_CK.
The LCD side ADC circuit 41 receives the address signal LCD_ADD from the LCD in synchronization with the control signal from the LCD side control circuit 40. Further, the selection operation of the word line and bit line of the memory cell 20 corresponding to the row address and column address indicated by the received LCD_ADD is performed. That is, the memory cell 20 corresponding to the designated row (for one row) is selected in synchronization with the control signal from the LCD side control circuit 40.

The LCD side readout circuit 42 reads out display data for one row from the memory cells 20 in the row selected by the LCD side ADC circuit 41 in synchronization with the control signal from the LCD side control circuit 40, and displays the readout display. The data LCD_RAD is output to the error detection circuit 43. Further, in synchronization with the control signal from the LCD side control circuit 40, the parity data PTD for one row is read from the memory cell 20 of the row selected by the LCD side ADC circuit 41, and error detection is performed on the read parity data PTD. Output to the circuit 43.
Note that the number of memory cells in the row direction (number of columns) of the memory cell array 21 is (n + 1) (n is a natural number of 1 or more), and the display data LCD_RD to be read is a bit data string of (n + 1) bits. (Second data string). Similarly, parity data PTD for one row is also a bit data string of (n + 1) bits.

  The error detection circuit 43 synchronizes with the control signal from the LCD side control circuit 40 based on the display data signal LCD_RD received from the LCD side read circuit 42 and the parity data signal PTD, and displays each bit of the display data LCD_RD. Parity check is performed for each data. Then, based on the result of the parity check, it is determined whether or not there is an error in each first data string corresponding to the read parity data PTD. Further, based on the determination result, an error detection signal EDC indicating whether or not there is an error in the read display data LCD_RD for m rows is output.

(Configuration example of memory cell)
Next, the circuit configuration of the memory cell 20 of the present embodiment will be described with reference to FIG.
Here, FIG. 2 is a diagram illustrating a circuit configuration example of the memory cell 20.
As shown in FIG. 2, the memory cell 20 includes a first inverter circuit INV1 and a second inverter circuit INV2. The first inverter circuit INV1 includes a load P-channel MOS transistor (PMOS transistor) PTr1 and a driving N-channel MOS transistor (NMOS transistor) NTr1. The PMOS transistor PTr1 and the NMOS transistor NTr1 are connected in series between a power supply terminal to which the power supply voltage VDD is supplied and a ground terminal to which the ground voltage VSS is supplied.

The second inverter circuit INV2 includes a load PMOS transistor PTr2 and a drive NMOS transistor NTr2. The PMOS transistor PTr2 and the NMOS transistor NTr2 are connected in series between the power supply terminal and the ground terminal.
Specifically, the source terminal of the PMOS transistor PTr1 is connected to the power supply terminal. The drain terminal of the PMOS transistor PTr1 is connected to the drain terminal of the NMOS transistor NTr1 via the storage node N1. The gate terminal of the PMOS transistor PTr1 is connected to the gate terminal of the NMOS transistor NTr1. The source terminal of the NMOS transistor NTr1 is connected to the ground terminal.

  The source terminal of the PMOS transistor PTr2 is connected to the power supply terminal. The drain terminal of the PMOS transistor PTr2 is connected to the drain terminal of the NMOS transistor NTr2 via the storage node N2. The gate terminal of the PMOS transistor PTr2 is connected to the gate terminal of the NMOS transistor NTr2. The source terminal of the NMOS transistor NTr2 is connected to the ground terminal.

  The gate terminal of the PMOS transistor PTr1 is connected to the storage node N2. The gate terminal of the PMOS transistor PTr2 is connected to the storage node N1. In other words, the first inverter circuit INV1 and the second inverter circuit INV2 are cross-coupled. That is, the output terminal of the first inverter circuit INV1 is connected to the input terminal of the second inverter circuit INV2, and the output terminal of the second inverter circuit INV2 is connected to the input terminal of the first inverter circuit INV1.

The storage node N1 is connected to the bit line 1BL via the NMOS transistor NTr3. The gate terminal of the NMOS transistor NTr3 is connected to the word line 1WL.
The storage node N2 is connected to the bit line 1XBL via the NMOS transistor NTr4. The gate terminal of the NMOS transistor NTr4 is connected to the word line 1WL.

The gate terminal of the PMOS transistor PTr2 is connected to the gate terminal of the PMOS transistor PTr3. The source terminal of the PMOS transistor PTr3 is connected to the power supply terminal. The drain terminal of the PMOS transistor PTr3 is connected to the source terminal of the PMOS transistor PTr4. The drain terminal of the PMOS transistor PTr4 is connected to the bit line 2BL. The gate terminal of the PMOS transistor PTr4 is connected to the word line 2WL.
The bit lines 1BL of the memory cells 20 arranged in the column direction of the memory cell array 21 are commonly connected for each column, and the bit lines 1XBL of the memory cells 20 arranged in the column direction of the memory cell array 21 are commonly connected for each column. Has been. Further, the word lines 1WL of the memory cells 20 arranged in the row direction of the memory cell array 21 are commonly connected for each row.

The plurality of bit lines 1BL, 1XBL and the plurality of word lines 1WL connected in common constitute a first access port 22.
Further, the bit lines 2BL of the memory cells 20 arranged in the column direction of the memory cell array 21 are commonly connected to each column. Further, the word lines 2WL of the memory cells 20 arranged in the row direction of the memory cell array 21 are commonly connected for each row.

The plurality of bit lines 2BL and the plurality of word lines 2WL connected in common constitute a second access port 23.
In the present embodiment, since only reading of data is performed from the second access port 23, as shown in the above configuration, the reading of data from each memory cell 20 is performed for the second access port 23. Is performed using a PMOS transistor.
With such a configuration, the area of the memory cell can be reduced as compared with the configuration using the NMOS transistor.

(Data writing / reading method to / from memory unit 2)
Next, a method for writing and reading data from the CPU side and a method for reading data from the LCD side with respect to the memory cell array 21 having the memory cell 20 having the configuration shown in FIG.
Here, FIG. 3 is a diagram schematically illustrating the CPU-side data reading and writing method and the LCD-side data reading method for the memory cell array 21.

In FIG. 3, a line in which the bit lines 1BL and 1XBL of the memory cells 20 arranged in the row direction are commonly connected to each row is referred to as a bit line CPU_BL. A line in which the word lines 1WL of the memory cells 20 arranged in the column direction are commonly connected to each column is referred to as a word line CPU_WL. A line in which the bit lines 2BL of the memory cells 20 arranged in the column direction are commonly connected in the column direction is referred to as a bit line LCD_BL. A line in which the word lines 2WL of the memory cells 20 arranged in the row direction are commonly connected to each row is referred to as a word line LCD_WL.
As shown in FIG. 3, the display data CPU_R / WD for reading or writing is a 9-bit bit composed of 1-bit parity bit data PTBD and 8-bit bit data (information data) PID. It becomes a data string.

  Then, from the CPU side, as shown in FIG. 3, the display data CPU_WD is written into the memory cells 20 that are selected by the word line CPU_WL and selected by the bit line CPU_BL and that are continuous in the column direction of the memory cell array 21. . Further, when a plurality of display data CPU_WD are written, each display data CPU_WD is written sequentially in the row direction. On the CPU side, the display data CPU_RD selected by the word line CPU_WL and selected by the bit line CPU_BL and written in the memory cells 20 continuous in the column direction are read as they are, including the parity bit data PTBD. That is, the CPU side has only an address for the display data CPU_WD to which the parity bit data PTBD is added, and does not have a dedicated address for the parity bit data PTBD.

On the other hand, on the LCD side, as shown in FIG. 3, display data written in the memory cells 20 selected in the row direction of the memory cell array 21 selected by the word line LCD_WL and selected by the bit line LCD_BL is displayed. The data is read sequentially for each line (line) as the data LCD_RD. The display data LCD_RD thus read out is the data written in the memory cell 20 at a position orthogonal to the display data CPU_WD written in the memory cell 20 that is continuous in the column direction on the CPU side in the memory cell array 21. It becomes.
Accordingly, a plurality of display data CPU_RD is composed of a plurality of display data LCD_RD read out sequentially line by line.

(Configuration example of error detection circuit)
Next, a detailed configuration of the error detection circuit 43 will be described with reference to FIG.
Here, FIG. 4 is a block diagram showing a configuration example of the error detection circuit 43.
As shown in FIG. 4, the error detection circuit 43 includes the same number of column error detection circuits 50_0 to 50_n as the number of columns (n + 1) of the memory cell array 21, and an error detection OR circuit 51.
The column error detection circuits 50_0 to 50_n are circuits that operate based on various error detection control signals and reset signals supplied from the LCD side control circuit 40.

The column error detection circuit 50_0 sequentially acquires the bit data LRD0 and the parity bit data PTBD0 that are sequentially read from the memory cell 20 corresponding to the column number 0 (for example, the leftmost column) in the memory cell array 21 in the LCD side read circuit 42. To do. Then, using the acquired bit data LRD0 and parity bit data PTBD0, parity check of the even parity method is sequentially performed on the read data of the display data CPU_WD0 written in the memory cell 20 corresponding to the column number 0 from the CPU side. Further, the column error detection signal EDC0 indicating the result of the parity check for the read data is output to the error detection OR circuit 51.
Each of the column error detection circuits 50_1 to 50_n is similar to the column error detection circuit 50_0 in that bit data LRD1 to LRDn and parity bit data PTBD1 to PTBDn are sequentially read from the memory cells 20 corresponding to the column numbers 1 to n, respectively. The data with the same number at the end is acquired sequentially.

Then, each of the display data written to the memory cells 20 corresponding to the column numbers 1 to n from the CPU side using the data having the same end number among the bit data LRD1 to LRDn and the parity data PTBD1 to PTBDn. Parity check is performed on data having the same end number among the read data LRD1 to LRDn of the CPU_WD1 to WDn.
Further, each of the column error detection circuits 50_1 to 50_n uses the column error detection signals EDC1 to EDCn having the same end number among the column error detection signals EDC1 to EDCn indicating the result of the parity check for the read data LRD1 to LRDn having the same end number. Output to the error detection OR circuit 51.

In this embodiment, column error detection signals EDC0 to EDCn indicate that an error has been detected when there is a high level signal (there is an error), and no error has been detected when the signal is a low level signal. (No error).
The error detection OR circuit 51 outputs a signal indicating the logical sum of the input column error detection signals EDC0 to EDCn. Accordingly, if any of the display data CPU_WD0 to WDn read as the LCD read data has an error detected, a high level signal is output, and no error has been detected. A low level signal is output.

(Configuration example of column error detection circuit)
Next, a detailed configuration of the column error detection circuit 50_0 will be described with reference to FIG.
Here, FIG. 5 is a block diagram illustrating a configuration example of the column error detection circuit 50_0 in the error detection circuit 43. Note that the column error detection circuits 50_1 to 50_n have the same configuration as the column error detection circuit 50_0 only in the data handled.
As shown in FIG. 5, the column error detection circuit 50_0 includes a latch circuit 50a, an exclusive OR circuit 50b, a latch circuit with reset 50c, a latch circuit 50d, an error detection output latch circuit 50e, and read data. And a latch circuit 50f.

Further, the column error detection circuit 50_0 is configured to include a data reading unit corresponding to the column number 0 in the LCD reading circuit 42 and a switch SW0 for switching between electrical connection and disconnection with the latch circuit 50a.
Further, the column error detection circuit 50_0 includes an electrical switch composed of a switch SW1 for switching electrical connection and disconnection between the exclusive OR circuit 50b and the latch circuit 50c with reset, and an electrical circuit between the latch circuit 50c with reset and the latch circuit 50d. A switch SW2 for switching between connection and disconnection is included.

Further, the column error detection circuit 50_0 includes a switch SW3 that switches between electrical connection and disconnection between the exclusive OR circuit 50b and the error detection output latch circuit 50e, an exclusive OR circuit 50b, and a read data latch circuit. The switch SW4 is configured to switch between electrical connection and disconnection with the 50f.
The latch circuit 50a holds the state of the read data signal input from the LCD read circuit 42 via the switch SW0 in response to the rising edge of the error detection control signal S0 supplied from the LCD control circuit 40. Then, the latch signal L0 indicating the held state is output to the exclusive OR circuit 50b and also output to the read data latch circuit 50f via the switch SW4. That is, the latch circuit 50a latches the data signal output from the LCD side read circuit 42 in response to the rising edge of the error detection control signal S0.

  The latch circuit with reset 50c receives the exclusive OR signal XOR input from the exclusive OR circuit 50b via the switch SW1 in response to the rising edge of the error detection control signal S1 supplied from the LCD side control circuit 40. Keep state. Then, the latch signal L1 indicating the held state is output to the latch circuit 50d via the switch SW2. That is, the latch circuit with reset 50c latches the exclusive OR signal XOR output from the exclusive OR circuit 50b in response to the rising edge of the error detection control signal S1.

Further, the latch circuit with reset 50c forcibly changes the currently held state to the reset state in response to the rising edge of the reset signal RST supplied from the LCD side control circuit 40. Specifically, when the state of the latch signal L2 that is currently output is at a high level, the holding state is forcibly changed so as to become a low level state.
The latch circuit 50d holds the state of the latch signal L1 input from the latch circuit with reset 50c via the switch SW2 in response to the rising edge of the error detection control signal S2 supplied from the LCD side control circuit 40. Then, the latch signal L2 indicating the held state is output to the exclusive OR circuit 50b. That is, the latch circuit 50d latches the latch signal L1 output from the latch circuit with reset 50c in response to the rising edge of the error detection control signal S2.

  The exclusive OR circuit 50b is reset with an exclusive OR signal XOR which is a signal indicating an exclusive OR of the latch signal L0 input from the latch circuit 50a and the latch signal L2 input from the latch circuit 50d. The data is output to the latch circuit 50c via the switch SW1. Further, the exclusive OR signal XOR is output to the error detection output latch circuit 50e via the switch SW3.

  The error detection output latch circuit 50e receives an exclusive OR signal input from the exclusive OR circuit 50b via the switch SW3 in response to the rising edge of the error detection control signal S3 supplied from the LCD side control circuit 40. Holds the state of XOR. Then, a signal indicating the held state is output to the error detection OR circuit 51 as a column error detection signal EDC0. That is, the error detection output latch circuit 50e latches the exclusive OR signal XOR output from the exclusive OR circuit 50b in response to the rising edge of the error detection control signal S3.

  The read data latch circuit 50f holds the state of the latch signal L0 input from the latch circuit 50a via the switch SW4 in response to the rising edge of the error detection control signal S4 supplied from the LCD side control circuit 40. Then, a signal indicating the held state is output to the LCD as a display data signal LRD0. That is, the read data latch circuit 50f latches the latch signal L0 output from the latch circuit 50a in response to the rising edge of the error detection control signal S4.

The switch SW0 is composed of a MOS transistor, and is turned on when the error detection control signal S0 supplied from the LCD side control circuit 40 is at a high level, and energizes the latch circuit 50a and the LCD side readout circuit 42. Let me. When the error detection control signal S0 is at a low level, the latch circuit 50a and the LCD side readout circuit 42 are electrically disconnected from each other.
The switch SW1 is composed of a MOS transistor, and is turned on when the error detection control signal S1 supplied from the LCD-side control circuit 40 is at a high level, and the exclusive OR circuit 50b and the latch circuit 50c with reset are provided. And energize. Further, when the error detection control signal S1 is at the low level, it is turned off, and the exclusive OR circuit 50b and the latch circuit 50c with reset are electrically disconnected.

The switch SW2 is composed of a MOS transistor, and is turned on when the error detection control signal S2 supplied from the LCD side control circuit 40 is at a high level, and energizes the latch circuit with reset 50c and the latch circuit 50d. Let Further, when the error detection control signal S2 is at a low level, it is turned off, and the latch circuit with reset 50c and the latch circuit 50d are electrically disconnected.
The switch SW3 is composed of a MOS transistor, and is turned on when the error detection control signal S3 supplied from the LCD-side control circuit 40 is at a high level, so that the exclusive OR circuit 50b and the error detection output latch The circuit 50e is energized. When the error detection control signal S3 is at a low level, the signal is turned off, and the exclusive OR circuit 50b and the error detection output latch circuit 50e are electrically disconnected.

  The switch SW4 is composed of a MOS transistor, and is turned on when the error detection control signal S4 supplied from the LCD side control circuit 40 is at a high level, and the latch circuit 50a and the read data latch circuit 50f are switched on. Energize. When the error detection control signal S4 is at a low level, the latch circuit 50a is electrically disconnected from the read data latch circuit 50f.

(Specific circuit configuration example of column error detection circuit)
Next, a specific circuit configuration of each circuit of the column error detection circuit 50_0 will be described with reference to FIG.
FIG. 6 is a diagram illustrating a specific circuit configuration example of the column error detection circuit 50_0.
As illustrated in FIG. 6, in the present embodiment, the latch circuit 50a includes a clocked inverter TN0 having both functions of a transmission gate and a NOT gate, and a NOT that receives a signal with negative logic and outputs a signal with positive logic. It consists of a gate N0.
The clocked inverter TN0 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NOT gate N0 and outputs. The terminal is electrically connected to the input terminal of the NOT gate N0. That is, the clocked inverter TN0 and the NOT gate N0 have a loop configuration.

The output terminal of the NOT gate N0 is electrically connected to the input terminal of the NOT gate N1, which receives a signal with negative logic and outputs a signal with positive logic.
Further, the clocked inverter TN0 receives an error detection control signal S0 from the LCD control circuit 40 at the second input terminal and has an error detection control complementary to the error detection control signal S0 at the third input terminal. The signal xS0 is input. When the detection control signal S0 is at the high level and xS0 is at the low level, the signal input to the first input terminal is inverted and output from the output terminal. Further, when the detection control signal S0 is at the low level and xS0 is at the high level, the signal input to the first input terminal is not output from the output terminal. Therefore, the clocked inverter TN0 also has the function of the switch SW0.

The latch circuit with reset 50c includes clocked inverters TN1 and TN2 having both functions of a transmission gate and a NOT gate, and a NAND gate NA0.
The clocked inverter TN1 has first to third three input terminals and one output terminal, and the first input terminal is the first input of the XOR gate of the exclusive OR circuit 50b. The output terminal is electrically connected to the first input terminal of the NAND gate NA0.

The error detection control signal S1 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN1, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN1. An error detection control signal xS1 having a complementary relationship with the signal S1 is input.
The clocked inverter TN2 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NAND gate NA0 and outputs The terminal is electrically connected to the first input terminal of the NAND gate NA0.

The error detection control signal S1 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN2, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN2. A signal xS1 is input.
Further, the second input terminal of the clocked inverter TN1 is electrically connected to the second input terminal of the clocked inverter TN2, and the third input terminal of the clocked inverter TN1 is the third input terminal of the clocked inverter TN2. Is electrically connected to the input terminal.

The reset signal RST is input from the LCD side control circuit 40 to the second input terminal of the NAND gate NA0.
The clocked inverter TN2 and the NAND gate NA0 are in a loop configuration. When a high level signal is input to the NAND gate NA0 as the reset signal RST, the NAND gate NA0 has the output signal of the clocked inverter TN2 at the high level. At this time, a low level signal is output. That is, a reset is applied and the output signal is forced to be a low level signal.

Further, the clocked inverters TN1 and TN2 have the error detection control signal S1 input to the second input terminal at a high level and the error detection control signal xS1 input to the third input terminal at a low level. The signal input to the first input terminal is inverted and output from the output terminal.
Further, when the error detection control signal S1 input to the second input terminal is at a low level and the error detection control signal xS1 input to the third input terminal is at a high level, the error detection control signal S1 is input to the first input terminal. Signal is not output from the output terminal. Therefore, the clocked inverters TN1 and TN2 also have the function of the switch SW1.

The latch circuit 50d includes clocked inverters TN3 and TN4 having both functions of a transmission gate and a NOT gate, and a NOT gate N2 that receives a signal with negative logic and outputs a signal with positive logic.
The clocked inverter TN3 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NAND gate NA0 and outputs The terminal is electrically connected to the input terminal of the NOT gate N2.

The error detection control signal S2 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN3, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN3. An error detection control signal xS2 having a complementary relationship with the signal S2 is input.
The clocked inverter TN4 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NOT gate N2 for output. The terminal is electrically connected to the input terminal of the NOT gate N2.

The error detection control signal S2 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN4, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN4. Signal xS2 is input.
Further, the second input terminal of the clocked inverter TN3 is electrically connected to the second input terminal of the clocked inverter TN4, and the third input terminal of the clocked inverter TN3 is the third input terminal of the clocked inverter TN4. Is electrically connected to the input terminal.

Further, the clocked inverters TN3 and TN4 have the error detection control signal S2 input to the second input terminal at a high level and the error detection control signal xS2 input to the third input terminal at a low level. The signal input to the first input terminal is inverted and output from the output terminal.
Further, when the error detection control signal S2 input to the second input terminal is at a low level and the error detection control signal xS2 input to the third input terminal is at a high level, the error detection control signal S2 is input to the first input terminal. Signal is not output from the output terminal. Therefore, the clocked inverters TN3 and TN4 also have the function of the switch SW2.

The error detection output latch circuit 50e includes clocked inverters TN5 and TN6 having both functions of a transmission gate and a NOT gate, and a NOT gate N3 that receives a signal with a negative logic and outputs a signal with a positive logic. The
The clocked inverter TN5 has first to third three input terminals and one output terminal. The first input terminal is electrically connected to the output terminal of the XOR gate, and the output terminal. Are electrically connected to the input terminal of the NOT gate N3.

The error detection control signal S3 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN5, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN5. An error detection control signal xS3 having a complementary relationship with the signal S3 is input.
The clocked inverter TN6 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NOT gate N3 for output. The terminal is electrically connected to the input terminal of the NOT gate N3.

The error detection control signal S3 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN6, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN6. Signal xS3 is input.
Further, the second input terminal of the clocked inverter TN5 is electrically connected to the second input terminal of the clocked inverter TN6, and the third input terminal of the clocked inverter TN5 is the third input terminal of the clocked inverter TN6. Is electrically connected to the input terminal.

Further, the clocked inverters TN5 and TN6 have the error detection control signal S3 input to the second input terminal at a high level and the error detection control signal xS3 input to the third input terminal at a low level. The signal input to the first input terminal is inverted and output from the output terminal.
Further, when the error detection control signal S3 input to the second input terminal is at a low level and the error detection control signal xS3 input to the third input terminal is at a high level, the error detection control signal S3 is input to the first input terminal. Signal is not output from the output terminal. Therefore, the clocked inverters TN5 and TN6 also have the function of the switch SW3.

The read data latch circuit 50f includes clocked inverters TN7 and TN8 having both functions of a transmission gate and a NOT gate, and a NOT gate N4 that receives a signal with a negative logic and outputs a signal with a positive logic. .
The clocked inverter TN7 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NOT gate N1 for output. The terminal is electrically connected to the input terminal of the NOT gate N4.

The error detection control signal S4 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN7, and error detection control is performed from the LCD side control circuit 40 to the third input terminal of the clocked inverter TN7. An error detection control signal xS4 having a complementary relationship with the signal S4 is input.
The clocked inverter TN8 has first to third three input terminals and one output terminal, and the first input terminal is electrically connected to the output terminal of the NOT gate N4 for output. The terminal is electrically connected to the input terminal of the NOT gate N4.

The error detection control signal S4 is input from the LCD side control circuit 40 to the second input terminal of the clocked inverter TN8, and the error detection control from the LCD side control circuit 40 is input to the third input terminal of the clocked inverter TN8. Signal xS4 is input.
Further, the second input terminal of the clocked inverter TN7 is electrically connected to the second input terminal of the clocked inverter TN8, and the third input terminal of the clocked inverter TN7 is the third input terminal of the clocked inverter TN8. Is electrically connected to the input terminal.

Further, the clocked inverters TN7 and TN8 have the error detection control signal S4 input to the second input terminal at a high level and the error detection control signal xS4 input to the third input terminal at a low level. The signal input to the first input terminal is inverted and output from the output terminal.
When the error detection control signal S4 input to the second input terminal is at a low level and the error detection control signal xS4 input to the third input terminal is at a high level, the error detection control signal S4 is input to the first input terminal. Signal is not output from the output terminal. Therefore, the clocked inverters TN7 and TN8 also have the function of the switch SW4.

(Configuration example of OR circuit for error detection)
Next, a specific circuit configuration of the error detection OR circuit will be described with reference to FIG.
Here, FIG. 7 is a diagram illustrating a circuit configuration example of the error detection OR circuit 51.
As shown in FIG. 7, the error detection OR circuit 51 includes first and second input terminals and an output terminal, and performs a logical sum of signals input to the first and second input terminals. OR gates ORA0 to ORAn that output the logical sum signal shown.
The OR gates ORA0 to ORAn are connected in series, and the output terminals of the OR gates ORA0 to ORA (n-1) correspond to the numbers at the end of the OR gate among the second input terminals of the OR gates ORA1 to ORAn, respectively. And the second input terminal of the OR gate whose last number is “+1”.

  The first input terminal of the OR gate ORA0 is electrically connected to the output terminal of the error detection output latch circuit 50e of the column error detection circuit 50_0. Further, the second input terminal of the OR gate ORA0 is electrically connected to the output terminal of the error detection output latch circuit 50e of the column error detection circuit 50_1. That is, the column error detection signal EDC0 is input to the first input terminal of the OR gate ORA0, and the column error detection signal EDC1 is input to the second input terminal of the OR gate ORA0.

The output terminal of the error detection output latch circuit 50e of the column error detection circuit 50_2 is electrically connected to the first input terminal of the OR gate ORA1. That is, the column error detection signal EDC2 is input to the first input terminal of the OR gate ORA1.
Further, the output terminal of the OR gate ORA0 is electrically connected to the second input terminal of the OR gate ORA1. That is, a signal indicating the logical sum of the column error detection signals EDC0 and EDC1 is input to the second input terminal of the OR gate ORA1.

  Similarly, the first input terminals of the OR gates ORA2 to ORAn are respectively connected to the end numbers of the OR gates of the output terminals of the error detection output latch circuits 50e of the column error detection circuits 50_3 to 50_n. The output terminal of the error detection output latch circuit 50e of the column error detection circuit whose number is “+1” is electrically connected. That is, among the column error detection signals EDC3 to EDCn, column error detection signals whose end number is "+1" with respect to the end number of the OR gate are input to the first input terminals of the OR gates ORA2 to ORAn. Is done.

In addition, the second input terminals of the OR gates ORA2 to ORAn have “−1” as the end number of the output terminals of the OR gates ORA1 to ORA (n−1) with respect to the end number of the OR gate. The output terminal of the OR gate is electrically connected. In other words, the second input terminals of the OR gates ORA2 to ORAn are connected to the OR of the signals indicating the logical sum of the column error detection signal EDCi (i is a natural number of 3 to n) and the OR gate ORA (i-1). A signal indicating the logical sum of the column error detection signal having the end number “+1” and the output signal of the OR gate having the end number “−1” with respect to the end numbers of the gates ORA2 to ORAn is input. Is done.
Therefore, the output signal of the OR gate ORAn becomes a signal indicating the logical sum of the column error detection signals EDC0 to EDC1, and this signal is output as the error detection signal EDC.

(Configuration example of LCD control circuit)
Next, a detailed configuration of the LCD side control circuit 40 will be described with reference to FIG.
Here, FIG. 8 is a diagram illustrating an internal configuration example of the LCD-side control circuit 40.
As shown in FIG. 8, the LCD side control circuit 40 includes a first internal pulse generation circuit 40a, a delay circuit 40b, a second internal pulse generation circuit 40c, and a timing generation circuit 40d. .

The first internal pulse generation circuit 40a generates a pulse signal PL1 having a cycle shorter than one cycle of the clock signal LCD_CK based on the clock signal LCD_CK supplied from the LCD.
Further, the first internal pulse generation circuit 40a is configured to generate error detection control signals S0 to S3 and a reset signal RST based on a clock signal LCD_CK supplied from the LCD, and an error detection control signal. S4 is generated.
The delay circuit 40b delays the pulse signal PL1 output from the first internal pulse generation circuit 40a for a predetermined time, and outputs the delayed pulse signal PL2 to the second internal pulse generation circuit 40c.

Second internal pulse generation circuit 40c has a configuration similar to that of first internal pulse generation circuit 40a, and is based on delay pulse signal PL2 supplied from delay circuit 40b for a predetermined time with respect to pulse signal PL1. A pulse signal PL3 having a cycle that is delayed and shorter than one cycle of the clock signal LCD_CK is generated.
Further, the second internal pulse generation circuit 40c generates pulse signals PLS4 to PLS5 for generating error detection control signals S0 to S2 based on the clock signal LCD_CK supplied from the LCD.

With the above configuration, the first internal pulse generation circuit 40a and the second internal pulse generation circuit 40c cause the two pulse signals PL1 and PL3 to be generated in the order of PL1 and PL3 in one cycle of the clock signal LCD_CK. Can be generated continuously.
In the present embodiment, pulse signals PL1 and PL3 output from the first internal pulse generation circuit 40a and the second internal pulse generation circuit 40c are internal clock signals CK (hereinafter referred to as internal CK), It is supplied to the LCD side readout circuit 42. Then, the LCD side readout circuit 42 reads out the display data LCD_RD in synchronization with the pulse signal PL1, and reads out the parity data PTD in synchronization with the pulse signal PL3.

In this embodiment, the parity bit data PTBD is 1 bit with respect to the display data CPU_WD of (m + 1) bits. Therefore, when reading data on the LCD side, the parity data PTD only needs to be read for one line. . Therefore, the pulse signal PL3 is generated only once every time (m + 1) lines are read.
The timing generation circuit 40d generates an error based on the pulse signals PLS0 to PLS5 output from the first internal pulse generation circuit 40a and the second internal pulse generation circuit 40c, and the 1L signal and the mL signal supplied from the LCD. This is a circuit that generates error detection control signals S0 to S3 and a reset signal RST supplied to the detection circuit 43.

Here, the 1L signal is active when an address corresponding to the 1st line, mth line, 2 × m + 1) line,..., ((K−1) × m + 1) line is selected on the LCD. Is a signal. Here, m is the number of bits of the information data PID corresponding to the parity bit data PTBD, and k is a natural number such that “k × m = total number of lines in the display area of the LCD”.
The mL signal is a signal that becomes active when an address corresponding to the m-th line, 2 × m-th line, 3 × m-th line,..., K × m-th line is selected on the LCD.

Specifically, the timing generation circuit 40d has first to second input terminals and an output terminal, and outputs a logical product signal indicating a logical product of signals input to the first to second input terminals. It is configured including AND gates A0 to A3.
The timing generation circuit 40d further includes first to second input terminals and an output terminal, and outputs an OR gate indicating a logical sum of signals input to the first to second input terminals. It is configured to include ORB0 to ORB1.
The first input terminal of the AND gate A0 is electrically connected to the output terminal of the pulse signal PLS4 of the second internal pulse generation circuit 40c, and the second input terminal is electrically connected to the output terminal of the 1L signal of the LCD. Has been.

The output terminal of the AND gate A0 is electrically connected to the first input terminal of the OR gate ORB0.
The first input terminal of the AND gate A1 is electrically connected to the output terminal of the pulse signal PLS5 of the second internal pulse generation circuit 40c, and the second input terminal is electrically connected to the output terminal of the 1L signal of the LCD. It is connected.

The output terminal of the AND gate A1 is electrically connected to the first input terminal of the OR gate ORB1.
The second input terminals of the OR gates ORB0 and ORB1 are electrically connected to the output terminal of the pulse signal PLS0 of the first internal pulse generation circuit 40a, respectively.
With the above configuration, the error detection control signals S0 and S2 corresponding to the state of the 1L signal and the states of the pulse signals PLS0 and PLS4 are output from the output terminal of the OR gate ORB0. An error detection control signal S1 corresponding to the state of the 1L signal and the states of the pulse signals PLS1 and PLS5 is output from the output terminal of the OR gate ORB1.

The first input terminal of the AND gate A2 is electrically connected to the output terminal of the pulse signal PLS2 of the first internal pulse generation circuit 40a, and the second input terminal is electrically connected to the output terminal of the mL signal of the LCD. It is connected to the.
The first input terminal of the AND gate A3 is electrically connected to the output terminal of the pulse signal PLS3 of the first internal pulse generation circuit 40a, and the second input terminal is electrically connected to the output terminal of the 1L signal of the LCD. It is connected to the.

  With the above configuration, the error detection control signal S1 corresponding to the state of the mL signal and the state of the pulse signal PLS2 is output from the output terminal of the AND gate A2. Further, a reset signal RST corresponding to the state of the 1L signal and the state of the pulse signal PLS3 is output from the output terminal of the AND gate A3. In the present embodiment, every time the bit data corresponding to the first line of the display data CPU_WD0 to WDn (first data string) corresponding to the (n + 1) columns corresponding to the m lines of the LCD is read, a reset is provided. A reset signal RST for resetting the latch signal L1 of the latch circuit 50c is output.

(About various signals and operation of each circuit on the LCD side)
Next, various signals generated in the LCD side control circuit 40 and operations of the respective circuits on the LCD side according to the various signals will be described with reference to FIG.
Here, FIG. 9 is a diagram illustrating an example of a timing chart of various signals generated in the LCD-side control circuit 40. In FIG. 9, the vertical axis represents voltage, the horizontal axis represents time, and time elapses from left to right in the drawing.

As shown in FIG. 9, first, the LCD side control circuit 40 starts the internal CK in the first high level period (the first high level period counted from the left in the figure) of the clock signal LCD_CK supplied from the LCD. As a result, two pulse signals (PL 1 and PL 3) are supplied to the LCD side readout circuit 42.
The LCD-side ADC circuit 41 is based on an address signal LCD_ADD supplied from the LCD in synchronization with the first pulse signal (PL1) of the two pulse signals, in the display area of the LCD in the memory cell array 21. The memory cell 20 in the row in which the display data LCD_RD0 displayed on the first line is stored is selected.

The LCD read circuit 42 reads the display data LCD_1RD displayed on the first line from the memory cell 20 on the line selected by the LCD ADC circuit 41 in synchronization with the first pulse signal. Then, the read display data LCD_1RD for the first line is output to the error detection circuit 43.
Subsequently, the LCD-side ADC circuit 41 synchronizes with the second pulse signal (PL3) in the memory cell array 21 in the memory cell in the row in which the parity data 1PTD corresponding to the display data LCD_1RD for the first line is stored. 20 is selected.

Then, the LCD read circuit 42 reads the parity data 1PTD corresponding to the display data LCD_1RD from the memory cell 20 of the line selected by the LCD ADC circuit 41 in synchronization with the second pulse signal. Then, the read parity data 1PTD is output to the error detection circuit 43.
That is, in this embodiment, both display data LCD_1RD for the first line and parity data 1PTD are read in one cycle of the clock signal LCD_CK.

  On the other hand, the LCD-side control circuit 40 first outputs a low-level error detection control signal S1 to the error detection circuit 43 during the high-level period of the first pulse signal, and subsequently outputs a reset signal RST (high level). Output to the error detection circuit 43. Subsequently, the LCD side control circuit 40 sets the reset signal RST to the low level and outputs the high level error detection control signals S0 and S2 to the error detection circuit 43. Thereafter, the low-level error detection control signals S0 and S2 and the high-level error detection control signal S4 are output to the error detection circuit 43. Subsequently, the low-level error detection control signal S4 and the high-level error detection control signal S1 are output to the error detection circuit 43.

Therefore, in each column error detection circuit 50_0 to 50_n of the error detection circuit 43 during the high level period of the first pulse signal, the switch SW1 is first turned off, and then the latch circuit 50c with reset is latched. The state of the active signal is reset (forced to low level).
Subsequently, the switches SW0 and SW2 are turned on, and in the latch circuit 50a, one bit of a column corresponding to each column error detection circuit 50_0 to 50_n in the display data LCD_1RD for the first line supplied from the LCD side reading circuit 42 is displayed. Data LRD0 to LRDn are latched. In the latch circuit 50d, the output signal L2 of the latch circuit 50c with reset is latched.

The latch signal L0 (read data signal on the first line) and the latch signal L2 (signal after reset) are input to the exclusive OR circuit 50b, and an exclusive OR signal XOR indicating the exclusive OR of both is input. Is output.
Subsequently, the switches SW0 and SW2 are turned off and the switch SW4 is turned on. The read data latch circuit 50f latches the latch signal L0 indicating the state of the read data LRD latched by the latch circuit 50a. Thereafter, the switch SW4 is turned off and the switch SW1 is turned on, and the exclusive OR signal XOR from the exclusive OR circuit 50b is latched in the latch circuit 50c with reset.

Subsequently, the LCD side control circuit 40 outputs a low level error detection control signal S1 to the error detection circuit 43. Next, the LCD side control circuit 40 outputs high-level error detection control signals S0 and S2 to the error detection circuit 43. Thereafter, low level error detection control signals S 0 and S 2 are output to the error detection circuit 43.
Therefore, in the high-level period of the second pulse signal, in each column error detection circuit 50_0 to 50_n of the error detection circuit 43, the switch SW1 is first turned off.

Subsequently, the switches SW0 and SW2 are turned on, and the latch circuit 50a latches the column data corresponding to the column error detection circuits 50_0 to 50_n in the parity bit data PTBD0 to PTBDn supplied from the LCD side read circuit 42. The In the latch circuit 50d, the latch signal L2 from the latch circuit 50c with reset is latched.
The latch signal L0 (parity data signal) and the latch signal L2 (previous exclusive OR signal XOR) are input to the exclusive OR circuit 50b, and an exclusive OR signal XOR indicating the exclusive OR of both is input. Is output.

Subsequently, the switches SW0 and SW2 are turned off, and then the switch SW1 is turned on, and the exclusive OR signal XOR from the exclusive OR circuit 50b is latched by the latch circuit 50c with reset.
The LCD side control circuit 40 continues to supply a pulse signal PL1 serving as a third pulse signal to the LCD side readout circuit 42 as the internal CK in the second high level period of the clock signal LCD_CK.
The LCD side ADC circuit 41 synchronizes with the third pulse signal, and based on the address signal LCD_ADD supplied from the LCD, the display data LCD_2RD displayed on the second line in the display area of the LCD in the memory cell array 21. The memory cells 20 in the stored row are selected.

Then, the LCD side readout circuit 42 reads out the display data LCD_2RD displayed on the second line from the memory cell 20 of the line selected by the LCD side ADC circuit 41 in synchronization with the third pulse signal. Then, the read display data LCD_2RD for the second line is output to the error detection circuit 43.
The LCD-side control circuit 40 outputs a low-level error detection control signal S1 to the error detection circuit 43 during the high-level period of the third pulse signal, and then continues to generate high-level error detection control signals S0 and S2. Output to the detection circuit 43. Thereafter, the low-level error detection control signals S0 and S2 and the high-level error detection control signal S4 are output to the error detection circuit 43. Subsequently, the low-level error detection control signal S4 and the high-level error detection control signal S1 are output to the error detection circuit 43.

Accordingly, in the high-level period of the third pulse signal, in each column error detection circuit 50_0 to 50_n of the error detection circuit 43, the switch SW1 is first turned off. Subsequently, the switches SW0 and SW2 are turned on, and in the latch circuit 50a, one bit of the column corresponding to each column error detection circuit 50_0 to 50_n in the display data LCD_RD1 for the second line supplied from the LCD side reading circuit 42 is displayed. Data LRD is latched. In the latch circuit 50d, the latch signal L2 that is an output signal of the latch circuit 50c with reset is latched.
The latch signal L0 and the latch signal L2 are input to the exclusive OR circuit 50b, and an exclusive OR signal XOR indicating the exclusive OR of both is output.

  Subsequently, the switches SW0 and SW2 are turned off and the switch SW4 is turned on. The read data latch circuit 50f latches the latch signal L0 indicating the state of the read data LRD latched by the latch circuit 50a. Thereafter, the switch SW4 is turned off, the switch SW1 is turned on, and the exclusive OR signal XOR is latched by the latch circuit 50c with reset.

  Even during the third to (m−1) th high level periods of the clock signal LCD_CK, the internal CK (pulse signal PL1) similar to the second high level period is read from the LCD side control circuit 40 on the LCD side. The error detection control signals S0 to S2 and S4 similar to those in the second high level period are supplied to the circuit 42 and supplied to the error detection circuit 43. As a result, the display data LCD_3RD to (m−1) RD displayed on the third line to the (m−1) th line are read from the memory cells 20 of each line selected by the LCD side ADC circuit 41. Then, the LCD side readout circuit 42 and the error detection circuit 43 perform the same operation as in the second high level period.

Subsequently, in the m-th high level period of the clock signal LCD_CK, the same internal CK as that in the second to (m−1) -th high level period is supplied to the LCD side readout circuit 42 and displayed on the m-th line. Display data LCD_3RD to (m−1) RD are read out. Further, error detection control signals S0 to S2 and S4 similar to those in the second high-level period are supplied to the error detection circuit 43. In addition, the error detection control signal S3 detects an error at the same timing as the error detection control signal S4. It is output to the circuit 43.
Therefore, in the column error detection circuits 50_0 to 50_n, after the switches SW0 and SW2 are turned off, the switch SW3 is turned on, and the error detection output latch circuit 50e outputs the exclusive OR circuit 50b. The logical sum signal XOR is latched.

That is, in the read data for (m + 1) lines including the parity data PTD (parity line), the column error detection signal indicating the error detection result for the m-bit information data sequence of each column is supplied to the error detection output latch circuit 50e. Latched. In the column error detection circuits 50_0 to 50_n, the column error detection signals EDC0 to EDCn latched in the error detection output latch circuit 50e are output to the error detection OR circuit 51.
The error detection OR circuit 51 outputs a signal indicating the logical sum of the column error detection signals EDC0 to EDCn input from the column error detection circuits 50_0 to 50_n as the error detection signal EDC. The error detection signal EDC is a signal indicating an error detection result for m lines of data.
Thereafter, the same processing as described above is repeated k times with the number of display lines being (k × m) lines.

(Specific operation example of error detection processing)
Next, the operation at the time of error detection processing (parity check) of the semiconductor circuit device 1 of the present embodiment will be described with reference to FIG.
Here, FIG. 10 is a diagram illustrating timing charts of various signals in the column error detection operation of the column error detection circuit 50_0 when the display data CPU_WD is a 9-bit data string. Specifically, in the example of FIG. 10, the display data CPU_WD written to the memory cell array 21 is a 9-bit data string composed of 8-bit information data PID and 1-bit parity bit data PTBD.

First, the column error detection circuit 50_0 for the data string “011000110” in which the data string of the information data PID of the display data CPU_WD written from the CPU side is “01100011” and “0” is added as the parity bit data PTBD. The error detection operation will be described.
As shown in FIG. 10, the LCD side control circuit 40 first supplies the pulse signal PL1 to the LCD side readout circuit 42 as the internal CK in the first high level period of the clock signal LCD_CK supplied from the LCD.

The LCD side readout circuit 42 reads out the display data LCD_1RD corresponding to the data of the first line from the memory cell array 21 in synchronization with the first pulse signal. For convenience of explanation, it is assumed that the bit data corresponds to the first line, the second line,. . The rightmost end (lower order) is parity data.
Accordingly, the LCD side read circuit 42 reads “0” from the memory cell array 21 as read data LRD0 corresponding to the first line of the data string “011000110” in synchronization with the first pulse signal. Here, a signal corresponding to “0” is a low level signal, and a signal corresponding to “1” is a high level signal.

Further, the LCD side control circuit 40 outputs a low level error detection control signal S1 to the switch SW1 and the latch circuit 50c with reset during the high level period of the first pulse signal. As a result, the switch SW1 is turned off, and the latch circuit 50c with reset is electrically disconnected from the exclusive OR circuit 50b.
Subsequently, the LCD side control circuit 40 outputs a reset signal RST to the latch circuit with reset 50c. As a result, the latch signal of the latch circuit with reset 50c is forcibly set to the low level, and the low-level latch signal L1 is output.

  Subsequently, the LCD side control circuit 40 outputs a high-level error detection control signal S0 to the switch SW0 and the latch circuit 50a, and outputs a high-level error detection control signal S2 to the switch SW2 and the latch circuit 50d. As a result, the switch SW0 is turned on, and the LCD side read circuit 42 and the latch circuit 50a are electrically connected, and a low level read data signal LDR0 corresponding to the read “0” is generated in the latch circuit 50a. Latched. Further, the switch SW2 is turned on, the latch circuit with reset 50c and the latch circuit 50d are electrically connected, and the low level latch signal L1 output from the latch circuit with reset 50c is latched in the latch circuit 50d. .

Accordingly, the latch circuit 50a outputs the low level latch signal L0, the latch circuit 50d outputs the low level latch signal L2, and these low level latch signals L0 and L2 are input to the exclusive OR circuit 50b. . The exclusive OR circuit 50b outputs a low level exclusive OR signal XOR indicating the exclusive OR of the low level latch signals L0 and L2.
Subsequently, the LCD-side control circuit 40 outputs a low-level error detection control signal S0 to the switch SW0 and the latch circuit 50a, and outputs a low-level error detection control signal S2 to the switch SW2 and the latch circuit 50d. In addition, a high-level error detection control signal S4 is output to the switch SW4 and the read data latch circuit 50f.

  As a result, the switch SW0 is turned off and the LCD side readout circuit 42 and the latch circuit 50a are electrically disconnected. Further, the switch SW2 is turned off, and the latch circuit with reset 50c and the latch circuit 50d are electrically disconnected. Further, the switch SW4 is turned on to electrically connect the latch circuit 50a and the read data latch circuit 50f, and the read data latch circuit 50f latches the low level latch signal L0. As a result, a low level read data signal LDR0 is output from the read data latch circuit 50f to the LCD. Thereafter, the LCD side control circuit 40 outputs a low level error detection control signal S4 to the column error detection circuit 50_0. As a result, the latch circuit 50a and the read data latch circuit 50f are electrically disconnected.

  Subsequently, the LCD side control circuit 40 outputs a high-level error detection control signal S1 to the switch SW1 and the latch circuit 50c with reset, and electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset. At the same time, the switch SW1 is turned on, and the low-level exclusive OR signal XOR output from the exclusive OR circuit 50b is latched in the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Subsequently, the LCD side control circuit 40 outputs a pulse signal PL3, which is the second pulse signal, to the LCD side readout circuit 42 as the internal CK following the pulse signal PL1 in the first high level period of the clock signal LCD_CK. To do.
The LCD read circuit 42 reads the parity data 1PTD corresponding to the display data LCD_1RD from the memory cell array 21 in synchronization with the second pulse signal.

Accordingly, the LCD readout circuit 42 outputs the rightmost “0” in the data string “011000110” from the memory cell array 21 to the column error detection circuit 50_0 as the parity bit data PTBD0 in synchronization with the pulse signal PL3. .
Further, the LCD side control circuit 40 outputs the low level error detection control signal S1 to the switch SW1 and the latch circuit 50c with reset during the high level period of the second pulse signal. As a result, the switch SW1 is turned off, and the latch circuit 50c with reset is electrically disconnected from the exclusive OR circuit 50b.

  Subsequently, the LCD side control circuit 40 outputs a high-level error detection control signal S0 to the switch SW0 and the latch circuit 50a, and outputs a high-level error detection control signal S2 to the switch SW2 and the latch circuit 50d. As a result, the switch SW0 is turned on, the LCD side read circuit 42 and the latch circuit 50a are electrically connected, and the signal corresponding to the read “0” is latched in the latch circuit 50a. Further, the switch SW2 is turned on, the latch circuit with reset 50c and the latch circuit 50d are electrically connected, and the result of the previous (one previous) exclusive OR output from the latch circuit with reset 50c. A certain low level latch signal L1 is latched in the latch circuit 50d.

  Accordingly, the latch circuit 50a outputs the low level latch signal L0, the latch circuit 50d outputs the low level latch signal L2, and these low level latch signals L0 and L2 are input to the exclusive OR circuit 50b. . The exclusive OR circuit 50b outputs a low level exclusive OR signal XOR indicating the exclusive OR of the low level latch signals L0 and L2.

  Subsequently, the LCD side control circuit 40 outputs a high-level error detection control signal S1 to the switch SW1 and the latch circuit 50c with reset, and electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset. At the same time, the low-level exclusive OR signal XOR output from the exclusive OR circuit 50b is latched by the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the third pulse signal, to the LCD side readout circuit 42 as the internal CK during the second high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the second line of the data string “011000110” in synchronization with the third pulse signal.

Further, the LCD side control circuit 40 outputs the low level error detection control signal S1 to the switch SW1 and the reset latch circuit 50c during the high level period of the pulse signal PL1. As a result, the switch SW1 is turned off, and the latch circuit 50c with reset is electrically disconnected from the exclusive OR circuit 50b.
Subsequently, the LCD side control circuit 40 outputs a high-level error detection control signal S0 to the switch SW0 and the latch circuit 50a, and outputs a high-level error detection control signal S2 to the switch SW2 and the latch circuit 50d. As a result, the switch SW0 is turned on, the LCD side read circuit 42 and the latch circuit 50a are electrically connected, and a high level signal corresponding to the read “1” is latched in the latch circuit 50a. The Further, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the low level latch signal L1 output from the latch circuit with reset 50c is latched in the latch circuit 50d. .

Accordingly, the latch circuit 50a outputs a high level latch signal L0, the latch circuit 50d outputs a low level latch signal L2, and the high level latch signal L0 and the low level latch signal L2 are exclusive ORed. Input to the circuit 50b. The exclusive OR circuit 50b outputs a high level exclusive OR signal XOR indicating an exclusive OR of the high level latch signal L0 and the low level latch signal L2.
Subsequently, the LCD-side control circuit 40 outputs a low-level error detection control signal S0 to the switch SW0 and the latch circuit 50a, and outputs a low-level error detection control signal S2 to the switch SW2 and the latch circuit 50d. In addition, a high-level error detection control signal S4 is output to the switch SW4 and the read data latch circuit 50f.

  As a result, the switch SW0 is turned off and the LCD side readout circuit 42 and the latch circuit 50a are electrically disconnected. Further, the switch SW2 is turned off, and the latch circuit with reset 50c and the latch circuit 50d are electrically disconnected. Further, the switch SW4 is turned on to electrically connect the latch circuit 50a and the read data latch circuit 50f, and the read data latch circuit 50f latches the high level latch signal L0. As a result, the read data latch circuit 50f outputs a high level read data signal LDR0 to the LCD. Thereafter, the LCD side control circuit 40 outputs a low level error detection control signal S4 to the column error detection circuit 50_0. As a result, the latch circuit 50a and the read data latch circuit 50f are electrically disconnected.

  Subsequently, the LCD-side control circuit 40 outputs a high-level error detection control signal S1 to the switch SW1 and the latch circuit with reset 50c, turns on the switch SW1, and sets the exclusive OR circuit 50b and the latch circuit with reset 50c. Are electrically connected to each other, and the high-level exclusive OR signal XOR output from the exclusive OR circuit 50b is latched by the latch circuit 50c with reset. As a result, the latch signal with reset 50c outputs a high level latch signal L1.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the fourth pulse signal, to the LCD side readout circuit 42 as the internal CK in the third high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the third line of the data string “011000110” in synchronization with the fourth pulse signal.

Hereinafter, since the operation timing is the same as that of the third pulse signal, the operation is omitted as appropriate.
Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side readout circuit 42 and the latch circuit 50a, and at the same time, a high level signal corresponding to the read “1”. Is latched by the latch circuit 50a. Further, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the latch circuit 50d latches the high level latch signal L1 output from the latch circuit with reset 50c. .

Accordingly, a high level latch signal L2 is output from the latch circuit 50d, and a low level exclusive OR signal XOR indicating the exclusive OR of the high level latch signals L0 and L2 is output from the exclusive OR circuit 50b. Is output.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the high level latch signal L0. Latch. As a result, the read data latch circuit 50f outputs a high level read data signal LRD0 to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and also outputs a low level output from the exclusive OR circuit 50b. The exclusive OR signal XOR is latched by the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the fifth pulse signal, to the LCD side readout circuit 42 as the internal CK in the fourth high level period of the clock signal LCD_CK.
Accordingly, the LCD-side read circuit 42 reads “0” from the memory cell array 21 as read data LRD0 corresponding to the fourth line of the data string “011000110” in synchronization with the fifth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side read circuit 42 and the latch circuit 50a, and outputs a low level signal corresponding to the read “0”. Latching is performed in the latch circuit 50a. Similarly to the above, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the low level latch signal L1 output from the latch circuit with reset 50c is supplied to the latch circuit 50d. To latch.

Accordingly, a low level latch signal L2 is output from the latch circuit 50d, and a low level exclusive OR signal XOR indicating the exclusive OR of the low level latch signals L0 and L2 is output from the exclusive OR circuit 50b. Is done.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and applies a low level latch signal L0 to the read data latch circuit 50f. Let it latch. As a result, a low level read data signal LRD0 is output from the read data latch circuit 50f to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and also outputs a low level output from the exclusive OR circuit 50b. The exclusive OR signal XOR is latched by the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the sixth pulse signal, to the LCD side readout circuit 42 as the internal CK in the fifth high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “0” from the memory cell array 21 as read data LRD0 corresponding to the fifth line of the data string “011000110” in synchronization with the sixth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side read circuit 42 and the latch circuit 50a, and outputs a low level signal corresponding to the read “0”. Latching is performed in the latch circuit 50a. Similarly to the above, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the low level latch signal L1 output from the latch circuit with reset 50c is supplied to the latch circuit 50d. To latch.

Accordingly, a low level latch signal L2 is output from the latch circuit 50d, and a low level exclusive OR signal XOR indicating the exclusive OR of the low level latch signals L0 and L2 is output from the exclusive OR circuit 50b. Is done.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and applies a low level latch signal L0 to the read data latch circuit 50f. Let it latch. As a result, a low level read data signal LRD0 is output from the read data latch circuit 50f to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and also outputs a low level output from the exclusive OR circuit 50b. The exclusive OR signal XOR is latched by the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the seventh pulse signal, to the LCD side readout circuit 42 as the internal CK in the sixth high level period of the clock signal LCD_CK.
Accordingly, the LCD-side read circuit 42 reads “0” from the memory cell array 21 as read data LRD0 corresponding to the sixth line of the data string “011000110” in synchronization with the seventh pulse signal.
Since the subsequent processing is the same as that in the fifth high level period, description thereof is omitted.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the eighth pulse signal, to the LCD side readout circuit 42 as the internal CK during the seventh high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the seventh line of the data string “011000110” in synchronization with the eighth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side readout circuit 42 and the latch circuit 50a, and at the same time, a high level signal corresponding to the read “1”. Is latched in the latch circuit 50a. Similarly to the above, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the low level latch signal L1 output from the latch circuit with reset 50c is supplied to the latch circuit 50d. To latch.

Accordingly, the latch circuit 50d outputs a low level latch signal L2, and the exclusive OR circuit 50b outputs a high level exclusive OR indicating an exclusive OR of the high level latch signal L0 and the low level latch signal L2. A logical sum signal XOR is output.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the high level latch signal L0. Latch. As a result, the read data latch circuit 50f outputs a high level read data signal LRD0 to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and outputs a high level output from the exclusive OR circuit 50b. The exclusive OR signal XOR is latched by the latch circuit with reset 50c. As a result, the latch signal with reset 50c outputs a high level latch signal L1.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the ninth pulse signal, to the LCD side readout circuit 42 as the internal CK in the eighth high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the eighth line of the data string “011000110” in synchronization with the ninth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side readout circuit 42 and the latch circuit 50a, and at the same time, a high level signal corresponding to the read “1”. Is latched in the latch circuit 50a. Similarly to the above, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and a high level latch signal L1 output from the latch circuit with reset 50c is supplied to the latch circuit. Latch at 50d.

Accordingly, a high level latch signal L2 is output from the latch circuit 50d, and a low level exclusive OR signal XOR indicating the exclusive OR of the high level latch signals L0 and L2 is output from the exclusive OR circuit 50b. Is output.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the high level latch signal L0. Latch. As a result, the read data latch circuit 50f outputs a high level read data signal LRD0 to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and also outputs a low level output from the exclusive OR circuit 50b. The exclusive OR signal XOR is latched by the latch circuit 50c with reset. As a result, a low level latch signal L1 is output from the latch circuit 50c with reset.

Subsequently, the LCD side control circuit 40 outputs a high level error detection control signal S3 to the switch SW3 and the error detection output latch circuit 50e. As a result, the switch SW3 is turned on, and the exclusive OR circuit 50b and the error detection output latch circuit 50e are electrically connected. Therefore, in the error detection output latch circuit 50e, the low level exclusive OR signal XOR output from the exclusive OR circuit 50b is latched, and the low level column error detection signal EDC0 is output to the error detection OR circuit 51. Is done.
That is, it is detected that there is no error in the read data string. If all the column error detection signals EDC1 to EDCn in other columns are low level signals, the error detection OR circuit 51 outputs a low level error detection signal EDC, and if there is at least one high level signal, The error detection OR circuit 51 outputs a high level error detection signal EDC.

Next, the operation of error detection processing when an error has occurred in the read data corresponding to the third line of the data string “011000110” will be described.
Since the first and second lines are the same as the error detection operation when there is no error, the error detection operation for the third and subsequent lines will be described below.
The LCD control circuit 40 supplies a pulse signal PL1, which is the fourth pulse signal, to the LCD readout circuit 42 as the internal CK during the third high level period of the clock signal LCD_CK.

  Therefore, the LCD side read circuit 42 reads the read data LRD0 corresponding to the third line of the data string “011000110” from the memory cell array 21 in synchronization with the fourth pulse signal. At this time, as shown by the dotted waveform in FIG. 10, the read data corresponding to the third line changes from “1” to “0” at the time of data writing, at the time of data reading or inside the memory cell 20. Assume that “0” is read as the read data LRD0.

Hereinafter, the operation timing is the same as that of the third and subsequent pulse signals when there is no error.
The LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side read circuit 42 and the latch circuit 50a, and outputs a low level signal corresponding to the read “0”. Latching is performed in the latch circuit 50a. Further, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the latch circuit 50d latches the high level latch signal L1 ′ output from the latch circuit with reset 50c. Let me.

  Accordingly, the latch circuit 50a outputs a low level latch signal L0 ′, the latch circuit 50d outputs a high level latch signal L2 ′, and the low level latch signal L0 ′ and the high level latch signal L2 ′ are Input to the exclusive OR circuit 50b. The exclusive OR circuit 50b outputs a high level exclusive OR signal XOR 'indicating the exclusive OR of the low level latch signal L0' and the high level latch signal L2 '.

  Subsequently, the LCD side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the low level latch signal L0 ′. Latch. As a result, a low level read data signal LRD0 is output from the read data latch circuit 50f to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and outputs a high level output from the exclusive OR circuit 50b. The exclusive OR signal XOR ′ is latched by the latch circuit 50c with reset. As a result, the latch signal with reset 50c outputs a high level latch signal L1 '.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the fifth pulse signal, to the LCD side readout circuit 42 as the internal CK in the fourth high level period of the clock signal LCD_CK.
Accordingly, the LCD-side read circuit 42 reads “0” from the memory cell array 21 as read data LRD0 corresponding to the fourth line of the data string “011000110” in synchronization with the fifth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side read circuit 42 and the latch circuit 50a, and outputs a low level signal corresponding to the read “0”. The latch circuit 50a latches. Further, the switch SW2 is turned on to electrically connect the latch circuit 50c with reset and the latch circuit 50d, and the high level latch signal L1 ′ output from the latch circuit 50c with reset is latched in the latch circuit 50d. Let

Accordingly, the latch circuit 50d outputs a high level latch signal L2 ′, and the exclusive OR circuit 50b outputs an exclusive OR of the low level latch signal L0 ′ and the high level latch signal L2 ′. A level exclusive OR signal XOR 'is output.
Subsequently, the LCD side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the low level latch signal L0 ′. Latch. As a result, a low level read data signal LRD0 is output from the read data latch circuit 50f to the LCD.

Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and outputs a high level output from the exclusive OR circuit 50b. The exclusive OR signal XOR ′ is latched by the latch circuit 50c with reset. As a result, the latch signal with reset 50c outputs a high level latch signal L1 ′.
In the subsequent fifth to sixth high level periods, the operation is the same as in the fourth high level period, and the latch circuit with reset 50c outputs a high level latch signal L1 ′.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the eighth pulse signal, to the LCD side readout circuit 42 as the internal CK during the seventh high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the seventh line of the data string “011000110” in synchronization with the eighth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side readout circuit 42 and the latch circuit 50a, and at the same time, a high level signal corresponding to the read “1”. Is latched by the latch circuit 50a. Further, the switch SW2 is turned on to electrically connect the latch circuit 50c with reset and the latch circuit 50d, and the high level latch signal L1 ′ output from the latch circuit 50c with reset is latched in the latch circuit 50d. Let

Accordingly, a high level latch signal L2 ′ is output from the latch circuit 50d, and a low level exclusive logic indicating the exclusive OR of the high level latch signals L0 ′ and L2 ′ is output from the exclusive OR circuit 50b. A sum signal XOR ′ is output.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the high level latch signal L0. 'Latch. As a result, the read data latch circuit 50f outputs a high level read data signal LRD0 to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and also outputs a low level output from the exclusive OR circuit 50b. The exclusive OR signal XOR ′ is latched by the latch circuit with reset 50c. As a result, the latch signal with reset 50c outputs a low level latch signal L1 '.

Next, the LCD side control circuit 40 supplies a pulse signal PL1, which is the ninth pulse signal, to the LCD side readout circuit 42 as the internal CK in the eighth high level period of the clock signal LCD_CK.
Accordingly, the LCD side read circuit 42 reads “1” from the memory cell array 21 as read data LRD0 corresponding to the seventh line of the data string “011000110” in synchronization with the ninth pulse signal.

Further, the LCD side control circuit 40 turns off the switch SW1 so that the latch circuit with reset 50c and the exclusive OR circuit 50b are electrically disconnected.
Subsequently, the LCD side control circuit 40 turns on the switch SW0 to electrically connect the LCD side readout circuit 42 and the latch circuit 50a, and at the same time, a high level signal corresponding to the read “1”. Is latched by the latch circuit 50a. Further, the switch SW2 is turned on to electrically connect the latch circuit with reset 50c and the latch circuit 50d, and the latch circuit 50d latches the low-level latch signal L1 ′ output from the latch circuit with reset 50c. .

Accordingly, a low level latch signal L2 ′ is output from the latch circuit 50d, and a high level indicating the exclusive OR of the high level latch signal L0 ′ and the low level latch signal L2 ′ is output from the exclusive OR circuit 50b. Is output as an exclusive OR signal XOR ′.
Subsequently, the LCD-side control circuit 40 turns on the switch SW4 to electrically connect the latch circuit 50a and the read data latch circuit 50f, and to the read data latch circuit 50f, the high level latch signal L0. 'Latch. As a result, the read data latch circuit 50f outputs a high level read data signal LRD0 to the LCD.

  Subsequently, the LCD-side control circuit 40 turns on the switch SW1, electrically connects the exclusive OR circuit 50b and the latch circuit 50c with reset, and outputs a high level output from the exclusive OR circuit 50b. The exclusive OR signal XOR ′ is latched by the latch circuit 50c with reset. As a result, the latch signal with reset 50c outputs a high level latch signal L1 '.

  Subsequently, the LCD side control circuit 40 outputs a high level error detection control signal S3 to the switch SW3 and the error detection output latch circuit 50e. As a result, the switch SW3 is turned on, and the exclusive OR circuit 50b and the error detection output latch circuit 50e are electrically connected. Accordingly, in the error detection output latch circuit 50e, the high-level exclusive OR signal XOR output from the exclusive OR circuit 50b is latched, and the high-level column error detection signal EDC0 is converted into the error detection OR circuit 51. Is output.

That is, it is detected that there is an error in the read data string. In this case, even if all the column error detection signals EDC1 to EDCn in other columns are low level signals, the error detection OR circuit 51 outputs a high level error detection signal EDC.
As described above, in the semiconductor circuit device 1 according to the present embodiment, in the error detection circuit 43, the display data LCD_RD read from the LCD side read circuit 42 in units of lines and the parity data PTD read out from the LCD side read circuit 42 in units of lines. And get. In the column error detection circuits 50_0 to 50_n of the error detection circuit 43, the parity check can be performed on the display data CPU_WD0 to WDn corresponding to the display data LCD_RD.

Further, the LCD-side control circuit 40 generates two internal CKs that provide a read timing to be supplied to the LCD-side read circuit 42 in the same cycle as the cycle of the clock signal LCD_CK when the display data for the first line is read. A pulse signal can be generated.
Then, the error detection circuit 43 supplies the display data for the first line, the parity data, and the parity data in a cycle in which the display data for the first line is read by the two pulse signals supplied from the LCD side control circuit 40. Can be read out.

In the column error detection circuits 50_0 to 50_n, the latch circuits 50a and 50d, the reset-equipped latch circuit 50c, and the exclusive OR circuit 50b read the display data and the bit data of the parity data sequentially read out. In order, an exclusive OR operation can be performed on each bit data and the previous operation result.
As a result, the exclusive OR operation can be executed sequentially while looping without reading all the data in the column direction corresponding to the parity data, so there is no need for a register for holding all the data corresponding to the parity data. It can be. Further, since it is not necessary for the CPU to have a dedicated address for reading the parity data, it is not necessary to modify the existing CPU when accessing the semiconductor circuit device 1 of the present embodiment. .

In the above embodiment, the CPU-side data R / W unit 3 corresponds to data writing means, and the LCD-side control circuit 40, the LCD-side address decoder circuit 41, and the LCD-side reading circuit 42 in the LCD-side data reading unit 4 are Corresponds to the data read circuit.
In the above embodiment, the error detection circuit 43 in the LCD side data reading unit 4 corresponds to an error detection circuit, and the column error detection circuits 50_0 to 50_n correspond to column error detection circuits.

  In the above embodiment, two pulse signals are generated in the same cycle as the cycle of the clock signal LCD_CK when reading the display data of the first line from the memory cell array 21, and the display data of the first line Although the configuration is such that the parity data corresponding to the display data is read, the present invention is not limited to this configuration. As long as the line corresponds to the parity data to be read, the parity data may be read out in the same cycle as the cycle for reading data in the second and subsequent lines.

In the above embodiment, the timing at which the error detection control signal S1 is set to the high level (the timing at which the switch SW1 is turned on) is set to the timing shown in the timing charts of FIG. 9 and FIG. Not limited to. Any timing can be used as long as the switches SW0 and SW2 are turned off (but before the next pulse signal rises).
Further, the configuration of the memory cell array 21 is limited to the dual port SRAM. However, the memory cell array 21 is not limited to this configuration, and the memory cell array 21 can be configured to be a DRAM configuration. Any other memory configuration may be used.

In the above embodiment, only the data reading is performed via the second access port. However, the present invention is not limited to this configuration, and both the data writing and reading are performed via the second access port. It is good also as composition which performs.
The above embodiments are preferable specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the above description. As long as there is no description, it is not restricted to these forms. In the drawings used in the above description, for convenience of illustration, the vertical and horizontal scales of members or parts are schematic views different from actual ones.
Further, the present invention is not limited to the above-described embodiment, and modifications, improvements, and the like within a scope that can achieve the object of the present invention are included in the present invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor circuit device, 2 ... Memory part, 3 ... CPU side read / write part, 4 ... LCD side read part, 30 ... CPU side control circuit, 31 ... CPU side row address decoder circuit, 32 ... CPU side column address decoder Circuit: 33... CPU side data read / write unit, 40... LCD side control circuit, 40 a... First pulse generation circuit, 40 b... Delay circuit, 40 c .. second pulse generation circuit, 40 d. LCD side address decoder circuit, 42 ... LCD side readout circuit, 43 ... error detection circuit, 50_0 to 50_n ... column error detection circuit, 51 ... error detection OR circuit, 50a, 50d ... latch circuit, 50b ... exclusive OR circuit 50c ... Latch circuit with reset, 50e ... Latch circuit for error detection output, 50f ... Latch circuit for read data, Tr1-PTr4 ... PMOS transistor, NTr1-NTr4 ... NMOS transistor, N1, N2 ... Storage node, INV1 ... First inverter circuit, INV2 ... Second inverter circuit, N0-N4 ... NOT gate, TN0-TN8 ... Clocked Inverter, NA0 ... NAND gate, ORA0-ORAn, ORB0, ORB1 ... OR gate, A0-A3 ... AND gate

Claims (6)

A memory cell array having a configuration in which a plurality of memory cells are arranged in a matrix;
A first access port for accessing data to the memory cell array;
A second access port for accessing data to the memory cell array;
A data writing circuit for writing a first data string including a plurality of bit data and parity bit data corresponding to the plurality of bit data to the memory cell array via the first access port;
A data read circuit for reading a second data string, which is a data string orthogonal to the first data string, from the memory cell array via the second access port;
An error detection circuit for detecting an error in data read from the memory cell array by the data read circuit,
The error detection circuit includes:
With column error detection circuit,
The error detection circuit acquires a plurality of the second data strings read by the data reading unit,
The semiconductor circuit device, wherein the column error detection circuit performs a parity check based on the first data sequence included in the plurality of second data sequences.   The semiconductor circuit device according to claim 1, wherein the column error detection circuit performs a parity check on the plurality of second data columns acquired in time series.   The column error detection circuit includes, for each bit data including the parity bit data of the first data sequence corresponding to the plurality of acquired second data sequences, the acquired bit data in the acquisition order of the bit data and The operation related to the parity check using the previous operation result is sequentially performed, and the operation result for each of the first data strings corresponding to the plurality of acquired second data strings is output as the result of the parity check. The semiconductor circuit device according to claim 2. The parity bit data is data corresponding to a parity code,
4. The semiconductor circuit device according to claim 3, wherein the column error detection circuit performs an exclusive OR operation as the operation related to the parity check. The data reading circuit reads the second data string in a time series in units of columns in synchronization with a reference clock signal supplied from a reading destination of the second data string.
The column error detection circuit is configured to acquire the second data string in time series in units of columns in synchronization with the reference clock signal, and the reference clock when acquiring the second data string 5. The semiconductor circuit device according to claim 3, wherein the parity bit data is acquired within the same period as one period of the signal. A memory cell array having a plurality of memory cells arranged in a matrix, a first access port for accessing data to the memory cell array, and a second access for accessing data to the memory cell array A data write circuit for writing a first data string including a plurality of bit data and parity bit data corresponding to the plurality of bit data to the memory cell array via a port and the first access port; For a semiconductor circuit device comprising: a data read circuit that reads a second data string that is a data string orthogonal to the first data string from the memory cell array via the second access port; An error detection circuit for detecting an error in data read by a data reading circuit,
Obtaining a plurality of the second data strings read by the data reading means;
An error detection circuit comprising: a column error detection circuit that performs a parity check based on each of the first data sequences included in the plurality of acquired second data sequences.

Images