JP2012042276A - Semiconductor testing device and method for detecting off capacity abnormality of relay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect whether or not there is an abnormality in the off capacity of a relay provided in a semiconductor tenting device.SOLUTION: The semiconductor testing device has a test section 1 including a driver circuit 10 and a comparator circuit 11 for testing a DUT 2. The semiconductor testing device has an abnormality detecting section 36 which turns off the relay to be tested out of a plurality of relays provided in the test section 1, outputs a voltage or a current to detect the voltage from the relay and, on the basis of temporal changes in the detected voltage, detects whether or not there is an abnormality in the off capacity of the relay. Thus, whether or not there is an abnormality in the off capacity of the relay can be detected before calibrating the operation timing of the driver circuit 10 and the comparator circuit 11.

Description

  The present invention relates to a semiconductor test apparatus for testing a device under test, and more particularly to a semiconductor test apparatus for adjusting timing and a relay off-capacity abnormality detection method for detecting an off-capacity of a relay provided in the semiconductor test apparatus.

  2. Description of the Related Art Conventionally, a semiconductor test apparatus that applies a predetermined test signal to a device under test (DUT) and determines pass / fail based on a response signal output from the device under test has been used. The semiconductor test apparatus includes a pin electronics card as a test unit, and tests a DUT connected to the pin electronics card. The pin electronics card is provided with a plurality of driver circuits for applying test signals and comparator circuits for comparing response signals.

  Each driver circuit applies a test signal at the same timing, and each comparator circuit compares response signals at the same timing. For this purpose, the operation timing is calibrated using a timing calibration device that calibrates the timing. This type of technology is disclosed in Patent Document 1.

  An outline of the technique of Patent Document 1 will be described with reference to FIG. This semiconductor test apparatus mainly includes a test unit 101, and a DUT 102 is connected to the test unit 101. The test unit 101 includes N (N is a natural number) driver circuits 111, M (M is a natural number) comparator circuits 112, a timing calibration device 113, and a DC measurement unit 114.

  The driver circuit 111 is a test circuit that applies a test signal to the DUT 102, and the comparator circuit 112 is a test circuit that compares the response signal output from the DUT 102 with a predetermined reference value. In this example, the driver circuit 111 is configured more than the comparator circuit 112 (N> M).

  The timing calibration device 113 exchanges timing calibration signals with a test circuit (driver circuit 111 or comparator circuit 112) to be subjected to timing calibration. The timing of the test circuit is calibrated by unifying the transfer times for each test circuit. The DC measurement unit 114 outputs a voltage or current to each test circuit, and performs self-diagnosis to detect whether there is an abnormality in the output voltage, output impedance, leak current, etc. of each test circuit.

  The timing calibration device 113 and the test circuit are connected by a calibration path 115, and the calibration path 115 has a tournament structure that branches from one path to a plurality of paths. Each calibration path 115 is provided with a calibration system relay 116, and the calibration path 115 and the calibration system relay 116 constitute a relay tournament 116T.

  The DC measurement unit 114 and the test circuit are connected by a force line 117 and a sense line 118. The force line 117 is a path for outputting voltage or current to the test circuit, and the sense line 118 is a path for inputting voltage from the test circuit.

  Each force line 117 is provided with a force relay 119, and each sense line 118 is provided with a sense relay 120. Thereby, the DC measurement unit 114 and the test circuit are connected to perform self-diagnosis. The path between the test circuit and the DUT 102 constitutes a test path 121 for applying a test signal, and the test path 121 is provided with a test relay 122 that turns the path on or off. And the relay control part 123 for controlling ON or OFF of each relay is provided.

  In the technique of Patent Document 1, an interrupt signal path and a control relay that can connect the DC measurement unit 114 and the calibration signal path are provided. As a result, the self-diagnosis function is realized while the DUT 102 is connected without increasing the board area and the component cost.

JP 2008-203073 A

  The timing calibration device 113 exchanges timing calibration signals with the test circuit to be calibrated, and detects the time until the timing calibration signal is input to the timing calibration device 113. Then, the time is detected for all the test circuits, and the timing calibration is performed so as to eliminate the error occurring during the detected time.

  Since the timing calibration signal is transmitted between the test circuit and the timing calibration device 113, the calibration system relay 116 and the test relay 122 on the path connected to the path of the timing calibration signal are in the OFF state. These relays have an off-capacitance, and when the off-capacity is abnormal, the timing calibration signal is affected, and as a result, the timing calibration cannot be performed accurately.

  There are various factors that cause abnormalities in the relay's off-capacity, such as incorrect relay mounting and changes in the off-capacity over time. The waveform of the timing calibration signal is rounded (degraded). As a result, the rise (or fall) of the waveform of the timing calibration signal becomes gentler (slower) than that of the original waveform.

  The timing calibration device 113 detects the voltage of the timing calibration signal, and detects the input of the timing calibration signal when the input voltage reaches a predetermined threshold value. Therefore, if a waveform rounding occurs in the timing calibration signal, an error occurs with respect to the originally detected time. Due to this time error, timing calibration of the test circuit cannot be performed accurately.

  Therefore, an object of the present invention is to detect whether or not an abnormality has occurred in the off-capacity of a relay provided in a semiconductor test apparatus.

  In order to solve the above problems, a first semiconductor test apparatus of the present invention is a semiconductor test apparatus including a test unit provided with a test circuit for testing a device under test, and is provided in the test unit. The relay to be inspected is turned off and a voltage or current is output to detect the voltage from the relay, and an abnormality occurs in the off-capacity of the relay based on a temporal change of the detected voltage. It is characterized by having an anomaly detector that detects whether or not it is present.

  According to this semiconductor test apparatus, the current or voltage output to the relay is detected to detect a temporal change in the detected voltage. This makes it possible to detect whether or not there is an abnormality in the off-capacity of the relay because the temporal voltage change differs between when the off-capacity is abnormal and when it is normal. .

  The second semiconductor test apparatus according to the present invention is the first semiconductor test apparatus, wherein the abnormality detection unit reaches a second threshold whose detected voltage is higher than the first threshold from the first threshold. A time measurement unit that measures the time until the measurement is performed as an actual measurement time, and the time from the first threshold value when the off-capacitance is not abnormal to the second threshold value as a reference time. And a processing unit that determines whether or not the abnormality has occurred based on a time difference between the actual measurement time measured by the measurement unit and the reference time.

  According to this semiconductor test apparatus, a temporal change in the detection voltage can be recognized by comparing the actual measurement time with the reference time. Thereby, it becomes possible to detect whether or not an abnormality occurs in the off-capacity of the relay.

  The third semiconductor test apparatus of the present invention is the second semiconductor test apparatus, wherein the processing unit is an ideal path capacity of a path between the relay to be inspected and the abnormality detection unit, the inspection The off-capacity of the relay to be inspected is detected based on the arrival time and the time difference when there is no off-capacity of the target relay.

  According to this semiconductor test apparatus, the off-capacity of the relay to be inspected can be detected. As a result, it is possible to detect whether or not there is an abnormality in the off-capacity based on the detected off-capacity of the relay, so that a more direct inspection is possible.

  A fourth semiconductor test apparatus of the present invention is a third semiconductor test apparatus, which transmits and receives a timing calibration signal to / from a test circuit to be subjected to timing calibration among the test circuits. The timing calibration unit calibrates the operation timing of the test circuit based on the transfer time of the test circuit, and the timing calibration unit is an off-state relay connected to a path between the test circuit and the timing calibration unit. Detecting an error in timing calibration based on the combined capacity based on the combined capacity of the off-capacitance, the ideal path capacity of the path, and the time until the timing calibration signal is detected when the combined capacity is zero In the timing calibration of the test circuit, the error is adjusted and the timing calibration is performed.

  According to this semiconductor test apparatus, based on the off-capacity of the relay provided in the path connected to the path of the timing calibration signal, it is possible to perform timing calibration in consideration of the influence of the off-capacitance on the timing calibration signal. This makes it possible to perform timing calibration that eliminates the influence of the relay off-capacitance.

  A fifth relay off-capacity abnormality detection method according to the present invention is a relay off-capacity abnormality detection method for detecting a relay off-capacity abnormality provided in a test unit for testing a device under test. While the relay to be inspected is turned off, a current or voltage is applied to the relay to detect the voltage from the relay, and the relay is turned off based on a temporal change in the detected voltage. It is characterized by detecting whether or not an abnormality has occurred in the capacity.

  The present invention applies a current or a voltage to a target whose off-capacity is to be detected, detects the voltage, and detects whether the off-capacity of the relay is abnormal by detecting a temporal change in the detected voltage. Can be detected.

1 is a configuration diagram of a semiconductor test apparatus according to an embodiment. It is a block diagram of DC measurement unit. It is the figure which showed the waveform of the voltage. It is a block diagram of the conventional semiconductor test apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a semiconductor test apparatus of the present invention. The semiconductor test apparatus includes a test unit 1, and a DUT (Device Under Test) 2 to be tested is connected to the test unit 1. The test unit 1 functions as a test unit that determines the quality of the DUT 2, and for example, a pin electronics card can be applied. A plurality of DUTs 2 may be connected to the test unit 1, and a plurality of test units 1 may be provided in a semiconductor test apparatus.

  The test unit 1 includes a driver circuit 10, a comparator circuit 11, a timing calibration device 12, a DC measurement unit 13, and a relay control unit 14. The driver circuit 10 is a test circuit that applies a test signal to the DUT 2 at a predetermined timing (latch timing), and the comparator circuit 11 compares the response signal output from the DUT 2 at a predetermined timing with a reference value to perform pass / fail judgment. Circuit.

  The driver circuit 10 includes N (N is a natural number), and the comparator circuit 11 includes M (M is a natural number: M <N). Therefore, the number of driver circuits 10 is larger than the number of comparator circuits 11. Of course, the number may be the same, or the number of comparator circuits 11 may be increased.

  All the input terminals of the comparator circuit 11 are connected to the output terminal of the driver circuit 10. On the other hand, since the “N−M” number of driver circuits 10 are not connected to the comparator circuit 11, the driver circuit 10 is configured by itself. Note that the driver circuit 10 and the comparator circuit 11 may not be connected and all may be configured independently.

  The timing calibration device 12 is a timing calibration unit that performs timing calibration of the driver circuit 10 and the comparator circuit 11. The timing calibration device 12 exchanges timing calibration signals with a test circuit (driver circuit 10 or comparator circuit 11) to be calibrated.

  The timing calibration device 12 detects the time until the timing calibration signal output from the test circuit is input (or may detect the time for the timing calibration signal to reciprocate between the timing calibration device 12 and the test circuit). . Timing calibration signals are exchanged with all test circuits, and time detection is performed for each test circuit. When the detected times differ for each test circuit, timing calibration is performed to calibrate the operation timing of the test circuit.

  The calibration path 15 serving as the path of the timing calibration signal connected to the timing calibration device 12 branches into a plurality of branches. A plurality of branched calibration paths 15 are branched. That is, the tournament structure has a plurality of branch stages. Finally, it branches to N calibration paths 15 and is connected to N driver circuits 10.

  Although one calibration path 15 can be branched into N (branch in one stage), a tournament structure divided into a plurality of stages allows the path length from the timing calibration device 12 to each test circuit, etc. We are trying to lengthen it. This suppresses the influence of the timing calibration signal on the transmission characteristics.

  A calibration system relay 16 is provided in the calibration path 15 of the tournament structure, whereby a relay tournament 17 is configured. By turning the calibration relay 16 on or off, the timing calibration device 12 and one specific test circuit are connected.

  The DC measuring unit 13 inputs voltage or current to each test circuit and detects the voltage from the test circuit. As a result, self-diagnosis is performed as to whether or not a circuit abnormality such as an output voltage or output impedance abnormality or a leakage current is detected. For this purpose, a force line 18 for outputting voltage or current and a sense line 19 for inputting voltage are provided. The sense line 19 is provided with a resistor 20.

  The force line 18 and the sense line 19 are branched into N lines. Then, one force line 18 and one sense line 19 join one test path 21. N test paths 21 are provided and connect between the driver circuit 10 and the DUT 2. The test path 21 is provided with a test relay 22 that switches the test path 21 on or off, and switches between the DUTs 2 to be connected or disconnected.

  A force relay 23 is provided on the force line 18 after branching, and a sense relay 24 is provided on the sense line 19 after branching. Accordingly, N force relays 23 and sense relays 24 are provided.

  FIG. 2 shows the configuration of the DC measurement unit 13 as an abnormality detection unit, and includes an output control unit 31, a current / voltage output unit 32, a voltage detection unit 33, a sampling unit 34, a time measurement unit 35, a processing unit 36, and a data storage. A portion 37 is provided. The output control unit 31 controls the current / voltage output unit 32 to output voltage or current. The current / voltage output unit 32 is connected to the force line 18 and outputs a voltage or a current to the force line 18.

  The voltage or current input to the inspection target via the force line 18 is input to the voltage detection unit 33 via the sense line 19. The voltage detector 33 detects a voltage input from the sense line, and inputs the detected voltage to the sampling unit 34. The sampling unit 34 performs sampling to detect a voltage value with a predetermined resolution in the time axis direction of the input voltage. Thereby, a change in voltage over time is recognized.

  The time measuring unit 35 measures time based on the voltage value detected by the sampling unit 34. The time measurement starts when the detected voltage reaches the threshold VL (first threshold), and ends when the threshold voltage VH (second threshold) higher than the threshold VL is reached. At this time, the time measured by the time measurement unit 35 is set as the actual measurement time T1, and data of the actual measurement time T1 is output to the processing unit 36.

  The processing unit 36 reads out the reference time T2 from the data storage unit 37 and compares the reference time T2 with the actually measured time T1 to detect whether or not an abnormality occurs in the off-capacity of the relay. The reference time T2 is the time until the detected voltage reaches the threshold value VL from the threshold value VL when the off-capacity of each relay is normal. The processing unit 36 performs abnormality detection by comparing the actual measurement time T1 and the reference time T2.

  The reference time T2 is a time when the off-capacity of the relay is normal, and is known information obtained from specifications and designs. Therefore, the reference time T2 can be stored in the data storage unit 37 for each relay. Each reference time T2 may be obtained by actual measurement under a condition in which no abnormality occurs in the off-capacitance.

  The relay control unit 14 performs on / off control of each relay and individually controls the relays. Control of the relay control unit 14 determines a route such as a timing calibration signal and a voltage and current from the DC measurement unit 13.

  Next, the operation will be described. The timing calibration device 12 performs timing calibration by exchanging timing calibration signals with a test circuit (driver circuit 10A) to be calibrated. At this time, the timing calibration signal is transmitted through a path between the driver circuit 10A and the timing calibration device 12.

  In order to transmit the timing calibration signal from the driver circuit 10A to the timing calibration device 12, the calibration relay 16 on the timing calibration signal path is turned on, but the relay of the path connected to the timing calibration signal path is Control off. Thereby, a specific path can be transmitted to the timing calibration signal.

  There are a calibration relay 16 and a test relay 22 as relays of the path connected to the path of the timing calibration signal. These relays are turned off. At this time, each relay in the off state has an off capacity, and the off capacity affects the timing calibration signal.

  When the off-capacity of the relay is large, the timing calibration signal waveform is distorted. The timing calibration device 12 detects the timing calibration signal with a voltage, and detects the input of the timing calibration signal when a predetermined voltage is reached. Therefore, when the waveform is rounded, an error occurs in the timing of detection of the timing calibration signal as compared with the case where the off-capacitance is normal. This error makes it impossible to ensure the accuracy of timing calibration.

  Therefore, it is checked in advance whether or not an abnormality occurs in the off-capacity of the relay connected to the path of the timing calibration signal. The inspection object is a relay that affects the timing calibration signal. Therefore, the calibration relay 16 and the test relay 22 are to be inspected as relays connected to the timing calibration signal path.

  An off-capacity abnormality is detected for all these relays. The off-capacitance abnormality detection is performed by the DC measurement unit 13 as an abnormality detection unit. Hereinafter, the inspection target will be described as one of the calibration relays 16 (calibration relay 16A).

  First, the relay control unit 14 performs various relay controls so that the DC measurement unit 13 and the calibration system relay 16A are connected and the others are not connected. Accordingly, the relays (the calibration relay 16 and the test relay 22) of the path connected to the path connecting the DC measurement unit 13 and the calibration relay 16A (path through which the timing calibration signal is transmitted) are turned off.

  In this state, the output control unit 31 of the DC measurement unit 13 outputs a predetermined voltage VF from the current / voltage output unit 32. The output voltage VF is input from the force line 18 through the test path 21 to the calibration relay 16A. At this time, the test circuit is set to a high impedance state or the like so that the voltage VF is not input to the test circuit.

  The calibration relay 16A to be inspected is controlled to be turned off. As a result, the voltage VF input to the calibration relay 16A is input to the DC measurement unit 13 via the test path 21 and the sense line 19 as it is. This voltage VF is detected by the voltage detection unit 33, and the voltage value is sampled by the sampling unit 34 every predetermined time.

  The voltage detected by the voltage detector 33 increases from 0 volts over time. The time measuring unit 35 measures the time until the voltage changes from the threshold value VL to the threshold value VH as the actual measurement time T1. The data of the actual measurement time T1 is output to the processing unit 36. The processing unit 36 reads the reference time T2 corresponding to the calibration relay 16A from the data storage unit 37, and compares the measured time T1 with the reference time T2.

  A solid line in FIG. 3 indicates a change in voltage when the off-capacitance of the calibration system relay 16A is in an ideal state, and a broken line in FIG. 3 indicates a change in voltage when the off-capacitance of the calibration system relay 16A is abnormal. . A plurality of arrows arranged in parallel in the time axis (t) direction in FIG. As shown in the figure, when the off-capacitance is abnormal, the waveform is rounded and the rising of the waveform is slowed down. Thereby, the actual measurement time T1 from reaching the threshold value VL to VH is later than the reference time T2.

  The processing unit 36 obtains a time difference between the actual measurement time T1 and the reference time T2. If the time difference is within the allowable range, it is determined that the off-capacitance of the calibration relay 16A is normal, and if it is outside the allowable range, it is determined that the off-capacity is abnormal. Thereby, it is detected whether or not the off-capacitance is abnormal.

  Therefore, it is possible to detect whether or not there is an abnormality in the off-capacity of the calibration relay 16A to be inspected. All relays that affect the timing calibration signal are inspected as to whether or not the off-capacitance is abnormal, and when all are recognized to be normal, the accuracy of timing calibration is guaranteed. On the other hand, if an abnormality has occurred, it will be recognized that the accuracy of timing calibration is not guaranteed.

  Here, the off-capacity abnormality is detected based on the time difference between the actual measurement time T1 and the reference time T2, and this time difference indicates a temporal change in the voltage detected by the voltage detector 33. That is, since the threshold values VL and VH are fixed, the temporal change of the detection voltage is indicated by the actual measurement time T1 and the reference time T2.

  Therefore, it is only necessary to be able to recognize a temporal change in the detection voltage. For example, by fixing the time detected by the voltage detection unit 33 and detecting the degree of increase in the voltage during the time, the temporal change in the detection voltage is also possible. Can be recognized. This also enables off-capacity abnormality detection.

  Next, Modification 1 will be described. In this modification, the off capacity (referred to as CX1) of the calibration relay 16A to be inspected is obtained. As described above, the voltage (voltage value VF) is output from the DC measurement unit 13, and the voltage returned from the calibration relay 16A is detected. Thereby, the actual measurement time T1 is obtained.

The ideal capacity (path capacity) of the path between the DC measurement unit 13 and the calibration system relay 16A is CX2, and the resistance of the path is RX. In addition, the time from reaching the threshold value VL to VH when the off-capacitance of the calibration relay 16A is zero is defined as an ideal time T3. At this time, if the off-capacity of the calibration relay 16A is zero, the following formula 1 is established.
“VH = VF × (1-exp (−T3 / (CX2 × RX)))” (Formula 1)

On the other hand, an off-capacitance CX1 is generated in the calibration relay 16A. Due to this off-capacitance, a delay of Δtx from the ideal time T3 occurs. Therefore, Equation 1 becomes Equation 2 below.
“VH = VF × (1−exp (− (T3 + Δtx) / ((CX2 + CX1) × RX)))” (Formula 2)

  In Equations 1 and 2, the threshold VL is assumed to be 0 volts for simplicity. From Expression 1 and Expression 2, “CX1 = Δtx × CX2 / T3” (Expression 3) is obtained. Δtx is the difference between the ideal time T3 and the actual measurement time T1 (Δtx = T1−T3), the ideal time T3 is obtained as known, and the actual measurement time T1 is obtained by measurement, so Δtx is obtained.

  The ideal path capacity CX2 and ideal time T3 are ideal values and can be obtained from design, specifications, and the like. Therefore, since all values of Δtx, CX2, and T3 can be obtained, the path capacity of the calibration relay 16A can be obtained.

  The off-capacitance CX1 may not be zero, and the accuracy of timing calibration is not impaired as long as it is within a predetermined allowable range. Therefore, the processing unit 36 determines whether or not the obtained off-capacitance CX1 is within an allowable range, and detects an off-capacitance abnormality when it is outside the allowable range.

  In the embodiment described above, the off-capacitance abnormality is detected based on the actual measurement time T1 and the reference time T2, but in this modification, the off-capacitance CX1 is directly obtained. What is detected is whether or not the off-capacitance CX1 is abnormal. As described above, it is possible to detect abnormality directly compared to the case where the off-capacitance CX1 is based on the actual measurement time T1 and the reference time T2.

Here, a voltage is applied from the DC measurement unit 13 to obtain an off-capacitance, but a current (current value IF) may be applied. In this case, the following expressions 4 and 5 are established.
“VH = (IF × T3) / CX2” (Formula 4)
“VH = (IF × (T3 + Δtx)) / (CX1 + CX2)” (Formula 5)

  From the above formulas 4 and 5, “CX1 = Δtx × CX2 / T3” (formula 6) is obtained. Equation 6 is the same as Equation 3, and thus an off-capacitance CX1 can be obtained.

  Next, Modification 2 will be described. When it is detected that the off-capacitance of the calibration relay 16 and the test relay 22 affecting the timing calibration signal is abnormal, the countermeasure is taken, but the coping method is changed depending on the value of the off-capacitance CX1.

  When the value of the off-capacitance CX1 is excessively large, the relay is replaced. This makes it possible to perform timing calibration using a relay with a normal off-capacity. On the other hand, when the off-capacity of the relay is abnormal but the value is not so large, the timing calibration device 12 adjusts the time for timing calibration instead of replacing the relay. As a result, accurate timing calibration is possible without the need for relay replacement.

  When adjusting the timing for timing calibration, it is necessary to obtain the adjustment time. Let this adjustment time be Δty. A test circuit to be subjected to timing calibration is a driver circuit 10A. Accordingly, the relay control unit 14 connects the driver circuit 10A and the timing calibration device 12 and performs relay control so as not to connect others.

  A timing calibration signal having a voltage value VD is output from the driver circuit 10 </ b> A to the timing calibration device 12. The timing calibration device 12 is provided with a mechanism substantially equivalent to the DC measurement unit 13, and detects the voltage of the timing calibration signal output from the driver circuit 10A. The voltage of the timing calibration signal detected by the timing calibration device 12 gradually increases from 0 volts. The timing calibration device 12 detects the input of the timing calibration signal when detecting a predetermined voltage (referred to as VT).

  The relay control unit 14 turns off the relays (the calibration relay 16 and the test relay 22) connected to the timing calibration signal path, whereby the timing calibration signal from the driver circuit 10A is input to the timing calibration device 12. Is done. Therefore, the off capacity of these relays affects the timing calibration signal.

  The off-capacity of the relay is connected in parallel to the relay. Therefore, the off-capacity of the relay of the path connected to the path of the timing calibration signal is in a state where the off-capacitances are connected in parallel when the path of the timing calibration signal is used as a reference. Therefore, if the off-capacities of the relays are cy1, cy2,..., The combined capacity CY1 is “CY1 = cy1 + cy2 +.

Further, an ideal path capacity between the driver circuit 10A and the timing calibration device 12 is CY2, and a path resistance is RY. Then, assuming that the time until the timing calibration signal is input from the driver circuit 10A to the timing calibration device 12 when the combined capacitance CY1 is zero is the ideal time T4, the following Expression 7 is established.
“VT = VD × (1-exp (−T4 / (CY2 × RY)))” (formula 7)

On the other hand, the off-capacity of each relay in the off state connected to the path of the timing calibration signal causes a waveform rounding in the timing calibration signal. As a result, an error occurs in the time until the timing calibration device 12 detects the input of the timing calibration signal. This error becomes the adjustment time Δty. At this time, Expression 7 becomes Expression 8 below.
“VT = VD × (1−exp (− (T4 + Δty) / ((CY2 + CY1) × RY)))” (Formula 8)

  From the above formulas 7 and 8, “Δty = CY1 × T4 / CY2” (formula 9) is obtained. T4 is an ideal time when the combined capacitance CY1 of the off capacitance is zero, and can be obtained as a known value. Since CY2 is also an ideal path capacity, it can be obtained as a known value.

On the other hand, CY1 is a combined capacity of the off capacity of each relay. The off-capacities cy1, cy2,... Of each relay are CX1 obtained in the first modification. Therefore, since the off-capacities cy1, cy2,... For each relay can be recognized, the combined capacity CY1 can also be obtained. Therefore, Expression 9 becomes Expression 10 below.
“Δty = (cy1 + cy2 +...) × T4 / CY2” (Formula 10)

  Therefore, the adjustment time Δty can be obtained. The timing calibration device 12 performs timing calibration by giving a predetermined delay time to the operation timing of the test circuit. At this time, by adding the adjustment time Δty to the predetermined delay time, it is possible to perform accurate timing calibration that takes into account the influence of the relay OFF capacity.

  In this modification, when the off-capacitance connected to the path of the timing calibration signal has an abnormality and the relay does not need to be replaced, the adjustment time Δty is obtained to adjust the timing calibration time. ing. This adjustment time Δty can also be applied when the off-capacity is normal.

  That is, the relay has a predetermined off-capacity, but the above-described allowable range is set for the off-capacity. Therefore, even within the permissible range, it is possible to adjust the timing with higher accuracy by adjusting the adjustment time Δty. Further, when the adjustment time Δty can be increased, the timing calibration may be performed based on the adjustment time Δty even if the time difference is large enough to require replacement of the relay.

1 Test part 2 DUT
DESCRIPTION OF SYMBOLS 10 Driver circuit 11 Comparator circuit 12 Timing calibration apparatus 13 DC measurement unit 14 Relay control part 15 Calibration path 16 Calibration system relay 17 Relay tournament 18 Force line 19 Sense line 21 Test path 22 Test relay 31 Output control part 32 Current voltage output part 33 Voltage detection unit 34 Sampling unit 35 Time measurement unit 36 Processing unit 37 Data storage unit

Claims (5)

A semiconductor test apparatus including a test unit provided with a test circuit for testing a device under test,
Of the plurality of relays provided in the test unit, the relay to be inspected is turned off, the voltage or current is output to detect the voltage from the relay, and based on the temporal change of the detected voltage, the relay A semiconductor test apparatus comprising an abnormality detection unit that detects whether or not an off-capacitance is abnormal. The abnormality detection unit
A time measuring unit that measures the time from when the detected voltage reaches the second threshold value, which is higher than the first threshold value, as the actual measurement time;
The time from the first threshold value to the second threshold value when the off-capacity is not abnormal is set as a reference time, and the interval between the actual measurement time measured by the time measurement unit and the reference time. A processing unit for determining whether or not the abnormality occurs based on a time difference;
The semiconductor test apparatus according to claim 1, further comprising: The processing unit is based on the ideal path capacity of the path between the relay to be inspected and the abnormality detection unit, the arrival time when there is no off capacity of the relay to be inspected, and the time difference, The semiconductor test apparatus according to claim 2, wherein an off-capacitance of a relay to be inspected is detected. A timing calibration unit that performs a timing calibration signal exchange with a test circuit to be subjected to timing calibration among the test circuits, and calibrates the operation timing of the test circuit based on the timing of the timing calibration signal exchange. Prepared,
The timing calibration unit is a combined capacity of an off-capacitance of an off-state relay connected to a path between the test circuit and the timing calibration unit, an ideal path capacity of the path, and a combined capacity of zero Detecting a timing calibration error based on the combined capacity based on a time until the timing calibration signal is detected, and adjusting the error when performing timing calibration of the test circuit to perform timing calibration The semiconductor test apparatus according to claim 3. A relay off-capacity abnormality detection method for detecting a relay off-capacity abnormality provided in a test section for testing a device under test,
With the relay to be inspected among the relays turned off, a current or voltage is applied to the relay to detect the voltage from the relay,
A relay off-capacity abnormality detection method comprising: detecting whether or not an abnormality has occurred in the off-capacity of the relay based on a temporal change in the detected voltage.

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