JP2012038896A - Solid state image sensor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor and a manufacturing method of the same capable of reducing warpage of an imaging surface.SOLUTION: The manufacturing method of the solid state image sensor comprises: a polishing process S2 to polish the rear surface of a semiconductor wafer, on the front face of which a plurality of solid state image sensors are formed and on the rear face of which a film is formed, and remove the film; and a dicing process S3 to dice the semiconductor wafer after the polishing process S2 into an individual one of the plurality of the solid state image sensors. The rear face of the semiconductor wafer after the polishing process S2 is a mirror surface and the thickness of the semiconductor wafer after the polishing process S2 is 700 μm or more.

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  A CMOS type, CCD type, and other various solid-state imaging devices are composed of a substrate and an element portion such as a pixel formed on one surface (front surface) side of the substrate. The solid-state imaging device is manufactured by forming a plurality of solid-state imaging devices on the surface side of the semiconductor wafer using a semiconductor manufacturing process or the like and then dicing the semiconductor wafer into individual solid-state imaging devices (chips). It has been broken.

  In recent years, a technique called stealth dicing is known as a dicing technique for cutting a chip from a wafer. In this dicing, a laser beam is irradiated to the inside of the wafer with a focusing point to form a modified region or the like inside the wafer, and cutting is performed using this modified region or the like as a starting point (see below). Patent Document 1).

JP 2002-192370 A

  In the method for manufacturing a solid-state imaging device as described above, a so-called residual film is formed on the back surface of the semiconductor wafer in a state where a plurality of solid-state imaging devices are formed on the front surface side along with the formation of the solid-state imaging device. .

  When manufacturing a solid-state imaging device, when performing a dicing process including a process of irradiating a semiconductor wafer with a converging point, as in the above-described stealth dicing, the laser beam into the semiconductor wafer In order to appropriately collect the light, it is preferable to remove the remaining film on the back surface of the semiconductor wafer and irradiate the laser beam from the back surface of the semiconductor wafer.

  In the case where the residual film is removed by polishing the back surface of the semiconductor wafer, it has been found that depending on the polishing condition, the warp of the imaging surface becomes large in the solid-state imaging device after manufacture.

  If the imaging surface is warped, the entire imaging surface cannot be placed on the focal plane, and even if the focus is matched at the center of the imaging surface, a large defocus occurs at the periphery of the imaging surface, resulting in imaging performance. Will drop significantly. In particular, in the case of a large-sized solid-state imaging device such as a solid-state imaging device mounted on a single-lens reflex digital camera, the imaging performance is significantly deteriorated due to warping of the imaging surface.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a solid-state imaging device capable of reducing warpage of an imaging surface and a method for manufacturing the same.

  The following aspects are presented as means for solving the problems. The manufacturing method of the solid-state imaging device according to the first aspect is a polishing method in which a semiconductor wafer having a plurality of solid-state imaging devices formed on the front surface side and a film formed on the back surface is polished on the back surface to remove the film. And a dicing step of dicing the semiconductor wafer after the polishing step individually into the plurality of solid-state imaging devices, and the back surface of the semiconductor wafer after the polishing step is a mirror surface, and the polishing step The thickness of the subsequent semiconductor wafer is 700 μm or more.

  The solid-state imaging device manufacturing method according to the second aspect is a polishing method in which a semiconductor wafer having a plurality of solid-state imaging devices formed on the front surface side and a film formed on the back surface is polished on the back surface to remove the film. And a dicing step of dicing the semiconductor wafer after the polishing step individually into the plurality of solid-state imaging devices, and the back surface of the semiconductor wafer after the polishing step is a mirror surface, and the polishing step The polishing amount is 1 to 10 times the thickness of the film.

  In the method for manufacturing a solid-state imaging device according to a third aspect, in the first or second aspect, the polishing step includes a first step for performing polishing in which a crushed layer is generated, and polishing for removing the crushed layer. It consists of a 2nd process.

  In the solid-state imaging device manufacturing method according to the fourth aspect, in the third aspect, the second step is a step of performing CMP or dry polishing.

  In the solid-state imaging device manufacturing method according to the fifth aspect, in the first or second aspect, the polishing step comprises only a step of performing CMP or dry polishing.

  According to a sixth aspect of the method for manufacturing a solid-state imaging device, in any one of the first to fifth aspects, the film includes a single layer having at least one of a silicon oxide layer, a silicon nitride layer, and a polysilicon layer. It is a layer film or a laminated film.

  According to a seventh aspect of the method for manufacturing a solid-state imaging device, in any one of the first to sixth aspects, the dicing step emits laser light from the back side of the semiconductor wafer after the polishing step. It includes a step of irradiating with a condensing point inside.

  A solid-state imaging device according to an eighth aspect includes a substrate and an element portion formed on the front surface side of the substrate, the back surface of the substrate is an exposed mirror surface, and the thickness of the substrate is 700 μm or more. It is.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can reduce the curvature of an imaging surface, and its manufacturing method can be provided.

1 is a schematic configuration diagram illustrating a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows one pixel in FIG. It is a schematic sectional drawing which shows typically a part of solid-state image sensor shown in FIG. It is a schematic flowchart which shows the manufacturing method by the 2nd Embodiment of this invention. It is a schematic plan view which shows typically the chip | tip area | region of a silicon wafer. It is a schematic sectional drawing which shows typically the state after the element formation process in FIG. It is a figure which shows the experimental result of the relationship between the finishing roughness of back surface grinding | polishing, and chip curvature. It is a figure which shows the experimental result of the relationship between the wafer thickness after back surface grinding | polishing, and chip curvature amount.

  Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic configuration diagram showing a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state image sensor 1 is configured as a CMOS solid-state image sensor. However, the present invention can also be applied to other solid-state imaging devices such as a CCD type.

  As shown in FIG. 1, the solid-state imaging device 1 includes a vertical scanning circuit 2, a horizontal scanning circuit 3, and a plurality of pixels 4 arranged in a two-dimensional manner, as in a general CMOS solid-state imaging device. , A read circuit 5 and an output amplifier 6. An electric signal output from a photodiode 15 (not shown in FIG. 1; see FIG. 2) of each pixel 4 is taken out by the vertical scanning circuit 2 to the reading circuit 5 in a row unit, and output by the horizontal scanning circuit 3 in a column unit. 6 is output to the output terminal 7 as an image signal.

  FIG. 2 is a circuit diagram showing one pixel 4 in FIG. As shown in FIG. 2, each pixel 4 includes a selection transistor 11, a source follower amplification transistor 12, a reset transistor 13, a transfer transistor 14, and a photodiode 15 as a light receiving unit that performs photoelectric conversion. ing. In FIG. 2, Vcc is a power source.

  As shown in FIGS. 1 and 2, the gate of the selection transistor 11 of the pixel 4 is commonly connected to the selection line 20 for each row. The gate of the reset transistor 13 of the pixel 4 is commonly connected to the reset line 21 for each row. The gate of the transfer transistor 14 of the pixel 4 is commonly connected to the transfer line 22 for each row. The source of the selection transistor 11 of the pixel 4 is commonly connected to the vertical signal line 23 for each column. The selection line 20, the reset line 21 and the transfer line 22 are connected to the vertical scanning circuit 2. The vertical signal line 23 is connected to the readout circuit 5.

  FIG. 3 is a schematic cross-sectional view schematically showing a part of the solid-state imaging device 1 shown in FIG. FIG. 3 schematically shows only a main part of a plurality of pixels 4 arranged in a predetermined direction in a simplified manner.

  In the solid-state imaging device 1, an element portion is formed on the surface side (upper side in FIG. 3) of the silicon substrate 31. In the present embodiment, specifically, as shown in FIG. 3, each pixel 4 is provided with a photodiode 15 on the surface side of the silicon substrate 31. On the silicon substrate 31, interlayer films 32 to 34 made of, for example, a silicon oxide film are sequentially formed from the lower side (the substrate 31 side). Further, as shown in FIG. 3, a first aluminum wiring layer 35, a second aluminum wiring layer 36, and a third aluminum wiring layer 37 are formed, and thereby the wiring of the circuit shown in FIGS. Has been made. The third aluminum wiring layer 37 also serves as a light shielding film that covers the effective light receiving area of each pixel 4. Although not shown in the drawing, the circuit shown in FIG. 2 of each pixel 4 and other circuits in FIG. 1 are also mounted on the silicon substrate 31. For example, a gate electrode made of polysilicon constituting the transistor described above is formed in the interlayer film.

  In the solid-state imaging device 1, as shown in FIG. 3, a passivation film (protective film) 38 such as a silicon nitride film and an insulating film such as a silicon nitride film are provided above the third aluminum wiring layer 37. 39, a flattening layer 40, red, green and blue color filter layers 41R, 41G, and 41B, a flattening layer 42, and a microlens 43 that collects incident light on the photodiode 15 are provided. In FIG. 3, for ease of understanding, red, green, and blue color filter layers 41R, 41G, and 41B are sequentially arranged for each pixel 4 in each column. For example, according to the Bayer array. The micro lens 43 is also formed for each pixel 4.

  And in the solid-state image sensor 1 by this Embodiment, the back surface (lower surface in FIG. 3) 31a of the silicon substrate 31 is an exposed mirror surface. In this specification, the mirror surface means a surface roughness of Ra of 0.005 μm or less and Ry of 0.030 μm or less. In the solid-state imaging device 1 according to the present embodiment, the total thickness D (in this embodiment, the thickness from the upper surface of the microlens 43 to the back surface of the silicon substrate 31) D is 700 μm or more. In order to further reduce the warp of the imaging surface (corresponding to the substrate surface), the thickness D is preferably 710 μm or more, and more preferably 720 μm or more.

  According to the present embodiment, since the back surface 31a of the silicon substrate 31 is an exposed mirror surface and the thickness D is 700 μm or more, the warp of the imaging surface can be reduced as can be seen from the experimental results described later. it can.

[Second Embodiment]
FIG. 4 is a schematic flowchart showing a manufacturing method according to the second embodiment of the present invention. The manufacturing method according to the present embodiment is a manufacturing method of the solid-state imaging device 1 shown in FIGS. 1 to 3 described above.

  First, a silicon wafer 51 as a semiconductor wafer is prepared in order to manufacture a plurality of solid-state imaging devices 1 in a batch. This silicon wafer 51 is finally divided for each chip to become the silicon substrate 31 of each solid-state imaging device 1. As shown in FIG. 5, the silicon wafer 51 has a plurality of chip regions 52 each serving as an individual solid-state imaging device 1. FIG. 5 is a schematic plan view schematically showing the chip region 52 of the silicon wafer 51.

  And element formation process S1 which forms solid-state image sensor 1 in each chip field 52 of this silicon wafer 51 is performed. That is, in the element formation step S1, the structure up to the microlens 43 (including the circuits shown in FIGS. 1 and 2) is formed on the surface side of the silicon wafer 51 using a semiconductor manufacturing process or the like as in the case of the conventional solid-state imaging element. )) Is produced collectively for the plurality of solid-state imaging devices 1. FIG. 6 is a schematic sectional view schematically showing the state after the element forming step S1, and corresponds to FIG.

  As shown in FIG. 6, a film (so-called residual film) 100 is formed on the back surface of the silicon wafer 51 after the element forming step S1. Although not shown in the drawings, in the present embodiment, this film 100 is formed of a silicon oxide layer and a passivation film 38 made of a silicon nitride film formed simultaneously with the formation of the interlayer films 32 to 34 made of a silicon oxide film. It is a laminated film composed of a silicon nitride layer formed simultaneously with film formation, a polysilicon layer formed simultaneously with film formation of a gate electrode (not shown) made of polysilicon, and the like. But the material of the film | membrane 100 formed in the back surface of the silicon wafer 51 after element formation process S1 is not limited to such a material, The film | membrane 100 may be a single layer film. The thickness d of the film 100 is, for example, 2 μm to 3 μm.

  Next, a back surface polishing step S2 is performed on the silicon wafer 51 after the element forming step S1. In the back surface polishing step S2, the back surface of the silicon wafer 51 after the element forming step S1 is polished and the film 100 is removed. In this back surface polishing step S2, the back surface of the silicon wafer 51 after the back surface polishing step S2 becomes a mirror surface, and the thickness of the silicon wafer 51 after the back surface polishing step S2 (same as the thickness D in FIG. 3) is 700 μm or more. Then, the back surface of the silicon wafer 51 after the element forming step S1 is polished.

In the back surface polishing step S2, for example, a first step of performing polishing in which a crushed layer is generated and a second step of removing the crushed layer may be performed. In the first step, specifically, for example, polishing is performed with a fairly coarse count wheel (abrasive material) such as # 2000, followed by polishing with a slightly coarse count wheel (abrasive material) such as # 6000. May be. Alternatively, in the first step, specifically, for example, polishing may be performed only with a slightly coarse wheel (abrasive material) such as # 6000. When grinding with a count wheel such as # 2000 or # 6000, a crushed layer is formed on the polished surface side. In the second step, specifically, for example, CMP (Chemical Mechanical Polishing) or dry polishing can be performed. In the case of CMP, for example, it can be performed under conditions of a slurry abrasive grain size of 70 to 90 nm, a load of 200 to 400 g / cm ² , and a polishing time of 150 to 250 seconds. In the case of dry polishing, for example, polishing can be performed with fixed abrasive grains having a slurry abrasive grain size of 70 to 90 nm, under conditions of a load of 200 to 400 g / cm ² and a polishing time of 150 to 250 seconds.

Alternatively, in the back surface polishing step S2, for example, CMP or dry polishing may be performed from the beginning to the end of the back surface polishing step S2. In the case of CMP, for example, it can be performed under conditions of a slurry abrasive grain size of 5 nm, a load of 200 to 400 g / cm ² , and a polishing time of 150 to 200 seconds. In the case of dry polishing, for example, the polishing can be performed with fixed abrasive grains having a slurry abrasive grain size of 5 nm, under conditions of a load of 200 to 400 g / cm ² and a polishing time of 150 to 250 seconds. If necessary, the CMP or dry polishing conditions may be changed during the process.

  Next, a dicing step S3 is performed in which the silicon wafer 51 after the back surface polishing step S2 is diced into individual solid-state imaging devices 1 (chips). In this dicing step S3, for example, known so-called stealth dicing is performed. That is, a laser beam is irradiated from the back surface side of the silicon wafer 51 after the back surface polishing step S <b> 2 to the inside of the silicon wafer 51 with a focusing point to form a modified region or the like inside the silicon wafer 51, Cutting is performed starting from the modified region. Thereby, the solid-state imaging device 1 shown in FIGS. 1 to 3 is completed.

  According to the present embodiment, it is possible to manufacture the solid-state imaging device 1 according to the first embodiment that can reduce the warpage of the imaging surface.

  The present inventor obtained FIGS. 7 and 8 as experimental results to support this point. In this experiment, six silicon wafers having a thickness of about 750 μm and a diameter of 8 inches were prepared, and these six silicon wafers were subjected to the same process as the element formation process S1 described above, and the process was performed 6 Each of the silicon wafers was used as a sample No. 1 to No. 6.

  And about the sample of No.1-No.6, the back surface grinding | polishing process corresponding to back surface grinding | polishing process S2 mentioned above is given, and also the dicing process S3 mentioned above is further given to a predetermined number of chips (equivalent to a solid-state image sensor). Dicing. About each sample, the chip | tip curvature amount before a back surface grinding | polishing process was measured. At this time, since the dicing process is not performed before the back surface polishing process is performed, the warpage amount (flatness) is measured for each of a predetermined number of chip areas of the silicon wafer after the element formation process. The average value of the amount of warpage was taken as the amount of chip warpage before the back surface polishing step for each sample. The amount of warpage of each chip area was obtained from the height of the measurement points with a plurality of predetermined points in the chip area as measurement points. Moreover, about each sample, the chip | tip curvature amount after a back surface grinding | polishing process was measured. At this time, for each sample, the warpage amount (flatness) is measured for a predetermined number of chips after the dicing process, and the average value of the warpage amounts of these chip regions is calculated as the chip warpage after the back surface polishing process of each sample. The amount. The amount of warpage of each chip was obtained from the height of the measurement point with a plurality of predetermined points (the same point as the measurement point of the chip region) as the measurement point.

  In the samples No. 1 to No. 6, only the back surface polishing step was changed. FIG. 7 shows the amount of chip warpage before and after the back surface polishing step of the samples No. 1 to No. 3. FIG. 8 shows the amount of chip warpage before and after the back surface polishing step of the samples No. 4 to No. 6. Although the unit of the vertical axis (chip warpage amount) in FIGS. 7 and 8 is an arbitrary unit, both units are the same. In the samples No. 1 to No. 6, since the same steps were performed for the steps other than the back surface polishing step, there was almost no variation in the amount of chip warpage of the No. 1 to No. 6 samples before the back surface polishing step. .

  In the No. 1 sample, the final wafer thickness was set to 600 μm by performing polishing only with a # 2000 count wheel in the back surface polishing step. In the No. 2 sample, the final polishing of the final wafer is performed by first polishing with a # 2000 count wheel in the backside polishing step and finally polishing with a # 6000 count wheel. The thickness was 600 μm. In the sample No. 3, in the backside polishing process, after first polishing with a # 2000 count wheel, polishing with a # 6000 count wheel, and finally with a mirror finish by CMP Thus, the final wafer thickness was 600 μm.

  In the No. 4 sample, like the No. 3 sample, in the backside polishing step, after first polishing with a # 2000 count wheel, polishing with a # 6000 count wheel, Finally, a mirror finish is performed by CMP to make the final wafer thickness 600 μm. In the sample No. 5, in the backside polishing step, after first polishing with a # 2000 wheel, polishing with a # 6000 wheel, and finally with a mirror finish by CMP Thus, the final wafer thickness was set to 650 μm. In the sample No. 6, in the backside polishing step, after first polishing with a # 2000 wheel, polishing with a # 6000 wheel, and finally with a mirror finish by CMP Thus, the final wafer thickness was set to 725 μm.

  FIG. 7 shows the experimental results of the relationship between the finishing roughness of the back surface polishing and the amount of chip warpage by describing the measurement results of No. 1 to No. 3. As can be seen from FIG. 7, as the finished surface in the back surface polishing process becomes finer and closer to a mirror surface, the amount of chip warpage becomes smaller. This is because by reducing the thickness of the crushing layer that occurs on the back surface of the wafer, the residual stress that pushes the back surface of the wafer into a convex shape is reduced, and as a result, the factors that cause the wafer surface to warp into a concave shape are reduced. It is considered that the warpage of the surface is reduced. If the finished surface is a mirror surface, the crushed layer is substantially absent.

  FIG. 8 shows the experimental results of the relationship between the wafer thickness after the back surface polishing and the chip warpage amount by describing the measurement results of No. 4 to No. 6. As can be seen from FIG. 8, in the case where the finished surface in the back surface polishing step is a mirror surface, the amount of chip warpage decreases as the final wafer thickness increases. It can be seen that if the final wafer thickness is 700 μm or more, the amount of chip warpage is sufficiently small. As described above, the film 100 is 2 to 3 μm, and the thickness of the wafer before the back surface polishing step of the samples No. 1 to No. 6 (particularly No. 4 to No. 6) is 750 μm. In consideration, since 750 μm− (3 μm × 10) = 720 μm, when the finished surface in the back surface polishing step is a mirror surface, the polishing amount in the back surface polishing step is the film 100 on the back surface of the wafer after the element forming step S1. It can be seen that when the thickness is 10 times or less, the amount of warping of the chip is sufficiently small.

  These points are applicable not only to wafers having a diameter of 8 inches but also to wafers of other sizes such as 12 inches in diameter.

  For the above reasons, according to the first and second embodiments, since the back surface 31a of the silicon substrate 31 is a mirror surface exposed and the thickness D is 700 μm or more, the warp of the imaging surface is reduced. It can be done.

  From the above description, in order to sufficiently reduce the amount of chip warpage, in the back surface polishing step S2 for removing the film 100, the back surface of the silicon wafer 51 after the back surface polishing step S2 is used as a mirror surface, and the back surface polishing step S2. It can be seen that the amount of polishing may be 1 to 10 times the thickness of the film 100.

  Further, it can be seen from the above description that it is preferable that the finished surface in the back surface polishing step S2 is a mirror surface and the final wafer is thick. Therefore, compared with the case where polishing is first performed with a # 2000 wheel in the back surface polishing step S2 and CMP or dry polishing is performed last, CMP or dry polishing is performed from the beginning to the end in the back surface polishing step S2. However, it is preferable because the final wafer thickness can be easily increased.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 31 Substrate 31a Back surface 51 Silicon wafer 100 Film

Claims (8)

A polishing step of polishing the back surface of a semiconductor wafer in which a plurality of solid-state imaging elements are formed on the front surface side and a film is formed on the back surface, and removing the film;
A dicing step of dicing the semiconductor wafer after the polishing step into the plurality of solid-state imaging devices individually;
With
A method of manufacturing a solid-state imaging device, wherein the back surface of the semiconductor wafer after the polishing step is a mirror surface, and the thickness of the semiconductor wafer after the polishing step is 700 μm or more. A polishing step of polishing the back surface of a semiconductor wafer in which a plurality of solid-state imaging elements are formed on the front surface side and a film is formed on the back surface, and removing the film;
A dicing step of dicing the semiconductor wafer after the polishing step into the plurality of solid-state imaging devices individually;
With
The solid-state imaging device, wherein the back surface of the semiconductor wafer after the polishing step is a mirror surface, and the polishing amount in the polishing step is 1 to 10 times the thickness of the film Method.   3. The solid-state imaging device according to claim 1, wherein the polishing step includes a first step of performing polishing for generating a crushed layer and a second step of performing polishing for removing the crushed layer. Production method.   4. The method of manufacturing a solid-state imaging device according to claim 3, wherein the second step is a step of performing CMP or dry polishing.   3. The method of manufacturing a solid-state imaging device according to claim 1, wherein the polishing step includes only a step of performing CMP or dry polishing.   6. The solid-state imaging device according to claim 1, wherein the film is a single layer film or a laminated film having at least one of a silicon oxide layer, a silicon nitride layer, and a polysilicon layer. Manufacturing method.   7. The dicing step includes a step of irradiating a laser beam from the back side of the semiconductor wafer after the polishing step to the inside of the semiconductor wafer with a focusing point aligned. The manufacturing method of the solid-state image sensor as described in 1 .. Comprising a substrate and an element portion formed on the surface side of the substrate;
The back surface of the substrate is an exposed mirror surface;
A solid-state imaging device, wherein the thickness of the substrate is 700 μm or more.

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