JP2017126678A - Solid-state image pickup device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of suppressing occurrence of flare and ghost, and a method for manufacturing the same.SOLUTION: According to one embodiment, a solid-state image pickup device is provided. The solid-state image pickup according to an embodiment includes a photoelectric conversion element and a wiring layer. The photoelectric conversion element is provided in a semiconductor layer and receives light incident from one surface side of the semiconductor layer. The wiring layer has a first wiring pattern in which a plurality of linear wirings are arranged in parallel in a planar direction of the semiconductor layer with a predetermined space therebetween at a position facing the photoelectric conversion element on the other surface side of the semiconductor layer.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  2. Description of the Related Art Conventionally, there is a back-illuminated solid-state imaging device that includes a semiconductor layer provided with a plurality of photoelectric conversion elements that photoelectrically convert incident light and a wiring layer provided on the side opposite to the light-receiving surface side of the semiconductor layer. .

  In such a solid-state imaging device, light incident on the photoelectric conversion element may pass through the photoelectric conversion element and reach the wiring layer. In such a solid-state imaging device, flare and ghost are generated when the light reflected by the wiring becomes stray light and enters the photoelectric conversion element again.

JP 2010-212635 A

  An object of one embodiment is to provide a solid-state imaging device and a method for manufacturing the solid-state imaging device that can suppress the occurrence of flare and ghost.

  According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device according to the embodiment includes a photoelectric conversion element and a wiring layer. The photoelectric conversion element is provided in the semiconductor layer and receives light incident from one surface side of the semiconductor layer. The wiring layer has a first wiring pattern in which a plurality of linear wirings are arranged in parallel at a predetermined interval in the surface direction of the semiconductor layer at a position facing the photoelectric conversion element on the other surface side of the semiconductor layer. Have.

FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera including the solid-state imaging device according to the first embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. FIG. 3 is an explanatory diagram illustrating a schematic cross section of the pixel array according to the first embodiment. FIG. 4 is an explanatory diagram illustrating a wiring arrangement relationship in a wiring layer included in the solid-state imaging device according to the first embodiment. FIG. 5 is an explanatory diagram illustrating a wiring pattern arrangement relationship in a wiring layer included in the comparative solid-state imaging device according to the first embodiment. FIG. 6 is a graph showing the reflectance in the wavelength region from 500 nm to 800 nm of the wiring layer included in the solid-state imaging device according to the first embodiment. FIG. 7 is a diagram illustrating the transmittance in the wavelength region from 500 nm to 800 nm of the wiring layer included in the solid-state imaging device according to the first embodiment. FIG. 8 is an explanatory diagram showing a cross-sectional view of the manufacturing process of the solid-state imaging device according to the first embodiment. FIG. 9 is an explanatory diagram of the manufacturing process of the solid-state imaging device according to the first embodiment in a cross-sectional view. FIG. 10 is a cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment. FIG. 11 is an explanatory diagram in a cross-sectional view of the manufacturing process of the solid-state imaging device according to the first embodiment. FIG. 12 is an explanatory diagram illustrating a schematic cross section of a pixel array according to the second embodiment. FIG. 13 is an explanatory diagram illustrating a wiring arrangement relationship in a wiring layer included in the pixel array according to the second embodiment. FIG. 14 is a diagram illustrating the transmittance in the wavelength region from 500 nm to 800 nm of the wiring layer included in the solid-state imaging device according to the second embodiment. FIG. 15 is an explanatory diagram illustrating a schematic cross section of a pixel array according to the second embodiment. FIG. 16 is an explanatory diagram illustrating a wiring arrangement relationship in a wiring layer included in the solid-state imaging device according to the third embodiment. FIG. 17 is an explanatory diagram of a manufacturing process of the solid-state imaging device according to the third embodiment in a cross-sectional view. FIG. 18 is an explanatory diagram of a manufacturing process of the solid-state imaging device according to the third embodiment in a cross-sectional view. FIG. 19 is an explanatory diagram illustrating a schematic configuration of an optical system provided in a camera module to which the solid-state imaging device according to the first, second, and third embodiments is applied.

  Exemplary embodiments of a solid-state imaging device and a method for manufacturing the solid-state imaging device will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera 1 including the solid-state imaging device 14 according to the first embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures a subject image formed by the imaging optical system 13 and outputs an image signal obtained by the imaging to the post-processing unit 12. In addition to the digital camera 1, the camera module 11 is applied to an electronic device such as a mobile terminal with a camera.

  The post-processing unit 12 includes an ISP (Image Signal Processor) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of the image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, and resolution conversion processing.

  Then, the ISP 15 outputs the image signal after the signal processing to the signal processing circuit 21 (see FIG. 2) described later provided in the storage unit 16, the display unit 17, and the solid-state imaging device 14 in the camera module 11. An image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores the image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs an image signal of the stored image to the display unit 17 according to a user operation or the like. The display unit 17 displays an image according to an image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, the solid-state imaging device 14 included in the camera module 11 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device 14 according to the embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, the image sensor 20 is a so-called backside-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on the surface opposite to the surface on which incident light enters in a photoelectric conversion element that photoelectrically converts incident light. The case where it is is demonstrated. Note that the image sensor 20 according to the first embodiment is not limited to the back-illuminated CMOS image sensor, and may be any image sensor such as a CCD (Charge Coupled Device) image sensor.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog / digital conversion unit) 27, and a line memory 28, and these are mainly configured by analog circuits. Is done.

  The pixel array 23 is provided in the imaging region of the image sensor 20. In the pixel array 23, a plurality of photoelectric conversion elements corresponding to each pixel of the captured image are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction). In the pixel array 23, each photoelectric conversion element corresponding to each pixel generates and accumulates signal charges (for example, electrons) corresponding to the amount of incident light.

  The timing control unit 25 is a processing unit that outputs a pulse signal serving as a reference for operation timing to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The vertical shift register 24 outputs to the pixel array 23 a selection signal for sequentially selecting photoelectric conversion elements for reading out signal charges from a plurality of photoelectric conversion elements two-dimensionally arranged in an array (matrix). It is a processing unit.

  The pixel array 23 outputs the signal charge accumulated in each photoelectric conversion element selected in units of rows by the selection signal input from the vertical shift register 24 from the photoelectric conversion element to the CDS 26 as a pixel signal indicating the luminance of each pixel. To do. The configuration of the pixel array 23 will be described later with reference to FIG.

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds the pixel signal input from the ADC 27 and outputs the pixel signal to the signal processing circuit 21 for each row of photoelectric conversion elements in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on the pixel signal input from the line memory 28 and outputs the processed signal to the subsequent processing unit 12, and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

  As described above, in the image sensor 20, a plurality of photoelectric conversion elements arranged in the pixel array 23 photoelectrically convert incident light into signal charges of an amount corresponding to the amount of received light, and the peripheral circuit 22 stores each photoelectric conversion element. Imaging is performed by reading out the signal charge accumulated in the pixel signal as a pixel signal.

  Next, the pixel array 23 will be described with reference to FIGS. 3 and 4. FIG. 3 is an explanatory diagram illustrating a schematic cross section of the pixel array 23 included in the solid-state imaging device 14 according to the first embodiment. FIG. 4 is an explanatory diagram illustrating the layout relationship of the wiring patterns in the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment. FIG. 4 shows an arrangement relationship of wiring patterns arranged for each pixel.

  FIG. 3 shows components necessary for the description of the pixel array 23 according to the first embodiment. The detailed structure of the pixel array 23 includes solid-state imaging including a method for forming the pixel array 23 described later. The manufacturing method of the device 14 will be described. Further, here, for the sake of convenience, the side on which the light 9 of the pixel array 23 is incident will be described as the upper side, and the side opposite to the side on which the light 9 of the pixel array 23 will be incident will be described.

  As shown in FIG. 3, the pixel array 23 includes a first conductivity type (P type) semiconductor (here, Si: silicon) layer 30. A second conductivity type (N-type) Si region 31 is provided at a position where the photoelectric conversion element 4 is formed inside the P-type Si layer 30. In the pixel array 23, a photodiode formed by a PN junction between the P-type Si layer 30 and the N-type Si region 31 is the photoelectric conversion element 4. The photoelectric conversion elements 4 are two-dimensionally arranged in an array (matrix) in the P-type Si layer 30.

  The pixel array 23 includes an antireflection film 6, a color filter 7, and a microlens 8 stacked on the light receiving surface side of the P-type Si layer 30. The color filter 7 is a filter that selectively transmits red, green, blue, or white color light, and covers each upper end surface corresponding to the upper end surface that is the light receiving surface of each photoelectric conversion element 4. Provided to hide. The microlens 8 is a lens having a convex shape from above, and is similarly provided so as to cover each upper end surface corresponding to the upper end surface of each photoelectric conversion element 4.

  The pixel array 23 includes the wiring layer 5 on the surface side opposite to the light receiving surface side of the P-type Si layer 30. The wiring layer 5 is formed on an unillustrated semiconductor substrate, for example, an interlayer insulating film 50 containing silicon oxide or the like, and wiring patterns 51, 52, 53 formed on the surface of the interlayer insulating film 50, Is a structure laminated in multiple layers in this order. The wiring patterns 51, 52, and 53 are stacked in this order on the surface of the P-type Si layer 30 opposite to the light receiving surface.

  Specifically, as shown in FIG. 4, the wiring layer 5 is provided with three layers of wiring patterns 51, 52, and 53 in this example via an interlayer insulating film 50. Such three-layer wiring patterns 51, 52, and 53 overlap each other when viewed from the light receiving surface of the photoelectric conversion element 4, and are provided at positions facing the microlenses 8.

  In the first wiring pattern 51 of the first layer, a plurality of linear wirings are arranged in parallel at a predetermined interval in the surface direction of the P-type Si layer 30 at a position facing the photoelectric conversion element 4. Specifically, the first wiring pattern 51 of the first layer has L1 / S1 (line and space) of, for example, 0.11 μm / 0.15 μm or less. Here, the term “line and space” means that patterns (lines) having a width of 0.11 μm are arranged in a stripe pattern with an interval (space) of 0.15 μm.

  In the second wiring pattern 52 in the second layer and the third wiring pattern 53 in the third layer, one flat wiring is arranged at a position facing the photoelectric conversion element. That is, in the present embodiment, the first wiring pattern 51 of the first layer formed in a stripe shape is arranged on the surface opposite to the light receiving surface side of the photoelectric conversion element 4, and the first wiring of the first layer is arranged. A second wiring pattern 52 of the second layer formed in a flat plate shape is arranged on the surface side opposite to the light receiving surface side of the pattern 51. Then, the third wiring pattern 53 of the third layer formed in a flat plate shape is disposed on the side opposite to the light receiving surface side of the second wiring pattern 52 of the second layer.

  The material used for the wiring patterns 51, 52, 53 is preferably a material having a low reflectance with respect to the light 9. Specifically, the materials of the wiring patterns 51, 52, 53 are tantalum (Ta), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), and the like. One of the materials may be used, or two or more may be used in combination.

  In the solid-state imaging device 14, the wiring patterns 51, 52, and 53 in the wiring layer 5 are respectively connected to the terminals of the transistors included in each pixel, and the signal charges generated in the photoelectric conversion element 4 are transferred to the wiring layer 5. Read through.

  Here, the wiring layer 5a included in the solid-state imaging device used for comparison with the solid-state imaging device 14 according to the embodiment will be described with reference to FIG. FIG. 5 is an explanatory diagram illustrating the arrangement relationship of the wiring patterns in the wiring layer 5a included in the comparative solid-state imaging device according to the embodiment. Of the constituent elements shown in FIG. 5, the same constituent elements as those shown in FIG. 4 are given the same reference numerals as those shown in FIG. 4, and detailed descriptions thereof are omitted.

  As shown in FIG. 5, in the wiring layer 5a included in the comparative solid-state imaging device, the first wiring pattern 51a of the first layer is formed in a flat plate shape. That is, the wiring layer 5 a is provided with wiring patterns 51 a, 52, and 53 formed in a three-layered plate shape through the interlayer insulating film 50.

  For this reason, in such a solid-state imaging device, when light incident on the photoelectric conversion element passes through the photoelectric conversion element and reaches the wiring layer 5a, even if the wiring uses a material having a low reflectivity for light, There is a case where it hits the first wiring pattern 51a of the first layer formed in a flat plate shape and is reflected. That is, when the amount of reflected light is large, there is a high possibility that flare and ghost are generated by the reflected light becoming stray light and entering the photoelectric conversion element again.

  Therefore, in the solid-state imaging device 14 according to the first embodiment, the first wiring pattern 51 of the first layer in the wiring layer 5 is formed in a stripe shape as described above. Thereby, in the solid-state imaging device 14, when the light 9 incident on the photoelectric conversion element 4 passes through the photoelectric conversion element 4 and reaches the wiring layer 5, a part of the reached light 9 is the first wiring pattern. The amount of light 9 that is transmitted and reflected through the interlayer insulating film 50 formed between the layers 51 is reduced.

  In the solid-state imaging device 14 according to the first embodiment described above, the linear wiring is P-type at a position facing the photoelectric conversion element 4 on the surface opposite to the light-receiving surface side of the P-type Si layer 30. A wiring layer 5 having a plurality of first wiring patterns 51 arranged in parallel with a predetermined interval in the plane direction of the Si layer 30 is provided.

  Thereby, in the solid-state imaging device 14 according to the first embodiment, a part of the light 9 that has passed through the photoelectric conversion element 4 and reached the wiring layer 5 is formed between the first wiring patterns 51. Permeates through the membrane 50.

  Therefore, the solid-state imaging device 14 according to the first embodiment can suppress the occurrence of flare and ghost because the amount of light 9 reflected to the wiring layer 5 is reduced.

  Here, the test results of evaluating the reflectance and transmittance of the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment will be described. FIG. 6 is a graph showing the reflectance in the wavelength region from 500 nm to 800 nm of the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment. FIG. 7 is a diagram illustrating the transmittance in the wavelength region from 500 nm to 800 nm of the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment.

  In FIG. 6, the vertical axis indicates the reflectance [%] of the light 9 with respect to the wiring layers 5 and 5a, and the horizontal axis indicates the wavelength [nm] of the light 9. In the graph of FIG. 6, the thin line is the test result in the wiring layer 5a, the dotted line is the test result focusing on the S-polarized light in the wiring layer 5, the alternate long and short dash line is the test result focusing on the P-polarized light in the wiring layer 5, and the thick line is the wiring layer. 5 shows the results when the S-polarized light and the P-polarized light at 5 are averaged.

  In FIG. 7, the vertical axis indicates the transmittance [%] of the light 9 with respect to the wiring layers 5 and 5 a, and the horizontal axis indicates the wavelength [nm] of the light 9. In the graph of FIG. 7, the thin line is the test result in the wiring layer 5a, the dotted line is the test result focusing on the S-polarized light in the wiring layer 5, the alternate long and short dash line is the test result focusing on the P-polarized light in the wiring layer 5, and the thick line is the wiring layer. 5 shows the results when the S-polarized light and the P-polarized light at 5 are averaged.

  In the wiring layer 5 used in the experiment, L1 / S1 (see FIG. 4) of the first wiring pattern 51 of the first layer is 0.11 μm / 0.15 μm, and the interlayer insulating film 50 has a refractive index n = 1.45 silicon oxide. Each of the wiring patterns 51, 52, and 53 has a two-layer structure. The light receiving surface layer is made of tantalum having a thickness of 10 nm, and the layer opposite to the light receiving surface is made of copper having a thickness of 130 nm. Consists of. The wiring layer 5a provided in the comparative solid-state imaging device used in the experiment has the same configuration as the wiring layer 5 except that the first wiring pattern 51a of the first layer is formed in a flat plate shape.

  As shown in FIG. 6, the reflectance at a wavelength of 650 nm was about 70% in the wiring layer 5 a included in the comparative solid-state imaging device. On the other hand, in the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment, the reflectance at a wavelength of 650 nm is about 55% for S-polarized light, and the reflectance at a wavelength of 650 nm is about 15% for P-polarized light. The reflectance at a wavelength of 650 nm obtained by averaging the polarized light and the P-polarized light was about 35%.

  Thereby, it is confirmed in the optical simulation that the reflectance of the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment is reduced by half compared to the wiring layer 5a included in the comparative solid-state imaging device. did.

  Further, as shown in FIG. 7, in the wiring layer 5a included in the comparative solid-state imaging device, the transmittance at a wavelength of 650 nm was a value close to 0%. On the other hand, in the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment, the transmittance at a wavelength of 650 nm is about 15% with P-polarized light having a low reflectance.

  From this, by forming the first wiring pattern 51 of the first layer in a stripe shape, P-polarized light that is a part of the light 9 incident on the wiring layer 5 is formed between the first wiring patterns 51. This is considered to be because it passes through the interlayer insulating film 50.

  Therefore, in the solid-state imaging device 14 including the wiring layer 5, the light 9 that is incident on the wiring layer 5 passes through the interlayer insulating film 50 formed between the first wiring patterns 51 to reflect light. The amount of 9 is reduced, and the occurrence of flare and ghost can be suppressed.

  Next, a method for manufacturing the solid-state imaging device 14 including the method for forming the pixel array 23 described above will be described with reference to FIGS. Note that the manufacturing method of the portion other than the pixel array 23 in the solid-state imaging device 14 is the same as that of a general CMOS image sensor. Therefore, in the following, a method for manufacturing the pixel array 23 portion in the solid-state imaging device 14 will be described.

  8-11 is explanatory drawing by the cross sectional view of the manufacturing process of the solid-state imaging device 14 which concerns on 1st Embodiment. 8 to 11 selectively show the manufacturing process of the pixel array 23 and also show the components omitted in FIG.

  As shown in FIG. 8A, in the case of manufacturing the pixel array 23, a Si layer doped with a P-type impurity such as boron is epitaxially grown on a semiconductor substrate 32 such as a Si wafer. The Si layer 30 is formed. The P-type Si layer 30 may be formed by ion-implanting P-type impurities into the Si wafer and performing an annealing process.

  Subsequently, an N-type impurity such as phosphorus is ion-implanted into the formation position of the photoelectric conversion element 4 in the P-type Si layer 30 to perform an annealing process, so that the N-type impurity is added to the P-type Si layer 30. Si regions 31 are two-dimensionally arranged in a matrix.

  Thus, the photoelectric conversion element 4 that is a photodiode is formed in the pixel array 23 by a PN junction between the P-type Si layer 30 and the N-type Si region 31. The pitch width between the photoelectric conversion element 4 (N-type Si region 31) and the photoelectric conversion element 4 (N-type Si region 31) is the same.

  Then, as shown in FIG. 8B, on the upper surface of the P-type Si layer 30, for example, CVD (Chemical Vapor Deposition) is used to form a first interlayer insulating film containing silicon oxide or the like having a predetermined thickness. The film 50 is formed uniformly. Thereafter, for example, RIE (Reactive Ion Etching) is performed using the resist 90 covering the region other than the region where the first wiring pattern 51 is formed as a mask to face the photoelectric conversion element 4 in the first interlayer insulating film 50. A plurality of stripe-shaped trenches 54 are formed at the positions to be formed.

  Next, as illustrated in FIG. 8C, the linear wiring is formed in a position facing the photoelectric conversion element 4 by embedding copper or the like in the trench 54 using, for example, CVD. A plurality of first wiring patterns 51 arranged in parallel with a predetermined interval in the surface direction of the Si layer 30 are formed. Then, the resist 90 used as a mask is removed to make the upper surface of the first wiring pattern 51 flush with the upper surface of the first interlayer insulating film 50.

  Subsequently, as shown in FIG. 9A, the upper surfaces of the first wiring pattern 51 and the first interlayer insulating film 50 include, for example, CVD using silicon oxide having a predetermined thickness. A second interlayer insulating film 50 is formed uniformly. Thereafter, with the resist 91 covering the region other than the region where the second wiring pattern 52 is formed as a mask, for example, by performing RIE, the position of the second interlayer insulating film 50 facing the photoelectric conversion element 4 is set to 1 A trench 55 for forming two flat wirings is formed.

  Next, as shown in FIG. 9B, one flat wiring is formed at a position facing the photoelectric conversion element 4 by embedding copper or the like in the trench 55 using, for example, CVD. The arranged second wiring pattern 52 is formed. Then, the resist 91 used as a mask is removed, and the upper surface of the second wiring pattern 52 and the upper surface of the second interlayer insulating film 50 are flush with each other.

  Then, as shown in FIG. 10A, the same process as the process of forming the second wiring pattern 52 is performed on the upper surfaces of the second wiring pattern 52 and the second-layer interlayer insulating film 50 to form the third wiring pattern 52. By forming the wiring pattern 53, the multilayer wiring layer 5 is formed. In the process of forming the wiring layer 5, a read gate and the like are also formed.

  Subsequently, as shown in FIG. 10B, for example, an adhesive is applied to the upper surface of the wiring layer 5 to provide an adhesive layer 60, and a support substrate 61 such as a Si wafer is pasted on the upper surface of the adhesive layer 60. To wear. Then, after turning the top and bottom of the structure shown in FIG. 10B, the semiconductor substrate 32 is polished from the back surface side (here, the upper surface side) by a polishing apparatus such as a grinder, for example, Thin until it is thick.

  Next, the back surface side of the semiconductor substrate 32 is further polished by, for example, CMP (Chemical Mechanical Polishing), and as shown in FIG. 11A, the back surface (here, the top surface) that becomes the light receiving surface of the P-type Si layer 30 ) Is exposed.

  Then, as shown in FIG. 11B, after the antireflection film 6 is formed on the upper surface of the P-type Si layer 30, red is formed at a position corresponding to the light receiving surface of the photoelectric conversion element 4 on the upper surface of the antireflection film 6. A color filter 7 that selectively transmits one of green, blue, and white color light is formed. Thereafter, the pixel array 23 is manufactured by forming the microlenses 8 that collect the light incident on the upper surface of each color filter 7.

  In the manufacturing method of the pixel array 23 described above, the first wiring pattern 51 of the first layer in the wiring layer 5 is formed in a stripe shape, the second wiring pattern 52 of the second layer, and the third wiring of the third layer. The pattern 53 is formed in a flat plate shape.

  Accordingly, in the pixel array 23, when the light 9 incident on the photoelectric conversion element 4 passes through the photoelectric conversion element 4 and reaches the wiring layer 5, a part of the reached light 9 is the first wiring pattern 51. The light passes through the interlayer insulating film 50 formed therebetween.

  Therefore, the solid-state imaging device 14 according to the first embodiment can suppress the occurrence of flare and ghost because the amount of light 9 reflected to the wiring layer 5 is reduced.

(Second Embodiment)
Next, a pixel array according to the second embodiment will be described. In such a pixel array, a plurality of linear wirings are arranged in parallel at predetermined intervals in a direction intersecting the first wiring pattern on the surface opposite to the light receiving surface side of the first wiring pattern. Two wiring patterns are provided.

  FIG. 12 is an explanatory diagram illustrating a schematic cross section of a pixel array 23b according to the second embodiment. FIG. 13 is an explanatory diagram illustrating a wiring arrangement relationship in the wiring layer 5b included in the pixel array 23b according to the second embodiment. Of the components shown in FIGS. 12 and 13, components having the same functions as those shown in FIGS. 3 and 4 are given the same reference numerals as those shown in FIGS. 3 and 4. The description is omitted.

  As shown in FIG. 12, the pixel array 23 b includes a wiring layer 5 b on the surface side opposite to the light receiving surface side of the P-type Si layer 30. The wiring layer 5b includes an interlayer insulating film 50 including, for example, silicon oxide formed on a semiconductor substrate (not shown), and wiring patterns 51, 52b, and 53 formed on the surface of the interlayer insulating film 50. Is a structure laminated in multiple layers in this order. The wiring patterns 51, 52b, and 53 are laminated in this order on the surface of the P-type Si layer 30 opposite to the light receiving surface.

  Specifically, as shown in FIG. 13, three layers of wiring patterns 51, 52b, and 53 are provided in the wiring layer 5b via the interlayer insulating film 50 in this example. Such three-layer wiring patterns 51, 52 b, 53 are provided at positions where the wiring patterns 51, 52 b, 53 overlap each other when viewed from the light receiving surface of the photoelectric conversion element 4 and face the microlens 8.

  In the first wiring pattern 51 of the first layer, a plurality of linear wirings are arranged in parallel at a predetermined interval in the surface direction of the P-type Si layer 30 at a position facing the photoelectric conversion element 4. In addition, the second wiring pattern 52b of the second layer has a predetermined wiring line in a direction orthogonal to the first wiring pattern 51 on the side opposite to the light receiving surface side of the first wiring pattern 51. A plurality are arranged in parallel at intervals. Specifically, in the second wiring pattern 52b of the second layer, L2 / S2 (line and space) is, for example, 0.11 μm / 0.15 μm or less.

  In the third wiring pattern 53 of the third layer, one flat wiring is arranged at a position facing the photoelectric conversion element 4. That is, in the present embodiment, the first wiring pattern 51 of the first layer formed in a stripe shape is arranged on the surface opposite to the light receiving surface side of the photoelectric conversion element 4, and the first wiring of the first layer is arranged. A second wiring pattern 52b of a second layer formed in a stripe shape in a direction orthogonal to the first wiring pattern 51 of the first layer is disposed on the surface opposite to the light receiving surface side of the pattern 51. Then, the third wiring pattern 53 of the third layer formed in a flat plate shape is arranged on the surface opposite to the light receiving surface side of the second wiring pattern 52b of the second layer.

  The solid-state imaging device 14 according to the above-described second embodiment has a predetermined arrangement in a direction in which the linear wiring is orthogonal to the first wiring pattern on the surface opposite to the light receiving surface of the first wiring pattern 51. A wiring layer having a plurality of second wiring patterns 52b arranged in parallel at intervals is provided.

  Thereby, in the solid-state imaging device 14 according to the second embodiment, an interlayer insulating film in which a part of the light that has passed through the photoelectric conversion element 4 and reached the wiring layer 5 b is formed between the first wiring patterns 51. 50 passes through the interlayer insulating film 50 formed between the second wiring pattern 53b and the second wiring pattern 53b.

  Therefore, the solid-state imaging device 14 according to the second embodiment can further suppress the occurrence of flare and ghost because the amount of light 9 reflected on the wiring layer 5b is further reduced.

  Here, the test results of evaluating the transmittance of the wiring layer 5b included in the solid-state imaging device 14 according to the second embodiment will be described. FIG. 14 is a diagram illustrating the transmittance in the wavelength region from 500 nm to 800 nm of the wiring layer 5b included in the solid-state imaging device 14 according to the second embodiment.

  In FIG. 14, the vertical axis indicates the transmittance [%] of the light 9 with respect to the wiring layer 5b, and the horizontal axis indicates the wavelength [nm] of the light 9. In the graph of FIG. 14, the alternate long and short dash line indicates the test result focusing on the P-polarized light in the wiring layer 5 b, and the thick line indicates the result when the S-polarized light and P-polarized light in the wiring layer 5 b are averaged.

  The wiring layer 5b used in the experiment is the same as that used in the above-described experiment except that L2 / S2 (see FIG. 13) of the second wiring pattern 52b of the second layer is 0.11 μm / 0.15 μm. It has the same configuration as layer 5.

  As shown in FIG. 14, in the wiring layer 5b included in the solid-state imaging device 14 according to the second embodiment, the transmittance of P-polarized light in the wavelength region of 500 nm to 800 nm was a value close to 0%. Specifically, in the wiring layer 5b, the transmittance of P-polarized light at a wavelength of 650 nm was a value close to 0%. On the other hand, in the wiring layer 5 included in the solid-state imaging device 14 according to the first embodiment described above, the transmittance of P-polarized light at a wavelength of 650 nm was about 15% (see FIG. 7).

  Accordingly, the second-layer second wiring pattern 52b is formed in a stripe shape and arranged in a direction intersecting the first-layer first wiring pattern 51, thereby transmitting P-polarized light to the wiring layer 5b. It can be seen that the rate can be reduced.

  This is presumably because the P-polarized light transmitted through the interlayer insulating film 50 formed between the first wiring patterns 51 hits the second wiring pattern 52b and is reflected.

  Therefore, the solid-state imaging device 14 including the wiring layer 5b can realize both a reduction in the amount of light 9 reflected to the wiring layer 5b and a reduction in the transmittance of P-polarized light to the wiring layer 5b. .

  Note that the pixel array 23b is the same as the manufacturing method of the solid-state imaging device 14 including the method of forming the pixel array 23 described above, except that the second wiring pattern 52b of the second layer is formed in a stripe shape. Manufactured.

  Specifically, in the step of forming the second wiring pattern 52b, first, an upper surface of the first wiring pattern 51 and the first interlayer insulating film 50 is oxidized with a predetermined thickness using, for example, CVD. A second interlayer insulating film 50 containing silicon or the like is uniformly formed. Subsequently, by using, for example, RIE as a mask that covers a region other than the region where the second wiring pattern 52b is formed, the second interlayer insulating film 50 is positioned at a position facing the photoelectric conversion element 4. A plurality of stripe-shaped trenches are formed in a direction orthogonal to one wiring pattern 51.

  Then, by embedding copper or the like in the trench using, for example, CVD, the linear wiring is arranged at a predetermined interval in a direction orthogonal to the first wiring pattern 51 at a position facing the photoelectric conversion element 4. A plurality of second wiring patterns 52b arranged in parallel with a gap are formed.

(Third embodiment)
Next, a pixel array according to the third embodiment will be described. In the first wiring pattern in the peripheral portion of the semiconductor layer of the pixel array, the light receiving surface has a downward slope from the peripheral portion of the semiconductor layer toward the central portion.

  FIG. 15 is an explanatory diagram illustrating a schematic cross section of a pixel array 23c according to the third embodiment. FIG. 16 is an explanatory diagram illustrating a wiring arrangement relationship in the wiring layer 5c included in the pixel array 23c according to the third embodiment. Of the components shown in FIGS. 15 and 16, components having the same functions as those shown in FIGS. 3 and 4 are given the same reference numerals as those shown in FIGS. The description is omitted. In FIG. 15, the pixel array 23 c is divided into a central portion M and a peripheral portion R in order to facilitate understanding of the description of the present embodiment.

  As shown in FIG. 15, in the pixel array 23c, the light receiving surface of the first wiring pattern 51c of the first layer formed in a stripe shape at the peripheral edge R of the pixel array 23c is centered from the peripheral edge R of the pixel array 23c. A wiring layer 5c having a downward slope toward the part M is provided.

  Specifically, as shown in FIG. 16, the first wiring pattern 51 c of the first layer in the peripheral portion R of the pixel array 23 c has a P-type linear wiring at a position facing the photoelectric conversion element 4. The Si layer 30 is arranged in parallel with a predetermined interval in the plane direction (L1 / S1 is, for example, 0.11 μm / 0.15 μm or less). In the first wiring pattern 51c of the first layer in the peripheral portion R of the pixel array 23c, the light receiving surface is inclined downward from the peripheral portion R of the pixel array 23c toward the central portion M.

  In the second wiring pattern 52 in the second layer and the third wiring pattern 53 in the third layer, one flat wiring is arranged at a position facing the photoelectric conversion element. That is, in the present embodiment, the peripheral portion R of the pixel array 23c is formed in a stripe shape on the surface opposite to the light receiving surface side of the photoelectric conversion element 4, and the light receiving surface extends from the peripheral portion R of the pixel array 23c. A first wiring pattern 51c in the first layer that is inclined downward toward the central portion M is disposed.

  A second wiring pattern 52 of the second layer formed in a flat plate shape is disposed on the surface opposite to the light receiving surface of the wiring pattern 51c of the first layer, and the second wiring pattern 52 of the second layer is arranged. A third wiring pattern 53 of the third layer formed in a flat plate shape is disposed on the surface side opposite to the light receiving surface side.

  In the solid-state imaging device 14 according to the third embodiment described above, the light receiving surface of the first wiring pattern 51c in the first layer formed in a stripe shape in the peripheral portion R of the pixel array 23c is the peripheral portion of the pixel array 23c. A wiring layer 5c having a downward slope from R toward the center M is provided.

  Accordingly, in the solid-state imaging device 14 according to the third embodiment, the light 9 that has passed through the photoelectric conversion element 4 and reached the wiring layer 5c is transmitted to the first wiring in the peripheral portion R of the pixel array 23c. When it hits the pattern 51c, it is reflected in the direction indicated by the thick arrow in FIG.

  For this reason, the solid-state imaging device 14 according to the third embodiment can suppress the light 9 reflected by the first wiring pattern 51c in the first layer from entering the adjacent photoelectric conversion element 4.

  Therefore, the solid-state imaging device 14 according to the third embodiment can suppress the occurrence of color mixture between adjacent pixels in the peripheral portion R of the pixel array 23c.

  Further, in the solid-state imaging device 14 according to the third embodiment, a part of the light 9 that has passed through the photoelectric conversion element 4 and reached the wiring layer 5b in the central portion M and the peripheral portion R of the pixel array 23c is It passes through the interlayer insulating film 50 formed between the one wiring pattern 51c.

  Therefore, the solid-state imaging device 14 according to the third embodiment can suppress the occurrence of flare and ghost because the amount of light 9 reflected to the wiring layer 5c is reduced.

  Next, a method for manufacturing the solid-state imaging device 14 including the method for forming the pixel array 23c described above will be described. The manufacturing method of the solid-state imaging device 14 is the same except that the step of forming the first wiring pattern 51 of the first layer shown in FIG. 8C is different from the steps shown in FIGS. The solid-state imaging device 14 is manufactured through the content process. In the following embodiments, different steps will be described with reference to FIG.

  FIG. 17 and FIG. 18 are explanatory views of the manufacturing process of the solid-state imaging device 14 according to the third embodiment in cross-sectional view. 17 and 18 show a method of forming the peripheral portion R of the pixel array 23c, and the central portion M of the pixel array 23c is not shown for convenience.

  As shown in FIG. 17A, first, a resist 92 is uniformly formed on the upper surface of the first interlayer insulating film 50. Next, as shown in FIG. 17B, the resist 92 is exposed using a grating mask 93 in which dots are formed so that the light transmittance gradually increases toward the center M of the pixel array 23c. To do.

  Subsequently, by developing the exposed resist 92, as shown in FIG. 18A, a resist mask 94 having a gradient corresponding to the density change of dots of the grating mask 93 is formed.

  Thereafter, as shown in FIG. 18B, using a mask substrate 95 covering a region other than the region where the first wiring pattern 51c is formed, using a resist mask 94 having a gradient, for example, using plasma CVD. Then, copper ions or the like are implanted into the first interlayer insulating film 50.

  At this time, as the resist mask 94 is thicker, the amount of copper ions or the like to be implanted becomes smaller, so that the first wiring pattern 51c having the same gradient as the resist mask 94 can be formed.

  That is, in the peripheral portion R of the pixel array 23c, in the first interlayer insulating film 50, the stripe-shaped first wiring whose light receiving surface is inclined downward from the peripheral portion R of the pixel array 23c toward the central portion M. A pattern 51c is formed. In the central portion M of the pixel array 23c, a stripe-shaped first wiring pattern 51c having no gradient is formed.

  In the manufacturing method of the pixel array 23c described above, the first wiring pattern 51c of the first layer is formed in a stripe shape at the peripheral edge R of the pixel array 23c, and the light receiving surface of the first wiring pattern 51c is used as the pixel array. 23c is formed in a descending gradient from the peripheral edge R to the center M.

  As a result, in the peripheral portion R of the pixel array 23c, when the light 9 that has passed through the photoelectric conversion element 4 and reached the wiring layer 5c hits the first wiring pattern 51c of the first layer, the thick line arrow in FIG. Reflects in the direction shown.

  For this reason, the solid-state imaging device 14 according to the third embodiment can suppress the light 9 reflected by the first wiring pattern 51c in the first layer from entering the adjacent photoelectric conversion element 4.

  Therefore, the solid-state imaging device 14 according to the third embodiment can suppress the occurrence of color mixture between adjacent pixels in the peripheral portion R of the pixel array 23c.

  Further, in the pixel array 23c according to the third embodiment described above, the positions of the microlens 8 and the color filter 7 in the peripheral portion R of the pixel array 23c may be shifted to the center side of the pixel array 23c.

  Thus, by scaling the microlens 8 and the color filter 7 at the peripheral edge R of the pixel array 23c, the light 9 can be incident at a predetermined angle with respect to the light receiving surface of the photoelectric conversion element 4, and adjacent pixels It is possible to further suppress the occurrence of color mixing.

  Next, a schematic configuration of an optical system provided in the digital camera 1 to which the solid-state imaging device 14 according to the first, second, and third embodiments described above is applied will be described with reference to FIG.

  FIG. 19 is an explanatory diagram illustrating a schematic configuration of an optical system provided in the digital camera 1 to which the solid-state imaging device 14 according to the first, second, and third embodiments is applied. Of the constituent elements shown in FIG. 19, the constituent elements having the same functions as those shown in FIG. 1 and FIG. 2 are given the same reference numerals as those shown in FIG. 1 and FIG. Is omitted.

  As shown in FIG. 19, the imaging optical system 13 includes a polarizing filter 96, a photographing lens unit 80, a half mirror 81, a mechanical shutter 82, a solid-state imaging device 14, a lens 83, a prism 84, and a finder 85.

  The polarizing filter 96 is provided on the incident surface of the imaging lens 86b and transmits light of a specific polarization component. Further, the deflection filter 95 is a rotatable structure and can selectively transmit light of a specific polarization component.

  The photographing lens unit 80 includes photographing lenses 86a and 86b, a diaphragm (not shown), and a lens driving mechanism 86c. The stop is disposed between the photographic lens 86a and the photographic lens 86b, and adjusts the amount of light guided to the photographic lens 86b.

  The solid-state imaging device 14 is disposed on the planned image planes of the photographing lenses 86a and 86b. For example, the photographing lenses 86 a and 86 b refract the incident light and form an image of the subject on the imaging surface (pixel arrays 23, 23 b, and 23 c) of the solid-state imaging device 14 via the half mirror 81 and the mechanical shutter 82.

  In the digital camera 1 described above, by providing the polarizing filter 96 on the incident surface of the photographing lens 86a, light of a specific polarization component can be selectively incident on the solid-state imaging device 14.

  As a result, the solid-state imaging device 14 according to the first, second, and third embodiments described above generates more flare and ghost when light of a specific polarization component selected by the polarization filter 96 is incident. Can be suppressed.

  In the pixel arrays 23, 23b, and 23c according to the first, second, and third embodiments described above, the Si layer 30 is P-type and the Si region 31 is N-type, but the Si layer 30 is N-type, The pixel arrays 23, 23b, and 23c may be configured with the Si region 31 as the P type.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Digital camera, 11 Camera module, 12 Post process part, 13 Imaging optical system, 14 Solid-state imaging device, 15 ISP, 16 Storage part, 17 Display part, 20 Image sensor, 21 Signal processing circuit, 22 Peripheral circuit, 23, 23b , 23c pixel array, 24 vertical shift register, 25 timing control unit, 26 CDS, 27 ADC, 28 line memory, 30 P-type Si layer, 31 N-type Si region, 32 semiconductor substrate, 4 photoelectric conversion element, 5b, 5c wiring layer, 50 interlayer insulating film, 51, 51a first wiring pattern, 52, 52b second wiring pattern, 53 third wiring pattern, 54, 55 trench, 6 antireflection film, 60 adhesive layer, 61 support substrate, 7 color filter, 8 micro 80, imaging lens unit, 81 half mirror, 82 mechanical shutter, 83 lens, 84 prism, 85 finder, 86a, 86b imaging lens, 86c lens driving mechanism, 9 light, 90, 91, 92 resist, 93 grating mask, 94 resist Mask, 95 Mask substrate, 96 Polarizing filter, L1, L2 line, S1, S2 space

Claims (6)

A photoelectric conversion element that is provided in the semiconductor layer and receives light incident from one side of the semiconductor layer; and
A first wiring pattern in which a plurality of linear wirings are arranged in parallel with a predetermined interval in the surface direction of the semiconductor layer at a position facing the photoelectric conversion element on the other surface side of the semiconductor layer. A solid-state imaging device comprising: a wiring layer. The wiring layer is
The solid-state imaging device according to claim 1, wherein the first wiring pattern is arranged according to a size of one pixel of the photoelectric conversion element. The wiring layer is
A second wiring in which a plurality of linear wirings are arranged in parallel with a predetermined interval in a direction intersecting the first wiring pattern on the surface opposite to the light receiving surface side of the first wiring pattern. The solid-state imaging device according to claim 1, further comprising a pattern. The second wiring pattern is:
4. The solid-state imaging device according to claim 3, wherein a plurality of linear wires are arranged in parallel at a predetermined interval in a direction orthogonal to the first wiring pattern. The first wiring pattern at the periphery of the semiconductor layer is
5. The solid-state imaging device according to claim 1, wherein the light receiving surface has a downward slope from a peripheral edge portion to a central portion of the semiconductor layer. Forming a plurality of photoelectric conversion elements in the semiconductor layer;
Forming an insulating film on the surface side opposite to the light-receiving surface side of the semiconductor layer;
Forming a first wiring pattern by arranging a plurality of linear wirings parallel to each other at a predetermined interval in the surface direction of the semiconductor layer at a position facing the plurality of photoelectric conversion elements in the insulating film; ,
A method for manufacturing a solid-state imaging device, comprising:

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