JP2012038860A5 - - Google Patents
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- JP2012038860A5 JP2012038860A5 JP2010176468A JP2010176468A JP2012038860A5 JP 2012038860 A5 JP2012038860 A5 JP 2012038860A5 JP 2010176468 A JP2010176468 A JP 2010176468A JP 2010176468 A JP2010176468 A JP 2010176468A JP 2012038860 A5 JP2012038860 A5 JP 2012038860A5
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- semiconductor substrate
- semiconductor
- laminating
- substrates
- stacking
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Claims (21)
複数の半導体基板のうち、第1の半導体基板に対する積層基準を満たす第2の半導体基板を選択する選択ステップと、
前記第1の半導体基板と前記第2の半導体基板とを互いに積層する積層ステップと、
を有する半導体基板の積層方法。 A method of laminating a semiconductor substrate in which at least two semiconductor substrates among a plurality of semiconductor substrates are laminated together ,
A selection step of selecting a second semiconductor substrate satisfying a stacking criterion for the first semiconductor substrate among the plurality of semiconductor substrates;
A laminating step of laminating the first semiconductor substrate and the second semiconductor substrate ;
A method for laminating a semiconductor substrate comprising:
前記選択ステップは、前記第1の半導体基板の前記位置に対して、予め定められた基準を満たす位置に指標が配置された半導体基板を、前記積層基準を満たす前記第2の半導体基板として選択する請求項1に記載の半導体基板の積層方法。 A measurement step of measuring a position of an index provided on the surface of the first semiconductor substrate;
The selection step, relative to the position of the first semiconductor substrate, a semiconductor substrate which index is arranged at a position that satisfies the predetermined criterion is selected as the second semiconductor substrate which satisfies the laminated reference The method for laminating a semiconductor substrate according to claim 1.
前記第2の半導体基板の研磨された面に指標を形成する指標形成ステップと、Forming an index on the polished surface of the second semiconductor substrate; and
を含み、Including
前記計測ステップは、前記指標形成ステップで形成された前記指標の位置を計測し、The measurement step measures the position of the index formed in the index formation step,
前記選択ステップは、前記計測ステップで計測された前記指標の位置に対して前記基準を満たす位置に指標が配置された半導体基板を、前記積層基準を満たす新たな前記第2の半導体基板として選択する請求項2から4のいずれか一項に記載の半導体基板の積層方法。In the selection step, a semiconductor substrate in which an index is arranged at a position satisfying the standard with respect to the position of the index measured in the measurement step is selected as a new second semiconductor substrate that satisfies the stacking standard. The method for laminating a semiconductor substrate according to claim 2.
複数の半導体基板のうち、予め定められた積層基準を満たす第1の半導体基板および第2の半導体基板をそれぞれ選択する選択ステップと、A selection step of selecting a first semiconductor substrate and a second semiconductor substrate that satisfy a predetermined stacking criterion among a plurality of semiconductor substrates,
前記第1の半導体基板と前記第2の半導体基板とを互いに積層する積層ステップと、A laminating step of laminating the first semiconductor substrate and the second semiconductor substrate;
を有する半導体基板の積層方法。A method for laminating a semiconductor substrate comprising:
複数の半導体基板のうち、第1の半導体基板に対する積層基準を満たす第2の半導体基板を選択する選択部と、
前記第1の半導体基板と前記第2の半導体基板とを互いに積層する積層部と、
を備える半導体基板の積層装置。 A semiconductor substrate laminating apparatus for laminating at least two semiconductor substrates among a plurality of semiconductor substrates,
A selection unit that selects a second semiconductor substrate that satisfies a stacking criterion for the first semiconductor substrate among the plurality of semiconductor substrates;
A stacked portion that stacks the first semiconductor substrate and the second semiconductor substrate ;
A semiconductor substrate laminating apparatus comprising:
前記選択部は、前記第1の半導体基板の前記位置に対して、予め定められた基準を満たす位置に指標が配置された半導体基板を、前記積層基準を満たす前記第2の半導体基板として選択する請求項12に記載の半導体基板の積層装置。 A measurement unit that measures the position of an index provided on the surface of the first semiconductor substrate;
The selection unit, with respect to the position of the first semiconductor substrate, a semiconductor substrate which index is arranged at a position that satisfies the predetermined criterion is selected as the second semiconductor substrate which satisfies the laminated reference 13. A semiconductor substrate stacking apparatus according to claim 12 .
複数の半導体基板のうち、予め定められた積層基準を満たす第1の半導体基板および第2の半導体基板をそれぞれ選択する選択部と、A selection unit that selects a first semiconductor substrate and a second semiconductor substrate that satisfy a predetermined stacking criterion among a plurality of semiconductor substrates;
前記第1の半導体基板と前記第2の半導体基板とを互いに積層する積層部と、A stacked portion that stacks the first semiconductor substrate and the second semiconductor substrate;
を備える半導体基板の積層装置。A semiconductor substrate laminating apparatus comprising:
前記複数の基板を重ね合わせる工程は、The step of superimposing the plurality of substrates includes:
請求項1から11のいずれか一項に記載の半導体基板の積層方法を有するデバイスの製造方法。The manufacturing method of the device which has the lamination | stacking method of the semiconductor substrate as described in any one of Claim 1 to 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010176468A JP5617418B2 (en) | 2010-08-05 | 2010-08-05 | Semiconductor substrate laminating method, semiconductor substrate laminating apparatus and device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2010176468A JP5617418B2 (en) | 2010-08-05 | 2010-08-05 | Semiconductor substrate laminating method, semiconductor substrate laminating apparatus and device manufacturing method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012038860A JP2012038860A (en) | 2012-02-23 |
JP2012038860A5 true JP2012038860A5 (en) | 2013-10-10 |
JP5617418B2 JP5617418B2 (en) | 2014-11-05 |
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Family Applications (1)
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JP2010176468A Active JP5617418B2 (en) | 2010-08-05 | 2010-08-05 | Semiconductor substrate laminating method, semiconductor substrate laminating apparatus and device manufacturing method |
Country Status (1)
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JP (1) | JP5617418B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5850412B2 (en) * | 2012-10-02 | 2016-02-03 | 株式会社デンソー | Semiconductor device manufacturing system and semiconductor device manufacturing method |
JP6264831B2 (en) * | 2012-11-06 | 2018-01-24 | 株式会社ニコン | Alignment apparatus, alignment method, and manufacturing method of laminated semiconductor device |
JP6600838B2 (en) * | 2016-03-08 | 2019-11-06 | ボンドテック株式会社 | Alignment apparatus and alignment method |
WO2018012300A1 (en) | 2016-07-12 | 2018-01-18 | 株式会社ニコン | Method for producing laminated substrate, device for producing laminated substrate, system for producing laminated substrate, and substrate treatment device |
KR102388201B1 (en) | 2017-11-02 | 2022-04-19 | 가부시키가이샤 니콘 | Manufacturing method, manufacturing apparatus, and program for laminated substrate |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4543935B2 (en) * | 2005-01-17 | 2010-09-15 | パナソニック株式会社 | Electronic component mounting apparatus and mounting method |
WO2008153086A1 (en) * | 2007-06-12 | 2008-12-18 | Nikon Corporation | Substrate detecting apparatus, substrate aligning apparatus, substrate bonding apparatus having substrate detecting apparatus and substrate aligning apparatus, wafer outer shape detecting apparatus, wafer aligning apparatus, and wafer bonding apparatus having wafer outer shape detecting apparatus and wafer outer shape detec |
WO2010023935A1 (en) * | 2008-08-29 | 2010-03-04 | 株式会社ニコン | Substrate aligning apparatus, substrate aligning method and method for manufacturing multilayer semiconductor |
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2010
- 2010-08-05 JP JP2010176468A patent/JP5617418B2/en active Active
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