JP2012038378A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve detection of a defect in a memory cell reliably with high efficiency, by eliminating influence of leakage characteristics of the memory cell and of imbalance in output characteristics of a sense amplifier.SOLUTION: A semiconductor memory includes: a plurality of static memory cells 5 arranged in a matrix; word lines WLn commonly connected to memory cells arrayed in a row direction; a pair of bit lines BLO and NBLO which are commonly connected to memory cells arrayed in a column direction so as to form a complementary pair; a sense amplifier which is connected to the pair of the bit lines so as to output data externally; a first precharge circuit 7a and a second precharge circuit 7b which set each pair of the bit lines individually to a first precharge voltage; a third precharge circuit 7c and a fourth precharge circuit 7d which set each pair of the bit lines individually to a second precharge voltage; and a first detection output unit 8a and a second detection output unit 8b which externally output a bit line voltage of the pair of the bit lines individually. The semiconductor memory achieves controlling so as to selectively output either of: data from the sense amplifier; and a bit line voltage from the first detection output unit or the second detection output unit.

Description

  The present invention relates to a static semiconductor memory device, and more particularly to a semiconductor memory device capable of reliably detecting defects.

  In recent years, various semiconductor memory devices have been devised, and the degree of integration per device has been steadily increasing in conjunction with miniaturization of semiconductor processes. On the other hand, the operating power supply voltage is decreasing due to the miniaturization of the process and the reduction in power consumption of the specification system, and the potential level and charge amount stored in the semiconductor memory device are also decreasing.

  In addition, along with miniaturization, extremely small defects (leakage, resistance fluctuation, transistor characteristic fluctuation, etc.) that have not been a problem until now have a significant impact on the yield, performance, and reliability of semiconductor memory devices. It has become. For this reason, the inspection time required for detecting a defect increases as the degree of integration increases, which is a major factor in increasing the cost of the semiconductor memory device. On the other hand, defects that cannot be detected are a major issue in ensuring reliability.

  With respect to a static semiconductor memory device (SRAM), which is a typical semiconductor memory device, a part of a technique for detecting a defect of a memory cell disclosed in Patent Document 1 will be described with reference to FIGS. FIG. 11 is a block diagram of the semiconductor memory device, and FIG. 12 is a configuration diagram of a read delay circuit of the semiconductor memory device.

  The memory cell array 4 in the semiconductor memory device of FIG. 11 is formed by arranging static type memory cells 5 in a matrix. A plurality of word lines WLn driven by the word driver 3 of the row decoder section 2 are connected in common to a plurality of static memory cells 5 arranged in the row direction. A plurality of complementary pairs of bit lines BLn and NBLn are connected in common to a plurality of static memory cells 5 arranged in the column direction. Data in the static memory cell 5 is detected and amplified by the sense amplifier 6 via the bit lines BLn and NBLn. The sense amplifier 6 is connected to a read delay circuit Rde that determines the sense amplifier activation timing.

  The control circuit 1 is configured to control the operation of these circuits. DO is a data output terminal for data output from the sense amplifier 6, and TEST1 is an external input terminal to which a control signal TEST1 is input. In this conventional example, a write amplifier and a write delay circuit for writing data are not shown.

  A specific configuration example of the read delay circuit Rde is shown in FIG. This circuit includes a delay buffer 9 composed of an even number of inverters and a selector 10 in order to control the first delay amount and the second delay amount. A drive signal Nr 1 from the control circuit 1 shown in FIG. 11 is input to the input terminal of the delay buffer 9. A signal passing through the four-stage delay buffer 9 is input to the input Y of the selector 10, and a signal passing through the eight-stage delay buffer 9 is input to the input X of the selector 10. The selector 10 selects one of the input X and the input Y according to the control signal TEST1, and outputs it as the drive signal Nr3. In this way, the delay amount of the read delay circuit Rde is controlled by the control signal TEST1.

  A read operation in this semiconductor memory device will be described with reference to FIG. The read operation is started by inputting the clock signal CLK, the address signal ADD, and the memory control signal CON to the control unit 1. First, the word driver 3 starts to operate in response to a signal input from the control unit 1 to the row decoder unit 2, and the word line WLn is activated.

  FIG. 13 shows the operation timing after activation of the word line WLn. The horizontal axis represents the passage of time, and the vertical axis represents the potential of the bit line BL0 (denoted as BLO). FIG. 13A shows the potential change timing of the bit line BL0 when a normal memory cell is being accessed. FIG. 13B shows the timing of potential change of the bit line BL0 when an abnormal memory cell is being accessed. Prior to the start of these operations, both of the bit lines BL0 and NBL0 are precharged to “H (VDD)”.

In FIG. 13, time T1 is the timing at which the word line WLn is activated and the data in the memory cell 5 begins to be output to the bit line BL0. Time T2 is the timing when the sense amplifier 6 is activated by the drive signal Nr3 of the sense amplifier 6 when the input X path is selected as the delay path in the read delay circuit Rde of FIG. Time T3 is the timing when the sense amplifier 6 is activated when the input Y path is selected as the delay path. Since the input Y path has a smaller delay amount,
(Second delay amount = T3-T1) <(first delay amount = T2-T1)
It has become.

  13A and 13B show the case where the output memory data is “L” data. In this case, since the bit line BL0 = “L” and NBL0 = “H”, there is no voltage change after the time T1 on the NBL0 side, so illustration is omitted. Since only the bit line BL0 outputs “L” data after the time T1, the bit line voltage decreases with time. For the sense amplifier 6, the minimum input voltage (Va) necessary for normal operation is determined, and when the sense amplifier 6 is activated, the minimum input voltage (Va) or more is set between the bit lines BL0 and NBL0. A potential difference is necessary.

  In the case of the normal memory cell shown in FIG. 13A, the potential of the bit line BL0 gradually decreases with a steep slope from the precharge voltage VDD as time elapses. When the input X path is selected as the delay path of the read delay circuit Rde by the control signal TEST1 (time T2), the potential of the bit line BL0 decreases from VDD by the voltage Vsa1. In this case, since Vsa1> Va is satisfied, the sense amplifier 6 can normally amplify the potential difference between the bit lines. When the input Y path is selected as the delay path of the read delay circuit Rde by the control signal TEST1 (time T3), the potential of the bit line BL0 decreases from VDD by the voltage Vsa2. Also in this case, since Vsa2> Va is satisfied, the sense amplifier 6 can normally amplify the potential difference between the bit lines BL0 and NBL0.

  On the other hand, in the case of the abnormal memory cell shown in FIG. 13B, the input voltage to the sense amplifier 6 is Vsa3> Va at time T2, and normal amplification is possible with the sense amplifier 6, but sensing at time T3. When the amplifier 6 is driven, Vsa4 <Va. This is because the abnormal memory cell is slow in changing the potential of the bit line BL0, so that the potential change of Va or more cannot be generated in the bit line BL0 by the time T3 when the sense amplifier 6 is driven. For this reason, the sense amplifier 6 cannot perform normal amplification. Based on this principle, it is possible to detect a memory cell having a reduced ability to drive the bit lines BL0 and NBL0 by increasing the drive time of the sense amplifier 6.

JP 2006-331511 A

  However, the conventional example has the following problems. The first problem in the conventional example will be described with reference to FIGS.

  FIG. 14 is a specific example of the static memory cell 5 shown in FIG. 11, and is composed of six transistors (6Tr-SRAM cell). That is, a pair of inverters 11 and 12 for storing data, an n-type MOS transistor Ta11 for outputting the stored data to the bit line BL0 by activation of the word line WLn, and an n-type MOS transistor Ta12 for outputting to the bit line NBL0. Composed. The inverters 11 and 12 are configured such that their outputs are connected to the other input. The inverter 11 includes a p-type MOS transistor Tp11 and an n-type MOS transistor Tn11, and the inverter 12 includes the p-type MOS transistor Tp12 and the n-type MOS transistor Tn12. It comprises a type MOS transistor Tn12.

  When the memory cell array of the conventional example is constituted by these 6Tr-SRAM cells, the output node N11 of the inverter 11 becomes “L” and the output node N12 of the inverter 12 becomes “H” in the operation of FIG. After the activation of the word line WLn, it is the serial connection element of the n-type MOS transistor Ta11 and the n-type MOS transistor Tn11 that lowers the potential of the bit line BL0 precharged to VDD. If the potential of the bit line NBL0 is lowered contrary to the operation of FIG. 13, the output node N11 of the inverter 11 becomes “H”, the output node N12 of the inverter 12 becomes “L”, and the word line WLn is activated and then becomes VDD. It is the series connection element of the n-type MOS transistor Ta12 and the n-type MOS transistor Tn12 that lowers the potential of the precharged bit line NBL0.

  For this reason, in the above conventional example, defects occur in the n-type MOS transistor Ta11, n-type MOS transistor Tn11, n-type MOS transistor Ta12, and n-type MOS transistor Tn12 that lower the potentials of the bit lines BL0 and NBL0, and the bit lines BL0 and NBL0. When the driving ability of the battery is reduced, it is easy to detect an abnormality.

  On the other hand, in the above conventional example, a defect generated in one or both of the p-type MOS transistor Tp11 and the p-type MOS transistor Tp12 cannot always be detected. The reason will be described in detail below.

  FIG. 15 is an equivalent circuit in the case where a defect occurs in which the drain of the p-type MOS transistor Tp12 is open in the static memory cell 5 of FIG. A resistor Rp12 shown in FIG. 15 is a parasitic leak resistance between the internal node N12 and the power supply VDD. The resistor Rn12 is a parasitic leak resistance between the internal node N12 and the ground VSS. Resistor Ra12 is a parasitic leak resistance between internal node N12 and bit line NBL0. The capacitance Cn12 is a parasitic capacitance that the internal node N12 has.

  FIG. 16 shows an operation in the case where data is held in the equivalent circuit of FIG. 15 by a timing chart of potential change of each part. In the figure, the line WLn is the activation timing of the word line WLn, the line NBP is the precharge timing, the lines BL0 and NBL0 are the potential changes of the bit lines BL0 and NBL0, and the lines N11 and N12 are the potential changes of the internal nodes N11 and N12. Indicates.

  As shown in FIG. 16, when the word line WLn is activated at time t0, desired data is written into the memory cell of FIG. 15 via the bit lines BL0 and NBL0 (in FIG. “L” for node N11, “H” for internal node N12).

After the writing is completed, after the word line WLn is closed at time t1, the “H” data written to the internal node N12 is held in the parasitic capacitor Cn12 because the p-type MOS transistor Tp12 is not connected. The parasitic capacitance Cn12 is a capacitance of the wiring or the junction and is generally on the order of several fF (10 to the 15th power). Where parasitic leakage resistance is
Rn12 <{(Ra12 × Rp12) / (Ra12 + Rp12)}
In this case, the holding potential of the parasitic capacitor Cn12 rapidly decreases, and the holding data of the memory cell is inverted when the inverter 11 falls below the level (VN11) where the inverter 11 recognizes the input “L” at time t3. If the word line WLn is activated after this time (for example, time t4) and a read operation is started, normal data cannot be read out, and an abnormality can be detected.

  However, when Rn12 is slightly smaller than {(Ra12 × Rp12) / (Ra12 + Rp12)}, the decrease in the holding potential of the parasitic capacitance Cn12 is slow. For this reason, the time t3 when the holding potential of the parasitic capacitance Cn12 reaches a state below the level (VN11) is delayed, and a long time is required from the time t1. Therefore, in order to detect an abnormality, an enormous waiting time is required after data is written in the memory cell until the word line WLn is activated, leading to an increase in inspection cost.

further,
Rn12 ≧ (Ra12 × Rp12) / (Ra12 + Rp12)
In this case, since the parasitic capacitance Cn12 is a very small capacitance, the data written in the internal node N12 is easily held, a normal read operation is performed, and a defect cannot be detected.

However, it is not uncommon for these defects to change (deteriorate over time) with the use (operation) time. Further, other transistor characteristics and parasitic resistance characteristics also change over time. if,
Rn12 ≧ (Ra12 × Rp12) / (Ra12 + Rp12)
Even when the normal operation is performed in the state of, when the parasitic resistance Rn12 increases due to the characteristic change over time,
Rn12 <(Ra12 × Rp12) / (Ra12 + Rp12)
As a result, normal data cannot be read.

  Next, the second problem in the conventional example will be described with reference to FIGS.

  FIG. 17 is a timing chart showing the operation of the sense amplifier 6 in the semiconductor memory device of FIG. 11. Line | BLO-NBLO | is a change in potential difference between bit lines BL0 and NBL0, and line Nr3 is a read delay circuit Rde. The timing of the output signal and the line DO indicate the potential change of the data output terminal DO.

  The sense amplifier 6 has a minimum input voltage (Va) necessary for normal operation, and when activated (Nr3 = "H"), when there is an input potential difference of Va or more, a correct output is obtained. can get. In the case of the operation shown in FIG. 17, since the potential difference | BLO−NBLO | is larger than Va, a correct output can be obtained from the sense amplifier 6. However, when the input voltage is lower than Va, the sense amplifier 6 is in a certain output state. The sense amplifier 6 is unbalanced (biased) depending on various conditions such as transistors, resistors, capacitors, and noise received from the vicinity, and the output is either “H” or “L”. It tends to be biased.

  FIG. 18 shows an operation in the case of a memory cell in which the driving capability on the bit line BL0 side is lowered. In this case, after the word line WLn is activated at time t0, the potential drop of the BLO is slow. When a read operation is performed with such a memory cell, the potential of BLO is not sufficiently lowered when the sense amplifier is activated (Nr3 = “H”), and the potential difference | BLO−NBLO | The input potential difference to is Va or less. In this state, when the sense amplifier 6 has an unbalance in which the output “H” tends to be inclined, the output becomes “H”, and an abnormality can be detected.

  However, as in the case shown in FIG. 19, it is a memory cell in which the driving capability on the bit line BL0 side is reduced as in FIG. 18, and the sense amplifier 6 has an unbalance that tends to tilt to the output “L”. In this case, although the input potential difference to the sense amplifier 6 is equal to or less than Va, the output becomes “L”, a correct output is pseudo-output, and an abnormality cannot be detected.

  However, when transistor characteristics and leakage characteristics change over time with long-term use, the unbalance factor of the sense amplifier 6 changes and the ease of output tilting changes. As a result, as shown in FIG. 19, a memory cell that has been operating normally in the initial state causes an abnormal operation with the passage of time. When the input of the sense amplifier 6 is Va or less, the probability that the output is biased to “H” is about 50%, and therefore the probability that the output is biased to “L” is about 50%. That is, a defect can be detected only with a probability of 50%.

  The present invention solves the above-described problem, and eliminates the influence of the unbalanced tendency of the leak characteristics of the static memory cells or the output characteristics of the sense amplifier, thereby ensuring the defects of the static memory cells with high efficiency. It is an object to provide a semiconductor memory device that can be inspected.

  In order to solve the above problems, a semiconductor memory device according to the present invention includes a plurality of static memory cells arranged in a matrix, and a word line commonly connected to the plurality of static memory cells arranged in a row direction. A bit line pair commonly connected to a plurality of the static memory cells arranged in a column direction and forming a complementary pair, and a sense connected to the bit line pair forming the complementary pair and outputting the data of the static memory cells to the outside An amplifier, a first precharge circuit for setting one bit line of the bit line pair forming the complementary pair to a first precharge potential, and a first precharge for the other bit line of the bit line pair forming the complementary pair A second precharge circuit for setting the potential; a third precharge circuit for setting one bit line of the bit line pair forming the complementary pair to a second precharge potential; A fourth precharge circuit for setting the other bit line of the bit line pair forming the complementary pair to a second precharge potential, and a first precharging circuit for outputting one bit line potential of the bit line pair forming the complementary pair to the outside. A test output unit; and a second test output unit that outputs the other bit line potential of the bit line pair forming the complementary pair to the outside, and the data from the sense amplifier or the first or second test output unit Can be controlled to selectively output any one of the bit line potentials.

  According to the above configuration, one bit line potential and the other bit line potential of the complementary bit line pair are individually set by the precharge circuit, and the individual bit line potentials are output to the outside by the inspection output unit. It is possible to inspect the memory cell for defects without activating the amplifier. This eliminates the influence of the unbalanced tendency of the leak characteristics of the static memory cell or the output characteristics of the sense amplifier, and can detect defects generated in the static memory cell with high efficiency and reliability.

1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. Timing chart showing a read operation of a normal static memory cell of the semiconductor memory device Timing chart showing defect detection operation for NBL0 side p-type MOS transistor in normal static type memory cell of the same semiconductor memory device Timing chart showing defect detection operation for BL0 side p-type MOS transistor in a normal static memory cell of the semiconductor memory device Timing chart showing defect detection operation for NBL0 side n-type MOS transistor in normal static type memory cell of same semiconductor memory device Timing chart showing defect detection operation for BL0 side n-type MOS transistor in a normal static memory cell of the same semiconductor memory device Timing diagram showing a defect detection operation in the case where an open defect has occurred in the NBL0 side p-type MOS transistor in the static memory cell of the same semiconductor memory device Timing chart showing a defect detection operation in the case where an open defect has occurred in the BL0 side p-type MOS transistor in the static memory cell of the semiconductor memory device. Timing chart showing defect detection operation in the case where an open defect has occurred in the NBL0 side n-type MOS transistor in the static memory cell of the semiconductor memory device Timing chart showing a defect detection operation in the case where an open defect has occurred in the BL0 side n-type MOS transistor in the static memory cell of the semiconductor memory device. Circuit diagram of semiconductor memory device using static memory cell in conventional example The figure which shows the read system delay circuit in the same semiconductor memory device Operation timing diagram of the semiconductor memory device The figure which shows the structure of the static type memory cell of a prior art example Equivalent circuit diagram when an open defect occurs in the p-type MOS transistor in the static memory cell Operation timing chart when an open defect occurs in the p-type MOS transistor in the static memory cell Timing chart for normal operation of the static memory cell Timing chart showing operation at the time of detecting a defect in the static memory cell Timing chart showing malfunction at the time of detecting a defect in the static memory cell

  The semiconductor memory device of the present invention can take the following modes based on the above configuration.

  That is, a defect of a MOS transistor included in the static memory cell is selectively inspected by a combination of driving of the first to fourth precharge circuits and selection of driving of the first and second inspection output units. It can be constituted as follows.

  The first precharge potential may be a power supply potential, and the second precharge potential may be a ground potential.

  In addition, the first precharge circuit and the second precharge circuit may be configured by p-type MOS transistors, and the third precharge circuit and the fourth precharge circuit may be configured by n-type MOS transistors.

(Embodiment)
An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to the present embodiment. FIG. 2 is a timing chart showing a normal read operation of the semiconductor memory device of FIG. Note that elements substantially the same as those of the conventional semiconductor memory device shown in FIG. 11 are denoted by the same reference numerals, and the description thereof is partially omitted.

  The memory cell array 4 in the semiconductor memory device of FIG. 1 is configured by arranging static memory cells 5 in a matrix. A plurality of word lines WL0, WL1,... WLn are connected in common to a plurality of static memory cells 5 arranged in the row direction. A plurality of complementary pairs of bit lines BLn and NBLn (BL0 and NBL0 in FIG. 1) are connected in common to a plurality of static memory cells 5 arranged in the column direction. Data in the static memory cell 5 is detected and amplified by the sense amplifier 6 via the bit lines BLn and NBLn.

  The first precharge circuit 7a and the third precharge circuit 7c included in the bit line precharge circuit 7 are connected to one bit line BL0 of the bit line pair forming the complementary pair. A second precharge circuit 7b and a fourth precharge circuit 7d are connected to the other bit line NBL0 of the bit line pair forming the complementary pair. The first and second precharge circuits 7a and 7b are made of p-type MOS transistors, and each set the bit line BL0 and the bit line NBL0 to the first precharge potential. The third and fourth precharge circuits 7c and 7d are composed of n-type MOS transistors, and each set the bit line BL0 and the bit line NBL0 to the second precharge potential. In this embodiment, the first precharge potential is the power supply potential (VDD), and the second precharge potential is the installation potential (VSS).

  The amplifier 8a constituting the bit line amplifier circuit 8 is connected to one bit line BL0 of the complementary bit line pair and outputs the potential to the outside via the data output terminal DO. The amplifier 8b is connected to the other bit line NBL0 of the complementary bit line pair and outputs the potential to the outside via the data output terminal DO. Each of the amplifiers 8a and 8b functions as an inspection output unit for detecting a defect.

  Next, a normal read operation of the semiconductor memory device shown in FIG. 1 will be described with reference to FIG. The static memory cell 5 in FIG. 1 has the same configuration as the memory cell 5 in the conventional example of FIG. 14, and FIG. 14 is also referred to in the description of the operation.

  In FIG. 2, DBL is a gate signal of the first precharge circuit 7a, DNBL is a gate signal of the second precharge circuit 7b, SBL is a gate signal of the third precharge circuit 7c, and SNBL is a gate signal of the fourth precharge circuit 7d. Signal. ABL is an activation signal for the BL0 side amplifier 8a, and ANBL is an activation signal for the NBL0 side amplifier 8b. During the read operation, both the gate signal SBL and the gate signal SNBL are maintained at “L”, and the second precharge potential is not supplied.

  FIG. 2 shows a read operation in a state where logic “0” (internal node N11 is “L” and internal node N12 is “H”) is written in static memory cell 5. In FIG. 2, during the time t0 to t1, all the word lines are “L”, and the gate signal DBL of the first precharge circuit 7a and the gate signal DNBL of the second precharge circuit 7b are both “L”. Both bit lines BL0 and NBL0 are precharged to "H".

  Next, at time t1, since the gate signal DBL of the first precharge circuit 7a and the gate signal DNBL of the second precharge circuit 7b both become “H”, the precharge of the bit lines BL0 and NBL0 is completed.

  Next, at time t2, the word line WLn becomes “H” and the n-type MOS transistors Ta11 and Ta12 in the static memory cell 5 are turned on, so that the internal node N11 and the bit line BL0, and the internal node N12 and the bit line are turned on. NBL0 becomes conductive. At this time, since the internal node N12 and the bit line NBL0 are both “H”, the potential variation does not appear in the bit line NBL0. On the other hand, since the internal node N11 is “L” and the bit line BL0 is “H”, the potential of the bit line BL0 is gradually decreased through Ta11 → Tn11 in the static memory cell 5 and the potential gradually decreases. To go.

  Next, since the sense amplifier drive signal Nr3 becomes active ("H") at time t3, the potential of the bit line BL0 is pulled to "L" level all at once and "L" (logic "" from the data output terminal DO). 0 ") is output. At this time, the potential of the bit line NBL0 does not change.

  Similarly, the read operation in a state where logic “1” (internal node N11 is “H” and internal node N12 is “L”) is written in static memory cell 5 is as follows. That is, when the word line WLn becomes “H”, the potential of the bit line NBL0 is lowered, and “H” is output from the output terminal DO. In this manner, data previously written in the static memory cell 5 is read out.

  Next, the defect detection operation in the static memory cell 5 of FIG. 1 will be described with reference to FIGS. 3 to 6 are timing charts showing the operation when the static memory cell 5 is not defective.

  FIG. 3 shows an operation timing chart in a mode for inspecting whether or not the transistor Tp12 (see FIG. 14) of the static memory cell 5 is defective. In this inspection mode, since the sense amplifier 6 is not used, the sense amplifier activation signal Nr3 is set in advance so as not to move from "L". Further, in order to inspect Tp12 for driving the NBL0 side, the activation signal ANBL of the NBL0 side amplifier 8b is set to “H”, and the activation signal ABL of the BL0 side amplifier 8a is set to “L”. During the inspection mode, the gate signal DBL of the first precharge circuit 7a and the gate signal DNBL of the second precharge circuit 7b are both maintained at "H".

  At time t0, since the gate signal SBL of the third precharge circuit 7c and the gate signal SNBL of the fourth precharge circuit 7d are both “H”, the bit lines BL0 and NBL0 are both “L”.

  At time t1, since the gate signal SNBL of the fourth precharge circuit 7d becomes “L”, the bit line NBL0 is in a high impedance state (the potential is maintained at “L”).

  At time t2, the word line WLn becomes “H”, the n-type MOS transistors Ta11 and Ta12 in the static memory cell 5 are turned on, and the internal node N11 and the bit line BL0, and the internal node N12 and the bit line NBL0 are in a conductive state. Become. At this time, since the bit line BL0 is fixed at “L”, the internal node N11 becomes “L”, and the transistor Tp12 is turned on. As a result, the internal node N12 becomes “H”, and the potential of the bit line NBL0 gradually rises to “H” via the transistor Ta12. At this time, since the sense amplifier 6 and the amplifier 8a are in an inactive state and the amplifier 8b is in an active state, the state of the bit line NBL0 is output from the output terminal DO and becomes “H”.

  FIG. 4 is an operation timing chart in a mode in which the presence or absence of a defect in the transistor Tp11 of the static memory cell 5 is inspected by the same operation as that of FIG. The operations of N11 and N12, SBL and SNBL, ABL and ANBL, and BL0 and NBL0 are merely interchanged with respect to the operation of FIG.

  FIG. 5 shows an operation timing chart in a mode for inspecting whether or not the transistor Tn12 of the static memory cell 5 is defective. In this inspection mode, the control of the sense amplifier 6, the amplifier 8a, and the amplifier 8b is the same as in FIG. During this inspection mode, the gate signal SBL of the third precharge circuit 7c and the gate signal SNBL of the fourth precharge circuit 7d are both maintained at "L".

  At time t0, since the gate signal DBL of the first precharge circuit 7a and the gate signal DNBL of the second precharge circuit 7b are both “L”, the bit lines BL0 and NBL0 are both “H”.

  At time t1, since the gate signal DNBL of the second precharge circuit 7b becomes “H”, the bit line NBL0 is in a high impedance state (the potential is maintained at “H”).

  At time t2, the word line WLn becomes “H”, the n-type MOS transistors Ta11 and Ta12 in the static memory cell 5 are turned on, and the internal node N11 and the bit line BL0, and the internal node N12 and the bit line NBL0 are conductive. Become. At this time, since the bit line BL0 is fixed to “H”, the internal node N11 is set to “H”, and the transistor Tn12 is turned on. As a result, the internal node N12 becomes “L”, and the potential of the bit line NBL0 gradually decreases to “L” via the transistor Ta12. At this time, since the sense amplifier 6 and the amplifier 8a are in an inactive state and the amplifier 8b is in an active state, the state of the bit line NBL0 is output from the output terminal DO and becomes “L”.

  FIG. 6 shows an operation timing chart in a mode in which the presence or absence of a defect in the transistor Tn11 of the static memory cell 5 is inspected by the same operation as that of FIG. Since the operations of N11 and N12, SBL and SNBL, ABL and ANBL, and BL0 and NBL0 are interchanged with respect to the operation of FIG. 5, detailed description is omitted.

  Next, the operation when a defect occurs in the static memory cell will be described with reference to FIGS.

  FIG. 7 corresponds to FIG. 3 and is an operation timing chart when the transistor Tp12 of the static memory cell 5 has the same defect as in FIG. Since the transistor Tp12 is not connected, the internal node N12 does not become “H” at time t0 and remains “L”. Other operations at times t0 and t1 are the same as those in FIG.

  At time t2, the word line WLn is activated and the third precharge circuit 7c is in the ON state (SBL is “H”). Therefore, the bit line BL0 is fixed to the ground potential, and the internal node of the static memory cell 5 is N11 becomes “L”. However, since the transistor Tp12 is open, the potential of the internal node N12 does not rise and remains “L”, and the potential of the bit line NBL0 does not change from “L”. For this reason, the output from the output terminal DO via the amplifier 8b also remains “L”, and an abnormality can be detected.

  FIG. 8 is an operation timing chart in a case where a defect occurs in the transistor Tp11 of the static memory cell 5 and the transistor Tp11 enters an open state. Since the operations of N11 and N12, SBL and SNBL, ABL and ANBL, and BL0 and NBL0 are interchanged with respect to the operation of FIG. 7, detailed description is omitted.

  FIG. 9 corresponds to FIG. 5 and is an operation timing chart in the case where a defect occurs in the transistor Tn12 of the static memory cell 5 and the transistor Tn12 is in an open state. Since the transistor Tn12 is not connected, the internal node N12 does not become “L” at time t0 and remains “H”. Other operations at times t0 and t1 are the same as those in FIG.

  At time t2, the word line WLn is activated, and the bit line BL0 is fixed at the power supply potential because the first precharge circuit 7a is in the ON state (SBL is “L”), and the internal node of the static memory cell 5 N11 becomes “H”. However, since the transistor Tn12 is open, the potential of the internal node N12 does not decrease and remains “H”, and the potential of the bit line NBL0 does not change from “H”. For this reason, the output from the output terminal DO via the amplifier 8b also remains “H”, so that an abnormality can be detected.

  FIG. 10 is an operation timing chart in the case where a defect occurs in the transistor Tn11 of the static memory cell 5 and the transistor Tn11 enters an open state. Since the operations of N11 and N12, SBL and SNBL, ABL and ANBL, and BL0 and NBL0 are interchanged with respect to the operation of FIG. 9, detailed description thereof is omitted.

  As described above, the semiconductor memory device of the present embodiment combines the selection of driving of the first to fourth precharge circuits 7a to 7c and driving of the amplifiers (inspection output units) 8a and 8b, thereby combining the static type. It is possible to control to selectively inspect defects of the MOS transistors Tp11, Tn11, Tp12, and Tn12 included in the memory cell 5.

  The configuration of the semiconductor memory device according to the present invention eliminates the influence of the leak characteristic of the static memory cell or the imbalance tendency of the output characteristic of the sense amplifier, and reliably and efficiently inspects the defect of the static memory cell. It is possible to reduce the cost of inspection for defect detection and to reduce the manufacturing cost.

1 control circuit 2 row decoder section 3 word driver 4 memory cell array 5 static memory cell 6 sense amplifier 7 bit line precharge circuit 7a first precharge circuit 7b second precharge circuit 7c third precharge circuit 7d fourth precharge Charge circuit 8 Bit line amplifier circuit 8a, 8b Amplifier 9 Delay buffer 10 Selector 11, 12 Inverter BL0, NBL0, BL1, NBL1 Bit line Cn12 Parasitic capacitance DO Data output terminal Rde Read delay circuit Rp12, Ra12, Rn12 Leak resistance Tp11, Tp12 p-type MOS transistors Ta11, Ta12, Tn11, Tn12 n-type MOS transistors WL0, WL1, WLn Word line

Claims (4)

A plurality of static memory cells arranged in a matrix;
A word line commonly connected to the plurality of static memory cells arranged in a row direction;
A bit line pair commonly connected to a plurality of the static memory cells arranged in a column direction to form a complementary pair;
A sense amplifier connected to the complementary bit line pair and outputting the data of the static memory cell to the outside;
A first precharge circuit for setting one bit line of the pair of complementary bit lines to a first precharge potential;
A second precharge circuit for setting the other bit line of the bit line pair forming the complementary pair to a first precharge potential;
A third precharge circuit that sets one bit line of the pair of complementary bit lines to a second precharge potential;
A fourth precharge circuit that sets the other bit line of the pair of complementary bit lines to a second precharge potential;
A first test output unit for outputting one bit line potential of the pair of bit lines forming the complementary pair to the outside;
A second test output unit for outputting the other bit line potential of the pair of bit lines forming the complementary pair to the outside;
A semiconductor memory device characterized in that it can be controlled to selectively output either data from the sense amplifier or a bit line potential from the first or second test output unit.   A defect of the MOS transistor included in the static memory cell is selectively inspected by a combination of driving of the first to fourth precharge circuits and selection of driving of the first and second inspection output units. The semiconductor memory device according to claim 1 configured.   The semiconductor memory device according to claim 1, wherein the first precharge potential is a power supply potential, and the second precharge potential is a ground potential.   4. The first precharge circuit and the second precharge circuit are constituted by p-type MOS transistors, and the third precharge circuit and the fourth precharge circuit are constituted by n-type MOS transistors. The semiconductor memory device according to any one of the above.

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