JP2012033690A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a semiconductor device with an ohmic electrode formed on a via hole.SOLUTION: A semiconductor device comprises: a substrate 10; a semiconductor layer 12 formed on the substrate 10; and an ohmic electrode 20 constituting a source electrode or a drain electrode, which is formed on a semiconductor layer 12. In the substrate 10 and the semiconductor layer 12, a via hole 30 penetrating the substrate 10 and the semiconductor layer 12 is formed. The via hole 30 includes a first via hole 32 at least penetrating the semiconductor layer, and a second via hole 34 that is formed in the substrate 10 under the first via hole 32 and that has a larger opening cross-sectional area than the second via hole 32. The ohmic electrode 20 is provided on the first via hole 32.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A semiconductor device in which a semiconductor layer is formed on a substrate and a via hole penetrating the substrate and the semiconductor layer is formed is known. When forming a via hole, a method is generally used in which a via receiving pad is formed on a semiconductor layer on the substrate surface, and the substrate and the semiconductor layer are etched all at once from the back surface of the substrate. A semiconductor device in which an ohmic electrode (for example, a source electrode) that is a part of a transistor is formed in an opening of a via hole on the surface side of a substrate is known (see, for example, Patent Document 1).

JP 2008-98456 A

  In the semiconductor device described above, since it is necessary to form an ohmic electrode so as to cover the opening of the via hole, it is difficult to reduce the size of the device.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the size of a semiconductor device in which an ohmic electrode is formed on a via hole.

  The semiconductor device includes a substrate, a semiconductor layer formed on the substrate, and an ohmic electrode constituting a source or drain electrode formed on the semiconductor layer, and the substrate and the semiconductor layer include: A via hole penetrating the substrate and the semiconductor layer is formed, and the via hole is cut off from the first via hole formed in at least the first via hole penetrating the semiconductor layer and the substrate under the first via hole. A second via hole having a large area, and the ohmic electrode is provided on the first via hole.

  The said structure WHEREIN: The outer peripheral end of the contact area | region of the said semiconductor layer and the said ohmic electrode can be set as the structure located inside the said 2nd via hole, when it sees from the thickness direction of the said board | substrate.

  The said structure WHEREIN: The outer peripheral end of the contact area | region of the said semiconductor layer and the said ohmic electrode can be set as the structure located outside the said 2nd via hole, when it sees from the thickness direction of the said board | substrate.

  In the above configuration, the second via hole may penetrate the substrate and reach the lower surface of the semiconductor layer.

  In the above configuration, the second via hole may not penetrate the substrate and may not reach the lower surface of the semiconductor layer.

  The said structure WHEREIN: It can be set as the structure provided with the via | veer receiving pad provided inside the opening part of the said 1st via hole in the lower side of the said ohmic electrode.

  The said structure WHEREIN: The outer peripheral end of the contact area | region of the said via receiving pad and the said semiconductor layer can be set as the structure located inside a said 2nd via hole, when it sees from the thickness direction of the said board | substrate.

  In the above configuration, the substrate may include a SiC substrate, and the semiconductor layer may include a nitride semiconductor layer.

  The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a semiconductor layer is provided on an upper surface of a substrate, the step of etching an upper side of the semiconductor layer and forming a first via hole penetrating the semiconductor layer; Forming an ohmic electrode constituting a source or drain electrode in the opening of the first via hole on the semiconductor layer, and etching the substrate to form a second via hole reaching the first via hole from the lower surface of the substrate. Forming.

  According to the present invention, in a semiconductor device in which an ohmic electrode is formed on a via hole, the size of the device can be reduced.

FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a comparative example. FIG. 2 is a diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment and a modification thereof. FIG. 4 is a top view illustrating the configuration of the semiconductor device according to Example 1 and the comparative example. FIG. 5 is a diagram illustrating the method of manufacturing the semiconductor device according to the second embodiment. FIG. 6 is a diagram illustrating a configuration of a semiconductor device according to the second embodiment and its modification.

(Comparative example)
First, a semiconductor device according to a comparative example will be described.

  1A to 1B are schematic cross-sectional views of a semiconductor device according to a comparative example. As shown in FIG. 1A, the semiconductor layer 12 is formed on the substrate 10, and the via hole 30 penetrating the substrate 10 and the semiconductor layer 12 is formed. In the following description, of the two main surfaces of the substrate 10, the main surface on the side where the semiconductor layer 12 is formed is referred to as the upper surface, and the opposite main surface is referred to as the lower surface.

  A via receiving pad 22 is formed in the opening of the via hole 30 on the semiconductor layer 12 so as to cover the opening. Furthermore, an ohmic electrode 20 is formed so as to cover the via receiving pad 22. The ohmic electrode 20 is, for example, a part of an electrode constituting a transistor (for example, a source electrode). The ohmic electrode 20 and the semiconductor layer 12 are in contact with each other at the periphery of the via receiving pad 22. The inside of the via hole 30 and the lower surface of the substrate 10 are metallized to form a metal layer 40. The metal layer 40 is electrically connected to the ohmic electrode 20 via the via receiving pad 22.

  FIG. 1B is an example in which the ohmic electrode 20 also serves as the via receiving pad 22 in FIG. The ohmic electrode 20 is formed so as to cover the opening of the via hole 30 and is in contact with the semiconductor layer 12 at the periphery of the opening.

  In any case of FIGS. 1A to 1B, the ohmic electrode 20 is formed in a wider range than the opening of the via hole 30. Further, since the via hole 30 is formed by etching the substrate 10 and the semiconductor layer 12 at once, the upper and lower opening cross-sectional areas of the via hole are substantially equal. That is, the size of the ohmic electrode 20 depends on the opening cross-sectional area below the via hole 30. It is difficult to reduce the opening cross-sectional area on the lower side of the via hole 30 because the metallization in the via hole 30 may deteriorate. From the above, it is difficult to reduce the size of the ohmic electrode 20 and the size of the semiconductor device.

  2A to 2E are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 2A, the semiconductor layer 12 is formed on the upper surface of the substrate 10. As the substrate 10, for example, a substrate made of SiC can be used. The semiconductor layer 12 includes, for example, a nitride semiconductor layer, and includes, for example, a 300 nm buffer layer made of AlN, a 1000 nm channel layer (electron transit layer) made of i-GaN, and 20 nm made of n-AlGaN. The electron supply layer and the 5 nm cap layer made of n-GaN are sequentially stacked. In addition, GaN, AlN, InN, InGaN, AlGaN, InAlN, InAlGaN, or the like can be used for the nitride semiconductor layer.

First, as shown in FIG. 2A, the upper side of the semiconductor layer 12 is etched to form a first via hole 32 that penetrates the semiconductor layer 12. The formation of the first via hole 32 can be performed by using, for example, a chlorine-based gas (for example, Cl ₂ ) as an etching gas and performing, for example, reactive ion etching (RIE) dry etching.

  Next, as illustrated in FIG. 2B, the via receiving pad 22 is formed so as to cover the semiconductor layer 12 in and around the first via hole 32. For example, Ni can be used for the via receiving pad 22. Next, as shown in FIG. 2C, an ohmic electrode 20 (hereinafter referred to as the source electrode 20) is formed above the first via hole 32 so as to cover the via receiving pad 22. At the same time, the gate electrode 50 and the drain electrode 60 are formed on the semiconductor layer 12. The source electrode 20, the gate electrode 50, the drain electrode 60, and the semiconductor layer 12 functioning as a channel layer constitute a field effect transistor. As these electrode materials, for example, a laminate of Ti and Al or a laminate of Ta and Al can be used.

Next, as shown in FIG. 2D, the lower side of the substrate 10 is etched to form a second via hole 34. The second via hole 34 is a through hole that penetrates the substrate 10 and reaches the lower surface of the semiconductor layer 12, and has a larger opening cross-sectional area than the first via hole 32. The formation of the second via hole 34 can be performed by, for example, RIE dry etching using, for example, a fluorine-based gas (eg, SF ₆ ) as an etching gas. A via hole 30 including the first via hole 32 and the second via hole 34 penetrates the substrate 10 and the semiconductor layer 12.

  Finally, as shown in FIG. 2E, metallization is performed on the lower surface of the substrate 10 and the inside of the via hole 30 to form a metal layer 40. For example, the metal layer 40 may have a configuration in which a plating layer containing Au is formed on a seed layer containing Ni and Au. The source electrode 20 on the upper surface of the substrate 10 and the metal layer 40 on the lower surface of the substrate 10 are electrically connected via the via receiving pad 22. The semiconductor device according to Example 1 is completed through the above steps.

  In the semiconductor device according to the first embodiment, the via hole 30 includes the first via hole 32 that penetrates the semiconductor layer 12 and the second via hole 34 that penetrates the substrate 10. By forming the first via hole 32 and the second via hole 34 separately, the opening sectional area of the first via hole 32 can be made smaller than the opening sectional area of the second via hole 34. Since the size of the source electrode 20 depends on the opening cross-sectional area of the first via hole 32, the size of the source electrode 20 can be reduced by the above configuration as compared with the comparative example. As a result, the semiconductor device can be reduced in size.

  FIG. 3A is a diagram illustrating a configuration of the semiconductor device according to the first embodiment, and FIGS. 3B to 3D are diagrams illustrating modifications thereof. As shown in FIG. 3A, in Example 1, the outer peripheral edge of the contact region between the via receiving pad 22 and the semiconductor layer 12 is located inside the second via hole 34 when viewed from the thickness direction of the substrate 10. ing. In the comparative example (FIG. 1A), since the outer peripheral edge of the contact area is located outside the second via hole 34, the via receiving pad 22 ( It can also be seen that the source electrode 20) is downsized. On the other hand, also in Example 1, the outer peripheral end of the contact region between the source electrode 20 and the semiconductor layer 12 is located outside the second via hole 34.

  FIG. 3B shows an example in which the second via hole 34 is further miniaturized. Unlike FIG. 3A, the outer peripheral edge of the contact region between the source electrode 20 and the semiconductor layer 12 is located inside the second via hole 34 when viewed from the thickness direction of the substrate 10. According to this configuration, since the transistor including the source electrode 20, the gate electrode 50, and the drain electrode 60 can be reduced in size by reducing the size of the source electrode 20, the semiconductor device can be further reduced in size. be able to. On the other hand, the leakage current from the drain electrode 60 (or the gate electrode 50) to the metal layer 40 in the via hole 30 can be suppressed by keeping the source electrode 20 to a certain size as shown in FIG. .

  FIG. 3C shows an example in which the source electrode 20 also serves as the via receiving pad 22 in FIG. By using the material of the source electrode 20 that is hard to be etched by the etchant used when forming the second via hole 34, the same effect as in the first embodiment can be obtained without forming the via receiving pad 22. Obtainable. According to this configuration, since the step of forming the via receiving pad 22 shown in FIG. 2B can be omitted, the number of manufacturing steps can be reduced. Further, the source electrode 20 can be made smaller than when the via receiving pad 22 is provided. In this case, for example, Ti and Ta can be used as the material of the source electrode 20. However, in the case of the above metal, since the etching selectivity is low, it is necessary to increase the film thickness.

  FIG. 3D shows an example in which the source electrode 20 also serves as the via receiving pad 22 in FIG. Also in this case, the number of steps can be reduced and the source electrode 20 can be made smaller than in the example shown in FIG. Since the manufacturing method and the material of the source electrode 20 are the same as in FIG. 3C, detailed description thereof is omitted.

  FIG. 4A is a schematic top view illustrating the semiconductor device according to the first embodiment, and corresponds to the configuration of FIG. FIG. 4B is a schematic top view showing a semiconductor device according to a comparative example, and corresponds to the configuration of FIG.

  As shown in FIG. 4A, the semiconductor device includes a source electrode 20, a gate electrode 50, and a drain electrode 60. The gate electrode 50 includes a pad 52 and a plurality of fingers 54 branched from the pad 52. Similarly, the drain electrode 60 includes a pad 62 and a plurality of fingers 64 branched from the pad 62. The fingers 54 of the gate electrode 50 are arranged in parallel, and the fingers 64 of the source electrode 20 and the drain electrode 60 are alternately arranged in a region between the fingers 54. The gate electrode 50 and the drain electrode 60 are disposed to face each other.

  The first via hole 32 and the second via hole 34 are indicated by dotted lines in the drawing. The first via hole 32 is located inside the region where the source electrode 20 is formed. On the other hand, the second via hole 34 is located outside the region where the source electrode 20 is formed. That is, in Example 1 (FIG. 4B), the formation region of the source electrode 20 is smaller than the second via hole 34.

  On the other hand, in the comparative example (FIG. 4B), the via hole 30 having the same size as the second via hole 34 in FIG. 4A is located inside the region where the source electrode 20 is formed. That is, the formation region of the source electrode 20 is larger than the via hole 30. As a result, the distance between the two gate electrodes 50 sandwiching the source electrode 20 is larger than that in the first embodiment.

  For example, when the length in the width direction (direction intersecting the longitudinal direction) of the second via hole 34 (symbol A in FIG. 4A) is 50 μm, in the comparative example (FIG. 4B), the source electrode 20 The length in the width direction (symbol B) is about 80 μm. On the other hand, in the modified example of the first embodiment (FIG. 4A), the length can be about 48 μm. Also in the case of Example 1 (FIG. 3A), the length can be about 60 μm. Thus, according to the semiconductor device according to the first embodiment, the size of the device can be reduced in the semiconductor device in which the ohmic electrode is formed on the via hole.

  Example 2 is an example in which the first via hole is formed partway through the substrate.

  5A to 5E are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. Detailed description of portions common to the first embodiment will be omitted. As shown in FIG. 5A, the semiconductor layer 12 is formed on the upper surface of the substrate 10.

First, as shown in FIG. 5A, the upper side of the semiconductor layer 12 is etched to form a first via hole 32 that penetrates the semiconductor layer 12. At this time, etching is performed until not only the semiconductor layer 12 but also a part of the substrate 10 ahead is scraped. When the substrate 10 is an SiC substrate and the semiconductor layer 12 is a nitride semiconductor layer, the first via hole 32 is formed by etching the nitride semiconductor layer using, for example, a chlorine-based gas (for example, chlorine (Cl)) as an etching gas. For example, a part of the substrate 10 is etched by using, for example, a fluorine-based gas (for example, sulfur fluoride (SF ₆ )) as an etching gas, for example, RIE dry etching. It can be formed by performing continuous etching.

  Next, as shown in FIG. 5B, the via receiving pad 22 is formed so as to cover the semiconductor layer 12 inside and around the first via hole 32. Next, as shown in FIG. 5C, the source electrode 20 is formed so as to cover the via receiving pad 22, and the gate electrode 50 and the drain electrode 60 are formed on the semiconductor layer 12.

Next, as shown in FIG. 5D, the lower side of the substrate 10 is etched to form a second via hole 34. The second via hole 34 is a through hole that reaches the first via hole 32 from the lower side of the substrate 10 and has a larger opening cross-sectional area than the first via hole 32. The formation of the second via hole 34 can be performed by, for example, RIE dry etching using, for example, a fluorine-based gas (eg, SF ₆ ) as an etching gas. By controlling the etching time to a predetermined time, the etching can be stopped at a position where the via receiving pad 22 is exposed.

  Finally, as shown in FIG. 5E, metallization is performed on the lower surface of the substrate 10 and the inside of the via hole 30 to form the metal layer 40. Through the above steps, the semiconductor device according to Example 2 is completed.

  FIG. 6A is a diagram illustrating a configuration of a semiconductor device according to the second embodiment, and FIGS. 6B to 6D are diagrams illustrating modifications thereof. 6A to 6D correspond to the forms of FIGS. 3A to 3D of the first embodiment, respectively. That is, in FIG. 6A, the outer peripheral edge of the contact region between the source electrode 20 and the semiconductor layer 12 is located outside the second via hole 34, and in FIG. 6B, the same region is located inside the second via hole 34. positioned. FIG. 6C and FIG. 6D are examples in which the source electrode 20 also serves as the via receiving pad 22.

  According to the semiconductor device according to the second embodiment, as in the first embodiment, the first via hole 32 and the second via hole 34 are separately formed, thereby reducing the size of the source electrode 20 and reducing the size of the semiconductor device. Can be achieved. In addition, by forming the first via hole 32 partway through the substrate 10, the second via hole 34 does not penetrate the substrate 10 and does not reach the lower surface of the semiconductor layer 12. As a result, the second via hole 34 and the semiconductor layer 12 are separated from each other by the substrate 10, so that leakage current from the drain electrode 60 (or the gate electrode 50) to the metal layer 40 in the via hole 30 is suppressed. Can do.

  In the first and second embodiments, the example in which the substrate 10 is a SiC substrate and the semiconductor layer 12 is a nitride semiconductor layer has been described. However, the present invention is not limited to the above configuration. For example, a Si substrate or a GaAs substrate may be used for the substrate 10, and a semiconductor layer other than the nitride semiconductor layer may be used for the semiconductor layer 12.

  In the first and second embodiments, an island source via (ISV) type semiconductor device in which a via hole 30 is formed immediately below the source electrode 20 constituting the transistor in which finger-like electrodes are arranged has been described as an example. . Although the present invention is particularly suitable for the above configuration, the present invention can be similarly applied to a case where a via hole is formed immediately below the drain electrode.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 substrate 12 semiconductor layer 20 ohmic electrode (source electrode)
30 via hole 32 first via hole 34 second via hole 40 metal layer 50 gate electrode 60 drain electrode

Claims (9)

A substrate,
A semiconductor layer formed on the substrate;
An ohmic electrode constituting a source or drain electrode formed on the semiconductor layer,
In the substrate and the semiconductor layer, a via hole penetrating the substrate and the semiconductor layer is formed,
The via hole includes at least a first via hole penetrating the semiconductor layer and a second via hole formed in the substrate under the first via hole and having a larger opening cross-sectional area than the first via hole,
The semiconductor device, wherein the ohmic electrode is provided on the first via hole.   2. The semiconductor device according to claim 1, wherein an outer peripheral end of a contact region between the semiconductor layer and the ohmic electrode is located inside the second via hole when viewed from a thickness direction of the substrate.   2. The semiconductor device according to claim 1, wherein an outer peripheral end of a contact region between the semiconductor layer and the ohmic electrode is located outside the second via hole when viewed from a thickness direction of the substrate.   The semiconductor device according to claim 1, wherein the second via hole penetrates the substrate and reaches a lower surface of the semiconductor layer.   The semiconductor device according to claim 1, wherein the second via hole does not penetrate the substrate and does not reach a lower surface of the semiconductor layer.   The semiconductor device according to claim 1, further comprising a via receiving pad provided inside the opening of the first via hole on the lower side of the ohmic electrode.   The semiconductor device according to claim 6, wherein an outer peripheral end of a contact region between the via receiving pad and the semiconductor layer is located inside the second via hole when viewed from a thickness direction of the substrate.   The semiconductor device according to claim 1, wherein the substrate includes a SiC substrate, and the semiconductor layer includes a nitride semiconductor layer. A method of manufacturing a semiconductor device in which a semiconductor layer is provided on an upper surface of a substrate,
Etching the upper side of the semiconductor layer to form a first via hole penetrating the semiconductor layer;
Forming an ohmic electrode constituting a source or drain electrode in an opening of the first via hole on the semiconductor layer;
Etching the substrate to form a second via hole reaching the first via hole from the lower surface of the substrate;
A method for manufacturing a semiconductor device, comprising:

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