JP2012032888A - Information processor and access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of executing a function to be executed with priority even if an operation part with the function fails.SOLUTION: A function replacement part 31 assigns a function to be executed with priority of a core in which a failure is detected by a failure detection part 30 to another core in which any failure is not detected by the failure detection part 30 by replacing functions between a plurality of cores so that mappings between the plurality of functions and the plurality of cores in arranging the plurality of cores in the order of addresses are shifted in a cyclic manner totally or partially. An address shift part 23 performs a cyclic shift on addresses output from a host processing part 22 in a similar manner as the cyclic shift in the function replacement 31 and outputs the addresses to the plurality of cores.

Description

  The present invention relates to an access technology for a plurality of arithmetic units.

  Conventionally, various techniques for information processing apparatuses have been proposed. For example, Patent Document 1 describes a self-restoring image forming apparatus that is a type of information processing apparatus.

JP-A-5-165277

  In an information processing apparatus, a plurality of arithmetic units such as a DSP (Digital Signal Processor) core may be mounted. In the plurality of arithmetic units, there may be an arithmetic unit having a function that should be prioritized for execution, for example, when the failure occurs, and the minimum performance of the information processing apparatus cannot be ensured.

  Therefore, the present invention has been made in view of the above points, and provides a technique capable of executing a function even when a computing unit having a function that should be prioritized for execution fails. For the purpose.

  In order to solve the above-described problem, an information processing apparatus according to the present invention includes a plurality of arithmetic units that are each assigned an address and accessed by inputting an address assigned to the information processing device, and the plurality of arithmetic units A function for exchanging functions between a failure detection unit that detects a failure, an address shift unit that cyclically shifts addresses directed to the plurality of calculation units, and outputs the addresses to the plurality of calculation units A replacement unit, and when the failure of the calculation unit having a function that should be prioritized for execution is detected in the failure detection unit, the function replacement unit is arranged when the plurality of calculation units are arranged in the order of addresses. By swapping the functions among the plurality of arithmetic units so that the correspondence of the plurality of functions to the plurality of arithmetic units is cyclically shifted in whole or in part, A function that should be prioritized for execution of a calculation unit in which a failure is detected in the failure detection unit is a function of a calculation unit in which no failure is detected in the failure detection unit, and the address shift unit is a function in the function replacement unit Similar to the cyclic shift, each address directed to the plurality of arithmetic units is cyclically shifted and output to the plurality of arithmetic units.

  In one aspect of the information processing apparatus according to the present invention, the functions executed by the plurality of calculation units include a plurality of functions that should be prioritized for execution, and the function replacement unit includes the plurality of calculation units. A failure is detected in the failure detection unit by switching functions between the plurality of calculation units so that the correspondence of the plurality of functions to the plurality of calculation units when arranged in order of addresses is cyclically shifted in whole or in part. Execution of the arithmetic unit in which the failure is detected in the failure detection unit so that the function that should be prioritized in the execution of the arithmetic unit not detected is not the function of the arithmetic unit in which the failure is detected in the failure detection unit Is a function of a calculation unit in which no failure is detected in the failure detection unit.

  Moreover, in one mode of the information processing apparatus according to the present invention, the plurality of arithmetic units are separately mounted on a plurality of chips, and the function executed by the plurality of arithmetic units includes the number of the plurality of chips. A plurality of functions that should be prioritized for execution are included, and in each of the plurality of chips, a plurality of consecutive addresses are assigned to a plurality of arithmetic units mounted on the chip, A plurality of consecutive addresses are assigned to a plurality of arithmetic units having a function whose execution should be prioritized before the function replacement by the function replacement unit.

  Further, the information processing apparatus according to the present invention includes a plurality of arithmetic units that are assigned addresses and are accessed by inputting the addresses assigned to the information processing device, and a fault that detects a fault of the plurality of arithmetic units. A detection unit; an address shift unit that cyclically shifts each address directed to the plurality of calculation units and outputs the address to the plurality of calculation units; and a function switching unit that switches a function between the plurality of calculation units. The functions executed by the plurality of calculation units include a plurality of functions that should be prioritized for execution, and the function replacement unit detects a failure of the calculation unit having a function for which execution should be prioritized by the failure detection unit. In this case, when the plurality of arithmetic units are arranged in the order of addresses, the correspondence of the plurality of functions to the plurality of arithmetic units is partially cyclically shifted and the cyclic cycle is entirely performed. By replacing the functions among the plurality of calculation units so that the failure detection unit detects a failure, the failure detection unit detects the failure of the function of the calculation unit that has not detected a failure. In order not to become a function of the calculation unit, the function that should be prioritized execution of the calculation unit in which the failure is detected in the failure detection unit, a function of the calculation unit in which no failure is detected in the failure detection unit, The address shift unit cyclically shifts the addresses directed to the plurality of calculation units and outputs the addresses to the plurality of calculation units, similarly to the cyclic shift in the function switching unit.

  Moreover, in one aspect of the information processing apparatus according to the present invention, an access processing unit that outputs an address to the address shift unit to access each calculation unit and controls the accessed calculation unit is further provided, and the access processing unit Stores an access map indicating an assignment status of addresses to the plurality of arithmetic units, and outputs an address of an arithmetic unit to be accessed based on the access map.

  The access method according to the present invention is an access method in which an address is input to access a plurality of arithmetic units each assigned an address, and (a) a failure of the plurality of arithmetic units is detected. And (b) the plurality of operation units when the plurality of operation units are arranged in the order of addresses when a failure of the operation unit having a function to be prioritized is detected in the step (a). Priority is given to the execution of the arithmetic unit in which the fault is detected in the fault detection unit by exchanging the functions among the plurality of arithmetic units so that the correspondence of the plurality of functions to the entire or part is cyclically shifted. A function to be performed is a function of a calculation unit in which no failure is detected in the failure detection unit; and (c) the plurality of calculations in the same manner as the cyclic shift in the step (b). Cyclically shifting each address directed to and a step of inputting to the plurality of arithmetic unit.

  The access method according to the present invention is an access method in which an address is input to access a plurality of arithmetic units each assigned an address, and (a) a failure of the plurality of arithmetic units is detected. And (b) a step of exchanging functions among the plurality of arithmetic units; and (c) a step of cyclically shifting each address directed to the plurality of arithmetic units and inputting the addresses to the plurality of arithmetic units. The functions executed by the plurality of arithmetic units include a plurality of functions having an execution priority of a predetermined value or more. In the step (b), the function to be prioritized in the step (a) When a failure of an operation unit is detected, the association of a plurality of functions with the plurality of operation units when the plurality of operation units are arranged in the order of addresses is partially cyclically shifted and entirely cyclically shifted. like By replacing the functions among the plurality of operation units, the function that should be prioritized for execution by the operation unit in which no failure is detected in the failure detection unit is the function of the operation unit in which the failure is detected in the failure detection unit. In order not to become a function, the function that should be prioritized for execution of the calculation unit in which the failure is detected in the failure detection unit is set as the function of the calculation unit in which no failure is detected in the failure detection unit, and the step (c) Then, similarly to the cyclic shift in the step (b), each address directed to the plurality of arithmetic units is cyclically shifted and input to the plurality of arithmetic units.

  According to the present invention, even when a calculation unit having a function that should be prioritized for execution fails, the function can be executed.

It is a figure which shows the structure of the information processing apparatus which concerns on this Embodiment. It is a figure which shows the structure of the control part which concerns on this Embodiment. It is a figure which shows the several core which concerns on this Embodiment. It is a figure which shows an example of the access map which concerns on this Embodiment. It is a flowchart which shows operation | movement of the information processing apparatus which concerns on this Embodiment. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores. It is a figure which shows an example of the access map which concerns on this Embodiment. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores after exchanging a function between a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores after exchanging a function between a plurality of cores. It is a figure which shows the example of a failure occurrence in a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of addresses after changing a function between a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of addresses after changing a function between a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores. It is a figure which shows an example of the access map which concerns on this Embodiment. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores after exchanging a function between a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores after exchanging a function between a plurality of cores. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores. It is a figure which shows a mode that the correlation of several functions with respect to several cores is partially cyclically shifted. It is a figure which shows a mode that the matching of several functions with respect to several cores is cyclically shifted altogether. It is a figure which shows the example of a failure occurrence in a plurality of cores. It is a figure which shows a mode that the correlation of several functions with respect to several cores is partially cyclically shifted. It is a figure which shows a mode that the matching of several functions with respect to several cores is cyclically shifted altogether. It is a figure showing an example of correspondence of a plurality of functions to a plurality of cores.

  FIG. 1 is a diagram illustrating a configuration of an information processing apparatus 100 according to the present embodiment. The information processing apparatus 100 according to the present embodiment is, for example, a communication apparatus, and communicates with a communication partner apparatus using an array antenna. In the information processing apparatus 100, it is possible to control the directivity of the array antenna using the adaptive array antenna system.

  As illustrated in FIG. 1, the information processing apparatus 100 includes a wireless communication unit 1 having an array antenna 10 including a plurality of antennas 10 a and a control unit 2 that manages the operation of the entire information processing apparatus 100.

  The wireless communication unit 1 includes a transmission unit 11 and a reception unit 12. The transmission unit 11 performs up-conversion and amplification processing on the plurality of baseband transmission signals generated by the control unit 2 to generate transmission signals of a plurality of carrier bands. Then, the transmission unit 11 inputs the generated transmission signals of the plurality of carrier bands to the plurality of antennas 10a of the array antenna 10, respectively. As a result, a radio signal is transmitted from the array antenna 10. The receiving unit 12 performs amplification processing and down-conversion on the plurality of reception signals received by the plurality of antennas 10a of the array antenna 10 to generate and output a plurality of baseband reception signals.

  The control unit 2 includes a CPU (Central Processing Unit), a DSP, a memory, and the like. The control unit 2 sets a reception weight for controlling the reception directivity of the array antenna 10 for each of a plurality of baseband reception signals output from the wireless communication unit 1. And the control part 2 synthesize | combines the some received signal to which the receiving weight was set, performs a demodulation process etc. with respect to the synthesized signal obtained by it, and acquires the bit data contained in the said synthesized signal. The control unit 2 performs error correction decoding processing on the acquired bit data and reproduces the bit data from the communication partner apparatus.

  The control unit 2 generates bit data for transmission based on the acquired bit data from the communication partner device. Then, the control unit 2 performs error correction coding processing or the like on the generated bit data, and generates a baseband transmission signal including the processed bit data. As many baseband transmission signals as the plurality of antennas 10a are prepared. The control unit 2 sets a transmission weight for controlling the transmission directivity of the array antenna 10 for each of the generated plurality of transmission signals. A plurality of transmission signals for which transmission weights are set are input to the wireless communication unit 1.

  FIG. 2 is a block diagram showing the configuration of the control unit 2. As shown in FIG. 2, the control unit 2 includes a DSP group 20 composed of a plurality of DSPs 21, a host processing unit 22 that manages the operation of the entire control unit 2, and an address shift unit 23.

  The DSP group 20 includes, for example, three DSPs 21. Each DSP 21 includes, for example, three cores 210 as shown in FIG. Each core 210 is an arithmetic unit that executes a predetermined function by executing an operation program. Accordingly, the control unit 2 is provided with nine arithmetic units. In each DSP 21, three cores 210 are mounted on one semiconductor chip 211. One DSP 21 is housed in one package. Hereinafter, the nine cores 210 may be referred to as first to ninth cores 210, respectively. A to I in FIG. 3 indicate functions executed by the first to ninth cores 210, respectively. However, as will be described later, when at least one of the first to ninth cores 210 fails, the functions of the first to ninth cores 210 may be switched. The numbers shown in parentheses in FIG. 3 indicate the numbers of the cores 210 above them.

  The upper processing unit 22 is configured by a CPU or the like, for example, and accesses each core 210 of the DSP group 20 to control each core 210. The host processing unit 22 that functions as an access processing unit that accesses each core 210 has a failure detection unit 30 and a function switching unit 31 as functional blocks. The failure detection unit 30 can detect a failure of each core 210 of the DSP group 20. The function exchange unit 31 can exchange functions among the plurality of cores 210.

  A unique address is assigned to each of the plurality of cores 210. The assignment status of addresses to the plurality of cores 210 is described in the access map 32 stored in the upper processing unit 22. FIG. 4 is a diagram illustrating an example of the access map 32.

  As shown in FIG. 4, in the access map 32, an address, core identification information (for example, a core number) for identifying the core 210, and function identification information (for example, a function executed by the core 210) Function names) are associated with each other. In the example of FIG. 4, addresses from 1000 to 9000 are assigned to the first to ninth cores 210 at 1000 intervals, respectively. As described above, the functions of the first to ninth cores 210 may be interchanged, but the access map 32 is not changed even if the functions of the first to ninth cores 210 are interchanged. Therefore, in the access map 32, function specifying information for specifying the original function of the core 210 is associated with core specifying information for specifying the core 210. In FIG. 3, a plurality of cores 210 are arranged from the left side to the right side so that assigned addresses become larger.

  When accessing the core 210 having a certain function, the upper processing unit 22 refers to the access map 32, identifies the address of the core 210, and outputs the identified address. If no failure is detected in all of the plurality of cores 210 in the failure detection unit 30, the address output from the upper processing unit 22 is input to the plurality of cores 210 as it is through the address shift unit 23. On the other hand, when a failure of the core 210 having a function that should be prioritized for execution in the failure detection unit 30 (hereinafter referred to as “execution priority function”) is detected, the address output from the host processing unit 22 is The address shift unit 23 converts the address into another address and inputs it to the plurality of cores 210. When the failure detection unit 30 detects a failure of the cores 210 other than the core 210 having the execution priority function, the address output from the host processing unit 22 is directly input to the plurality of cores 210 through the address shift unit 23. Is done. When an address assigned to each core 210 is input, each core 210 receives a command from the host processing unit 22 and performs an operation based on the command.

  As described above, when all of the plurality of cores 210 are operating normally, the upper processing unit 22 can access the core 210 of the output address. On the other hand, when the core 210 having the execution priority function among the plurality of cores 210 fails, the upper processing unit 22 accesses a core 210 different from the core 210 of the output address. . The address conversion method in the address shift unit 23 will be described in detail later.

  When the failure detection unit 30 detects a failure in the core 210 having the execution priority function, the function replacement unit 31 switches the function among the plurality of cores 210. Thereby, the correspondence of the plurality of functions A to I to the plurality of cores 210 changes. The function switching unit 31 stores a plurality of operation programs corresponding to the functions A to I, and loads the plurality of operation programs to the plurality of cores 210 to replace the functions of the plurality of cores 210. When an operation program is sent from the function replacement unit 31, each core 210 executes the operation program from the function replacement unit 31 instead of the operation program that has been executed so far. As a result, each core 210 executes a function corresponding to the operation program from the function switching unit 31. The operation of the function switching unit 31 will be described in detail later.

  Next, failure detection for a plurality of cores 210 in the information processing apparatus 100 will be described in detail. In the information processing apparatus 100, when a failure occurs in any part and a desired characteristic cannot be obtained, for example, when the power of the transmission signal is insufficient, the information processing apparatus 100 performs information processing by the action of the control unit 2. The operation of the apparatus 100 is reset, and the information processing apparatus 100 is restarted. When the information processing apparatus 100 is restarted, in the higher order processing unit 22, the failure detection unit 30 outputs an address to each core 210 to perform access. The failure detection unit 30 determines that the core 210 has failed when data cannot be read from the accessed core 210 or data cannot be written to the core 210. If the entire chip of the DSP 21 fails, all three cores 210 in the DSP 21 will fail.

  Next, the operation of the information processing apparatus 100 when a failure of the core 210 is detected will be described. FIG. 5 is a flowchart showing the operation. In the present embodiment, the functions A to I executed by the plurality of cores 210 include an execution priority function, that is, a function having a high execution priority. In the information processing apparatus 100, when the core 210 having the execution priority function fails and the function cannot be executed, the minimum performance cannot be exhibited.

  In the present embodiment, when the core 210 having the execution priority function fails, the function replacement unit 31 has a plurality of functions A to I when the plurality of cores 210 are arranged in the order of addresses. By replacing the functions among the plurality of cores 210 so that the association of the cores is cyclically shifted, the execution priority function of the failed core 210 is set as the function of the non-failed core 210. Then, the address shift unit 23 cyclically shifts each address output from the higher order processing unit 22 in the same manner as the cyclic shift in the function switching unit 31. Thereby, even if the core 210 having the execution priority function fails, the upper processing unit 22 accesses the core 210 having the execution priority function that operates normally without changing the access map 32. be able to. Hereinafter, the operation of the information processing apparatus 100 will be described in detail with reference to FIG.

  As shown in FIG. 5, when the failure detection unit 30 detects a failure of at least one core 210 in step s1, the higher-level processing unit 22 determines in step s2 based on the function of the failed core 210. It is determined whether the information processing apparatus 100 can continue the operation. In step s2, if the core 210 having the execution priority function is included in the core 210 in which the failure is detected by the failure detection unit 30, the information processing apparatus 100 has the minimum performance. It cannot be demonstrated and it is determined that the operation cannot be continued. Further, the upper processing unit 22 does not execute the function of the failed core 210 even when the core 210 in which the failure is detected by the failure detection unit 30 does not include the core 210 having the execution priority function. Therefore, when the information processing apparatus 100 cannot exhibit the minimum performance, it is determined that the operation cannot be continued. On the other hand, even when the failure detection unit 30 detects a failure of the core 210 and the function of the failed core 210 cannot be executed, the upper processing unit 22 ensures the minimum performance in the information processing apparatus 100. If so, the information processing apparatus 100 determines that the operation can be continued.

  FIG. 6 is a diagram illustrating a specific example of the functions A to I. In this embodiment, the array antenna 10 is assumed to be composed of eight antennas 10a. Each of Rx1 to Rx8 in FIG. 6 represents a reception processing function for performing reception processing such as setting of a weight on a reception signal received from one antenna 10a output from the reception unit 12. Tx in FIG. 6 indicates a transmission processing function for performing transmission processing for generating a plurality of baseband transmission signals input to the transmission unit 11. FIG. 7 is a diagram showing the access map 32 in the example of FIG.

  In this example, eight antennas 10a constituting the array antenna 10 are associated with the eight cores 210 of the first to sixth cores 210 and the eighth and ninth cores 210, respectively. As shown in FIGS. 6 and 7, each of the eight cores 210 has a function of performing reception processing on a reception signal received by the corresponding antenna 10 a. The seventh core 210 has a transmission processing function Tx. Hereinafter, when it is not necessary to particularly distinguish the reception processing functions Rx1 to Rx8, each is referred to as a “reception processing function Rx”.

  In the example of FIG. 6, the transmission processing function Tx is an execution priority function. In the information processing apparatus 100, when the transmission processing function Tx is not executed, that is, when a signal cannot be transmitted to the communication partner apparatus, it is determined that the minimum performance of the information processing apparatus 100 is not exhibited. Therefore, the host processing unit 22 may continue the operation when the core 210 having the transmission processing function Tx is included in the core 210 in which the failure is detected by the failure detection unit 30. Judge that it is not possible.

  In the information processing apparatus 100, when five or more reception processing functions Rx out of the eight reception processing functions Rx are not executed, that is, when an adaptive array antenna system using four or more antennas 10a is not realized. Is determined that the minimum performance of the information processing apparatus 100 is not exhibited. Therefore, when the core 210 in which the failure is detected by the failure detection unit 30 includes five or more cores 210 having the reception processing function Rx, the information processing apparatus 100 continues to operate. Judge that you can not.

  On the other hand, the high-order processing unit 22 does not include the core 210 having the transmission processing function Tx in the core 210 in which the failure is detected in the failure detection unit 30 and the failure detection unit 30 detects the failure. When the number of cores 210 having the processing function Rx is four or less, the information processing apparatus 100 determines that the operation can be continued.

  If it is determined in the upper processing unit 22 that the information processing apparatus 100 can continue the operation, the information processing apparatus 100 continues to operate in step s3. In this case, the address shift unit 23 does not perform the cyclic shift of the address, and the function replacement unit 31 does not perform the function replacement between the plurality of cores 210.

  On the other hand, when it is determined that the information processing apparatus 100 cannot continue the operation in the higher order processing unit 22, in step s 4, the function exchanging unit 31 replaces the functions of the plurality of cores 210 to perform information processing apparatus 100. Is determined to be able to continue operation. In step s4, for example, the function exchanging unit 31 associates a plurality of functions A to I with the plurality of cores 210 when the plurality of cores 210 are arranged in the order of addresses, for example, virtually one by one. It is checked whether the operation of the information processing apparatus 100 can be continued while performing a cyclic shift to virtually replace the functions of the plurality of cores 210. Hereinafter, the association of the plurality of functions A to I with the plurality of cores 210 when the plurality of cores 210 are arranged in the order of addresses may be referred to as “function association”. Also, the process of virtually cyclically shifting the function association may be referred to as “virtual overall shift”. In addition, the replacement of functions among the plurality of cores 210 may be simply referred to as “function replacement”.

  For example, let us consider a case where only the seventh core 210 having the transmission processing function Tx whose execution should be prioritized fails in the example of FIG. The function exchanging unit 31 cyclically shifts only one function association in the right direction, that is, toward the core 210 having the largest address. As a result, as shown in FIG. 8, the function of the eighth core 210 in which no failure has occurred is virtually switched from the reception processing function Rx7 to the transmission processing function Tx. After the virtual entire shift is performed, only one core 210 having the reception processing function Rx has failed, so the information processing apparatus 100 can continue the operation.

  In the example of FIG. 6, consider a case where a chip failure occurs in the DSP 21 having the seventh to ninth cores 210 and all of the seventh to ninth cores 210 fail. When the function switching unit 31 virtually shifts the function association by one in the right direction, the transmission processing function Tx becomes a function of the failed eighth core 210, and thus the information processing apparatus 100 continues to operate. I can't. When the function replacement unit 31 virtually shifts the function association by one cyclically in the right direction, the transmission processing function Tx becomes the function of the failed ninth core 210. 100 cannot continue operation. When the function replacement unit 31 further virtually shifts the function association by one cyclic shift, that is, when the function replacement unit 31 performs a total of three cyclic shifts, as illustrated in FIG. 9, a failure occurs in the transmission processing function Tx. Since the function of the first core 210 is not, the information processing apparatus 100 can transmit. Since only three cores 210 having the reception processing function Rx have failed, the information processing apparatus 100 can continue to operate.

  Further, in the example of FIG. 6, a chip failure occurs in each of the DSP 21 having the first to third cores 210 and the DSP 21 having the fourth to sixth cores 210, and as shown in FIG. Consider a case where each of the six cores 210 fails. In this case, no matter how the function association is cyclically shifted, the number of failures of the core 210 having the reception processing function Rx does not become four or less. Therefore, in this case, the function replacement unit 31 determines that the information processing apparatus 100 cannot continue the operation even if the functions of the plurality of cores 210 are virtually replaced.

  Note that the nine functions associated with the first to ninth cores 210 may be cyclically shifted not to the right but to the left, that is, to the side of the core 210 having the smallest address.

  In step s4, when the function replacing unit 31 determines that the information processing apparatus 100 can continue the operation by virtually replacing the functions of the plurality of cores 210 by virtual overall shift, the information processing apparatus 100 The address shift unit 23 is notified of the mode (shift direction and shift amount) of the virtual overall shift necessary for enabling the operation to continue. Thereafter, step s5 is executed.

  On the other hand, in step s4, even if the function replacement unit 31 virtually replaces the functions of the plurality of cores 210 using the virtual overall shift as in the example of FIG. 10, the information processing apparatus 100 continues to operate. If the information processing apparatus 100 determines that it cannot be performed, in step s7, the information processing apparatus 100 stops the communication operation and notifies the host apparatus (not shown) to that effect.

  In step s5, the function association unit 31 actually cyclically shifts the function association as a whole in the same manner as the virtual whole shift mode necessary for the information processing apparatus 100 to continue the operation. As described above, a plurality of operation programs corresponding to the functions of the plurality of cores 210 are loaded into the plurality of cores 210, respectively.

  For example, in the example of FIG. 8, the operation program corresponding to the transmission processing function Tx is loaded into the eighth core 210, and the eight operation programs corresponding to the reception processing functions Rx1 to Rx8 are the second to seventh cores 210, The ninth core 210 and the first core 210 are loaded respectively. Each core 210 executes the operation program loaded from the function switching unit 31. As a result, the functions are actually exchanged among the plurality of cores 210, and the function association is changed from FIG. 6 to FIG. FIG. 11 is a diagram illustrating a correspondence relationship between the address and the function of the core 210 after the function association is changed as illustrated in FIGS. 6 to 8.

  9, the operation program corresponding to the transmission processing function Tx is loaded into the first core 210, and the eight operation programs corresponding to the reception processing functions Rx1 to Rx8 are the fourth to ninth cores 210, The second core 210 and the third core 210 are loaded respectively. Each core 210 executes the operation program loaded from the function switching unit 31. As a result, the functions are interchanged among the plurality of cores 210, and the function association is changed as shown in FIGS. FIG. 12 is a diagram illustrating a correspondence relationship between the address and the function of the core 210 after the function association is changed as illustrated in FIGS. 6 to 9.

  Even when the function association is changed, the access map 32 of the upper processing unit 22 is not changed.

  When step s5 is executed, the communication operation of the information processing apparatus 100 resumes in step s6. When the communication operation of the information processing apparatus 100 resumes, the address shift unit 23 circulates each address output from the upper processing unit 22 as a whole, in the same manner as the virtual whole shift notified from the upper processing unit 22. shift.

  For example, in the example of FIG. 8, the virtual overall shift mode necessary for enabling the information processing apparatus 100 to continue the operation is “one shift in the right direction”. Cyclically shifts each address from the higher order processing unit 22 to the larger one. For example, the address shift unit 23 converts the address “1000” from the upper processing unit 22 into the address “2000”, and converts the address “2000” from the upper processing unit 22 into the address “3000”. Further, the address shift unit 23 converts the last address “9000” from the upper processing unit 22 into the first address “1000”.

  Further, in the example of FIG. 9, the mode of the virtual overall shift necessary for enabling the information processing apparatus 100 to continue the operation is “three shifts in the right direction”. Cyclically shifts each address from the higher order processing unit 22 to the larger one by three. For example, the address shift unit 23 converts the address “1000” from the upper processing unit 22 into the address “4000”, and converts the address “2000” from the upper processing unit 22 into the address “5000”. Further, the address shift unit 23 converts the last address “9000” from the upper processing unit 22 into an address “3000”.

  As described above, in the present embodiment, when the core 210 having the execution priority function fails, the functions are switched among the plurality of cores 210 so that the function association is cyclically shifted, thereby causing the failure. The execution priority function of the core 210 is a function of the core 210 in which no failure is detected. Therefore, the information processing apparatus 100 can execute the execution priority function even when the core 210 having the execution priority function fails.

  Further, the address shift unit 23 cyclically shifts each address directed to the plurality of cores 210 output from the upper processing unit 22 in the same manner as the function-related cyclic shift in the function switching unit 31. Therefore, even if the core 210 having the execution priority function fails, the upper processing unit 22 changes the access map 32 without changing the correspondence between the core 210 and the address in its own device. The core 210 having the execution priority function can be accessed. In the example of FIGS. 8 and 11, the upper processing unit 22 outputs the address “7000” of the seventh core 210 that had the transmission processing function Tx before the failure, so that it has the transmission processing function Tx after the failure. It is possible to access the eighth core 210 that has become. In the example of FIGS. 9 and 12, the upper processing unit 22 accesses the first core 210 having the transmission processing function Tx after the failure by outputting the address “7000” of the seventh core 210. Can do.

  Further, in the present embodiment, as a function replacement for providing the execution priority function of the core 210 in which a failure is detected to the core 210 in which no failure is detected, a function replacement in which the function association is cyclically shifted. Thus, the execution priority function of the core 210 in which the failure is detected can be provided to the core 210 in which no failure is detected by a very simple process.

  Further, in the present embodiment, the addresses of the core 210 having the execution priority function before the failure detection in the failure detection unit 30 is changed to the failure by cyclically shifting each address output from the upper processing unit 22. Since the address of the core 210 that has the execution priority function after the failure detection in the detection unit 30 is converted, the address of the core 210 having the execution priority function is obtained by a very simple process. It can be converted into the address of the core 210 having the execution priority function.

  Note that, as in the present embodiment, a plurality of cores 210 are separately mounted on a plurality of chips 211, and each of the plurality of chips 211 has a plurality of cores 210 mounted on the chip 211. When a plurality of consecutive addresses are assigned, and the functions of the plurality of cores 210 include a plurality of execution priority functions equal to or more than the number of the chips 211, the plurality of execution priority functions It is desirable to assign a plurality of consecutive addresses to a plurality of cores 210 having The reason for this will be described below.

  For example, the function A of the first core 210, the function D of the fourth core 210, the function F of the sixth core 210, and the function G of the seventh core 210 are execution priority functions, and the execution priority function for each chip 211 Consider a case in which at least one core 210 having the above is mounted and an address is assigned to each of the plurality of cores 210 as in the example of FIG.

  In this case, if a chip failure occurs in the DSP 21 having the seventh to ninth cores 210 and all of the seventh to ninth cores 210 fail as shown in FIG. Even if the virtual entire shift is performed, one of the functions A, D, F, and G always becomes a function of the core 210 that has failed. That is, a failure is detected so that not all of the execution priority functions of the first, fourth, and sixth cores 210 in which no failure has been detected are functions of the seventh to ninth cores 210 in which a failure has been detected. The execution priority function of the seventh core 210 cannot be a function of the core 210 in which no failure is detected. Accordingly, it is not possible to have all of the plurality of execution priority functions in the core 210 that has not failed. In FIG. 13, the core 210 having the execution priority function is indicated by a bold square. The same applies to the following drawings.

  Next, in the example of FIG. 13, consider a case where the function A of the first core 210 and the function H of the eighth core 210 are interchanged, and the function D of the fourth core 210 and the function I of the ninth core 210 are interchanged. The access map 32 in this case is as shown in FIG. In this case, as shown in FIG. 14, four consecutive addresses are assigned to the sixth to ninth cores 210 having the four functions F, G, A, and D which are execution priority functions. ing. In the example of FIG. 14, when a chip failure occurs in the DSP 21 having the seventh to ninth cores 210 and all of the seventh to ninth cores 210 fail as shown in FIG. Is shifted four times in the right direction, all the functions F, G, A, and D can be provided to the core 210 that has not failed. In other words, the seventh to ninth cores 210 in which the failure is detected so that the execution priority function of the sixth core 210 in which no failure is detected does not become the function of the seventh to ninth cores 210 in which the failure is detected. All of the execution priority functions of the core 210 can be functions of the core 210 in which no failure is detected.

  In this way, when a plurality of consecutive addresses are assigned to a plurality of cores 210 having the execution priority function and more than the number of chips 211, a chip failure occurs and all cores 210 of the chip fail. Even so, there is a high possibility that all of the plurality of execution priority functions can be made to wait for the core 210 that has not failed. Therefore, it is possible to suppress the communication operation of the information processing apparatus 100 from stopping.

  Note that the number of execution priority functions included in the functions of the plurality of cores 210 is not limited to four, and may be three or five or more. In any case, by assigning a plurality of consecutive addresses to a plurality of execution priority functions, there is a possibility that all of the plurality of execution priority functions can be kept waiting for the core 210 that has not failed. Can be increased.

<First Modification of Cyclic Shift of Function Correspondence>
In the above example, the function replacement is performed so that the function association is cyclically shifted as a whole. However, the function replacement may be performed so that the function association is partially cyclically shifted.

  For example, in the example of FIG. 6, when only the seventh core 210 having the transmission processing function Tx that should be prioritized for execution fails, as shown in FIG. The functions are switched so that the correspondence of the three functions to the ninth core 210 is cyclically shifted by one in the right direction. As a result, as in the case of FIG. 8, the transmission processing function Tx can be provided to the eighth core 210 that has not failed.

  In the example of FIG. 6, when the seventh to ninth cores 210 fail, as shown in FIG. 17, the correspondence of the six functions to the fourth to ninth cores 210 is 3 in the right direction. The functions are changed so that only one is cyclically shifted. As a result, the transmission processing function Tx can be provided to the fourth core 210 that has not failed.

<Second Modification of Function-Related Cyclic Shift>
In FIG. 3 described above, when the functions A to E and G are execution priority functions, as shown in FIG. 18, when a failure occurs in the seventh to ninth cores 210, the entire function association is performed. Even if the functions are switched so as to cyclically shift, the cores 210 in which no failure has occurred cannot be provided with all of the functions A to E and G. Further, even if the function is switched so that the function association is partially cyclically shifted, all of the functions A to E and G cannot be provided to the core 210 in which no failure has occurred.

  Therefore, in such a case, the function is switched so that the function association is partially cyclically shifted and is also entirely cyclically shifted. Specifically, as shown in FIG. 19, the functions of the seventh to ninth cores 210 are virtually shifted in the right direction by associating the three functions corresponding to the seventh to ninth cores 210. Are virtually replaced. After that, as shown in FIG. 20, the function association is virtually cyclically shifted by one in the right direction, and the functions of the first to ninth cores 210 are virtually interchanged. Then, by loading a plurality of operation programs corresponding to the functions A to I to the plurality of cores 210, the functions of the plurality of cores 210 are actually replaced, and the function association is actually as shown in FIG. To be. As a result, all of the functions A to E and G are mounted on the core 210 in which no failure is detected.

  Further, as shown in FIG. 21, for example, when the functions A to C, E, G, and H are execution priority functions, when the fourth to sixth cores 210 fail, as shown in FIG. In addition, the correspondence of the three functions to the fourth to sixth cores 210 is virtually cyclically shifted by two in the right direction to virtually replace the functions of the fourth to sixth cores 210, and the seventh to ninth The association of the three functions with the core 210 is virtually cyclically shifted by one in the right direction, and the functions of the seventh to ninth cores 210 are virtually interchanged. Thereafter, as shown in FIG. 23, the function association is virtually cyclically shifted by one in the left direction, and the functions of the first to ninth cores 210 are virtually interchanged. Then, by loading a plurality of operation programs corresponding to the functions A to I to the plurality of cores 210, the functions of the plurality of cores 210 are actually replaced, and the function association is actually as shown in FIG. To be. Thereby, all of the functions A to C, E, G, and H are mounted on the core 210 in which no failure is detected.

<Modification of function assignment to core>
Various combinations of a plurality of functions assigned to the plurality of cores 210 are conceivable. Hereinafter, an example of a combination of a plurality of functions assigned to the plurality of cores 210 will be described.

  In the above example, one antenna 10a is associated with each of the eight cores 210. However, the information processing apparatus 100 includes a reception period configured by a plurality of reception slots (reception unit periods), and a plurality of When communicating with a plurality of communication counterpart devices using a TDMA / TDD (Time Division Multiple Access / Time Division Duplexing) method in which transmission periods composed of transmission slots (transmission unit periods) appear alternately, One reception slot may be associated with each of the cores 210. In this case, each of the eight cores 210 performs reception processing on a plurality of reception signals received by the array antenna 10 in a reception slot assigned to itself, and from the plurality of reception signals, the communication partner apparatus The process of acquiring the bit data is performed. Also in this case, the transmission processing function Tx assigned to one core 210 is the execution priority function.

  Further, when the information processing apparatus 100 uses eight antennas 10a as two array antennas each including four antennas 10a, and performs MIMO (Multiple Input Multiple Output) communication using each of the two array antennas. Associates one array antenna with four cores 210 and associates the other array antenna with another four cores 210. Each of the eight cores 210 performs a reception process on a reception signal received by one antenna 10a among the array antennas associated with itself. In this case, the number of non-failed cores 210 that process the received signals received by one array antenna and the number of non-failed cores 210 that process the received signals received by the other array antenna. It is desirable to replace the functions so that the numbers are equal. Also in this case, the transmission processing function Tx assigned to one core 210 is the execution priority function.

  Also, as shown in FIG. 24, a tenth core 210 is mounted as a new core 210 on any one of the three DSPs 21, and an ADPCM (Adaptive Differential Pulse) is installed on the tenth core 210. Functions that perform audio processing such as code modulation and echo cancellation may be assigned. In this case, the transmission processing function Tx and the voice processing function of the tenth core 210 are execution priority functions.

22 upper processing unit 23 address shift unit 30 failure detection unit 31 function switching unit 100 information processing device 210 core

Claims (7)

A plurality of arithmetic units each assigned an address and accessed by inputting the address assigned to itself;
A failure detection unit for detecting a failure of the plurality of arithmetic units;
An address shift unit that cyclically shifts each address directed to the plurality of calculation units and outputs the address to the plurality of calculation units;
A function switching unit for switching functions between the plurality of calculation units;
The function switching unit is
When a failure of a calculation unit having a function to be prioritized is detected in the failure detection unit, a plurality of functions are associated with the plurality of calculation units when the plurality of calculation units are arranged in order of address. By replacing the functions among the plurality of arithmetic units so as to perform a cyclic shift in whole or in part, the fault detection unit has a function to be prioritized for execution of the arithmetic unit in which the fault is detected in the fault detection unit. As a function of the arithmetic unit in which no failure is detected in the unit,
The address shift unit is an information processing apparatus that cyclically shifts addresses directed to the plurality of calculation units and outputs the addresses to the plurality of calculation units, similarly to the cyclic shift in the function switching unit. The information processing apparatus according to claim 1,
The functions executed by the plurality of arithmetic units include a plurality of functions that should be prioritized for execution,
The function switching unit is
By exchanging functions between the plurality of arithmetic units so that the correspondence of the plurality of functions to the plurality of arithmetic units when the plurality of arithmetic units are arranged in the order of addresses is cyclically shifted in whole or in part. In the failure detection unit, a failure is detected so that a function that should be prioritized for execution by a calculation unit in which no failure is detected in the failure detection unit does not become a function of the calculation unit in which the failure is detected in the failure detection unit. An information processing apparatus in which a function that should be prioritized for execution included in the calculation unit is a function of a calculation unit in which no failure is detected in the failure detection unit. An information processing apparatus according to claim 2,
The plurality of arithmetic units are separately mounted on a plurality of chips,
The functions executed by the plurality of arithmetic units include a plurality of functions that should be prioritized for execution more than the number of the plurality of chips.
In each of the plurality of chips, a plurality of consecutive addresses are assigned to a plurality of arithmetic units mounted on the chip,
An information processing apparatus in which a plurality of consecutive addresses are assigned to a plurality of arithmetic units having a function whose execution should be prioritized before the function replacement by the function replacement unit. A plurality of arithmetic units each assigned an address and accessed by inputting the address assigned to itself;
A failure detection unit for detecting a failure of the plurality of arithmetic units;
An address shift unit that cyclically shifts each address directed to the plurality of calculation units and outputs the address to the plurality of calculation units;
A function switching unit for switching functions between the plurality of calculation units;
The functions executed by the plurality of arithmetic units include a plurality of functions that should be prioritized for execution,
The function switching unit is
When a failure of a calculation unit having a function to be prioritized is detected in the failure detection unit, a plurality of functions are associated with the plurality of calculation units when the plurality of calculation units are arranged in order of address. A function to be prioritized for execution of a calculation unit in which no failure is detected in the failure detection unit by switching functions among the plurality of calculation units so as to perform partial cyclic shift and overall cyclic shift However, in order to prevent the failure detection unit from becoming a function of a calculation unit in which a failure has been detected, the failure detection unit has a function that should be prioritized for execution by the calculation unit in which the failure has been detected. As a function of the computing unit that is not detected,
The address shift unit is an information processing apparatus that cyclically shifts addresses directed to the plurality of calculation units and outputs the addresses to the plurality of calculation units, similarly to the cyclic shift in the function switching unit. An information processing apparatus according to any one of claims 1 to 4,
The address shift unit further includes an access processing unit that outputs an address to access each operation unit and controls the accessed operation unit,
The information processing apparatus, wherein the access processing unit stores an access map indicating an assignment status of addresses to the plurality of arithmetic units, and outputs an address of an access destination arithmetic unit based on the access map. An access method for accessing a plurality of operation units each assigned an address by inputting the address,
(A) detecting a failure of the plurality of arithmetic units;
(B) In the step (a), when a failure of an arithmetic unit having a function to be prioritized is detected, a plurality of functions for the plurality of arithmetic units when the arithmetic units are arranged in order of address The function that should be prioritized for execution of the arithmetic unit in which the failure is detected in the failure detection unit is obtained by replacing the functions among the plurality of arithmetic units so that the correspondence of the entire or part is cyclically shifted. , A step as a function of a calculation unit in which no failure is detected in the failure detection unit;
(C) An access method comprising the steps of cyclically shifting each address directed to the plurality of operation units and inputting the addresses to the plurality of operation units in the same manner as the cyclic shift in the step (b). An access method for accessing a plurality of operation units each assigned an address by inputting the address,
(A) detecting a failure of the plurality of arithmetic units;
(B) replacing the function among the plurality of arithmetic units;
(C) cyclically shifting each address directed to the plurality of arithmetic units and inputting the addresses to the plurality of arithmetic units,
The functions executed by the plurality of arithmetic units include a plurality of functions having an execution priority of a predetermined value or more,
In the step (b), in the step (a), when a failure of an arithmetic unit having a function that should be prioritized is detected, the arithmetic units when the arithmetic units are arranged in the order of addresses. An operation unit in which no failure is detected in the failure detection unit by exchanging functions between the plurality of operation units so that the association of a plurality of functions with respect to is partially and cyclically shifted The function that should be prioritized for execution included in the calculation unit in which the failure is detected in the failure detection unit, so that the function that should have priority in execution is not the function of the calculation unit in which the failure is detected in the failure detection unit The function of the arithmetic unit in which no failure is detected in the failure detection unit,
In the step (c), as in the cyclic shift in the step (b), each address directed to the plurality of arithmetic units is cyclically shifted and input to the plurality of arithmetic units.

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