JP2012031004A - SEMI-INSULATIVE GaAs SINGLE CRYSTAL WAFER - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semi-insulative GaAs single crystal wafer which can prevent slip dislocations and cracks generated in a manufacturing step of a semiconductor device.SOLUTION: A semi-insulative GaAs single crystal wafer having a diameter of ≥6 inches is taken as an object. The dislocation density of the peripheral part beyond 0.9R from the center of the wafer is made ≥1.5 times the average value of the dislocation density of the central part located inside 0.9R therefrom, and the dislocation density of the peripheral part is made 120,000 pieces/cm.

Description

  The present invention relates to a semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more. In particular, the present invention provides a semi-insulating GaAs single crystal wafer that contributes to improving the performance of a semiconductor device and manufacturing yield.

  Semi-insulating GaAs single crystal wafers have higher electron mobility than silicon wafers and high sheet resistance of several MΩ / port, so that leakage current and parasitic capacitance can be reduced, so high speed operation and low power consumption are required. Widely used in semiconductor devices such as GaAsFET GaAsIC and the like.

  A semi-insulating GaAs single crystal wafer having high crystallinity is required in order to exhibit the performance expected by a semiconductor device using a semi-insulating GaAs single crystal wafer and realize a high manufacturing yield. A semi-insulating GaAs single crystal wafer is manufactured by, for example, slicing a columnar semi-insulating GaAs single crystal manufactured by a technique called LEC method into a thin disk shape. In the LEC method, a seed crystal is brought into contact with a GaAs raw material melt held in a crucible maintained in a high-pressure inert gas atmosphere and covered with a surface sealing liquid, and the seed crystal is pulled up vertically below the seed crystal. This is a technique for growing a single crystal (Patent Document 1). This LEC method lowers the temperature of a high-temperature GaAs raw material melt exceeding 1200 ° C. at a low rate when pulling up the seed crystal, rotates the seed crystal and the crucible at low speeds in opposite directions, and columnar semi-insulating GaAs single crystal Therefore, complicated control such as controlling the outer diameter to a predetermined value and cooling to room temperature after crystal growth is required. In particular, when a single crystal is grown and cooled, thermal stress is applied due to the temperature difference between the crystal central portion and the outer peripheral portion, so that a specific pattern of dislocation density in the wafer surface, that is, the outer peripheral portion in the wafer surface. It is known that the transition density is higher in the central part. The inventor has paid attention to this point and proposed a method of making the dislocation density at the outer peripheral portion of the wafer higher than that at the central portion (Patent Document 2). Specifically, by defining the temperature gradient in the crystal growth direction during growth, when the radius of the wafer is R, the dislocation density in the region from the center to 2 / 3R is made smaller than that in other regions. Thus, it has been found that this can improve the yield of the manufacturing process of the semiconductor device and reduce the leakage current of the semiconductor device.

JP 2009-23867 JP 2008-273804 A

  Even when the method for manufacturing a semi-insulating GaAs single crystal disclosed in Patent Document 2 is used, improvement in the yield of the manufacturing process of a semiconductor device using the GaAs single crystal wafer and reduction in leakage current of the semiconductor device are not sufficient. For example, in the manufacture of a semiconductor device using a semi-insulating GaAs single crystal having a diameter of 6 inches or more as a wafer, after the epitaxial annealing by activation annealing treatment after ion implantation and vapor phase epitaxial method (MOVPE method) due to the influence of dislocation density, Slip dislocations and wafer cracks occur in a GaAs single crystal wafer, which is disadvantageous in that it cannot be used as a semiconductor device.

One object of the present invention is to provide a semi-insulating GaAs single crystal wafer that solves the above disadvantages.
Other objects of the present invention will become clear from the description of the embodiments.

  The semi-insulating GaAs single crystal wafer of the present invention that achieves the above-described object is characterized by a semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more, and the portion having the highest dislocation density in the plane is the outer periphery. The point is located in the section. Specifically, a region located outside 0.9R from the center of the semi-insulating GaAs single crystal wafer when the radius of the semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more is R is referred to as an outer peripheral portion. In the semi-insulating GaAs single crystal wafer surface, the place with the highest dislocation density is located at the outer peripheral portion.

  Another feature of the semi-insulating GaAs single crystal wafer of the present invention that achieves the above-described object is that the dislocation density in the outer peripheral portion of the semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more is 0. 0 from the center of the wafer. It is in the point which is 1.5 times or more of the average value of dislocation density inside 9R. This makes it possible to reduce the slip occurrence rate to approximately 0%.

Another feature of the semi-insulating GaAs single crystal wafer of the present invention that achieves the above object is that the dislocation density at the outer periphery of the semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more is 120,000 / cm 2. It is in the point which is ² or more.

  According to the present invention, the dislocation density in the outer peripheral portion of a semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more is 1.5 times or more the average value of dislocation density inside 0.9R from the center of the wafer. Therefore, in the process of manufacturing a semiconductor device using a semi-insulating GaAs single crystal wafer, it is possible to prevent the slip S generated at the periphery of the wafer and the bending and cracking of the wafer. This significantly improves the yield in the manufacturing process of the semiconductor device.

1 is a schematic plan view of a semi-insulating GaAs single crystal wafer of the present invention. The present invention is a schematic plan view illustrating slip generated in a semi-insulating GaAs single crystal wafer. It is the schematic which shows the relationship between the dislocation density of an outer peripheral part, a dislocation density ratio (dislocation density of an outer peripheral part / dislocation density of center part), and a slip generation rate. It is a schematic block diagram of the growth furnace used for manufacture of this invention semi-insulating GaAs single crystal wafer.

The best mode of the present invention is directed to a semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more, and has a dislocation density of more than 0.9R from the center of the wafer to the inside of 0.9R from the center of the wafer. The dislocation density is 1.5 times or more of the average value of the dislocation density in the central portion, and the dislocation density in the outer peripheral portion is 120,000 pieces / cm ² or more.
Hereinafter, preferred embodiments of the semi-insulating GaAs single crystal wafer of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view for explaining a semi-insulating GaAs single crystal wafer of the present invention. In the figure, W is a semi-insulating GaAs single crystal wafer having a circular shape with a diameter of 6 inches or more, and its radius is R. A region from the center to 0.9R is referred to as a center portion W1, and a region on the outer peripheral side, that is, a region exceeding 0.9R from the center is referred to as an outer periphery portion W2. The dislocation density of the outer peripheral portion W2 is higher than the dislocation density of the central portion W1, and specifically, the dislocation density of the outer peripheral portion W2 is 1.5 times the dislocation density of the central portion W1. Further, the dislocation density in the outer peripheral portion of the semi-insulating GaAs single crystal wafer is 120,000 / cm ² or more, and the average dislocation density in the central portion is 80,000 / cm ² . By making the dislocation density in this way, in the process of manufacturing a semiconductor device using a semi-insulating GaAs single crystal wafer, slip S generated at the wafer periphery as shown in FIG. Can be prevented.

For the semi-insulating GaAs single crystal wafer, the relationship between the dislocation density in the outer peripheral portion, the dislocation density ratio (dislocation density in the outer peripheral portion / dislocation density in the central portion) and the slip occurrence rate was investigated, and the relationship shown in FIG. 3 was obtained. It was. FIG. 3 shows the relationship with the dislocation density in the outer peripheral portion on the horizontal axis and the dislocation density ratio (dislocation density in the outer peripheral portion / dislocation density in the central portion) on the vertical axis, and the slip occurrence rate as a factor. The region indicated by the broken line in this figure, that is, the dislocation density in the outer peripheral portion is 120,000 / cm ² or more, and the dislocation density ratio (dislocation density in the outer peripheral portion / dislocation density in the central portion) is 1.5 or more. It can be understood that the slip occurrence rate can be reduced to 0%.

  FIG. 4 is a schematic configuration diagram of a growth furnace (LEC furnace) used for manufacturing the semi-insulating GaAs single crystal wafer of the present invention. In the figure, 1 is a pressure vessel, 2 is a crucible made of PBN that melts the raw material disposed in the pressure vessel 1, 3 is connected to a drive device (not shown) installed outside the pressure vessel 1, A pulling shaft 5 that holds the seed crystal 4 at the tip, 5 is a graphite pedestal that supports the crucible 2 by a graphite susceptor 6 and rotates and moves up and down, 7 is a heater that heats the raw material in the crucible 2, and 8 is Inside the pedestal 5 is a thermocouple. The lower end of the pedestal 5 is connected to a drive device (not shown) installed outside the pressure vessel 1.

  FIG. 4 illustrates a method of manufacturing a semi-insulating GaAs single crystal using a growth furnace. In the first case, first, the inside of the pressure vessel 1 is maintained in an inert gas atmosphere at a predetermined pressure, and the group III element Ga and group V element As and the liquid sealing material as raw materials are guided into the crucible 2, and the heater 7 Melt by heating. Specifically, the liquid sealing material is melted when the temperature of the heater 8 reaches the melting temperature of the liquid sealing material, and then the raw material is melted when the melting temperature of the raw material is reached. Generally, since the specific gravity of the GaAs melt 9 is larger than the melt 10 of the liquid sealing material 2, the surface of the GaAs melt 9 is held in the crucible 2 in a state of being covered with the liquid sealing material melt 10. . Thereby, dissociation of the As element from the GaAs melt 9 is prevented. In this state, the pulling shaft 3 is lowered and the seed crystal 4 is brought into contact with the GaAs melt 9 to start crystal growth. While the seed crystal 4 is in contact with the GaAs melt 9, the semi-insulating GaAs single crystal grows on the lower end surface of the seed crystal by slowly pulling up the pulling shaft 3 while gradually lowering the temperature of the GaAs melt 9. . During crystal growth, the pulling shaft 3 and the crucible 2 are rotated in opposite directions.

A method of manufacturing the semi-insulating GaAs single crystal wafer of the present invention using the growth furnace shown in FIG. 4 will be described. A crucible 2 having a diameter of 300 mm is charged with 4 kg of 40 kg of GaAs polycrystalline material and B ₂ O ₃ as a liquid sealing material, and the atmosphere in the pressure vessel is replaced with an inert gas. Specifically, after exhausting by evacuation, the method is filled with an inert gas. In this state, the crucible 2 was heated by the heater 7 to raise the melting point of GaAs to 1238 ° C. or higher, thereby melting the polycrystalline raw material of GaAs. Next, the pulling shaft 3 is lowered, the tip of the seed crystal 4 attached to the lower end is brought into contact with the raw material melt 9, and the temperature is adjusted to 3 ° C./h by the temperature controller after the temperature is sufficiently adjusted. The seed crystal 4 was slowly pulled up at a speed of 6 to 10 mm / h while being lowered at a rate of. During crystal growth, the seed crystal 4 was rotated clockwise by 5 rpm by the pulling shaft 3 and the pedestal 5, and the crucible 2 was rotated counterclockwise by 20 rpm. When the growth of the crystal shoulder was completed and the diameter became about 160 mm, automatic control of the outer diameter of the grown crystal was started by an external controller. The automatic control of the outer diameter is a real-time measurement of the weight of the grown crystal using a load cell installed on the pulling shaft 3, and the outer diameter of the growing crystal is monitored from the increase in weight per unit time and the amount of movement of the pulling shaft 3. In this control, feedback is made to a temperature controller that controls the temperature of the heater 7 so that the outer diameter of the grown crystal becomes a set value. During crystal growth, the amount of the raw material melt 9 gradually decreases as the growth amount increases, and the liquid surface position of the raw material melt 9 decreases. In order to correct the lowering of the liquid surface position of the raw material melt 9, the amount of lowering of the liquid surface is calculated from the output of the load cell installed on the pulling shaft 3. The crucible 2 is automatically raised so as to come to When the grown crystal is pulled up to a predetermined weight of the charged GaAs polycrystal raw material, the temperature of the heater 7 is increased to form the tail shape of the crystal, and then the crystal is separated from the raw material melt 9 to room temperature. After cooling, a columnar semi-insulating GaAs single crystal ingot having a diameter of 160 mm was obtained. This columnar semi-insulating GaAs single crystal ingot is usually processed, that is, its cylindrical outer peripheral surface is ground by a cylindrical grinder to finish to a predetermined size diameter, sliced in a direction perpendicular to the longitudinal direction, and sliced. A semi-insulating GaAs single crystal wafer having a diameter of 152.4 mm (6 inches) was obtained by lapping, etching, polishing, etc. on the disk-shaped substrate. In addition, an oriental flat indicating a crystal orientation may be provided on a semi-insulating GaAs single crystal wafer. When the dislocation density in the region on the outer peripheral side from 0.9R = 137.2 mm from the center of this semi-insulating GaAs single crystal wafer was measured, it was 120,000 pieces / cm ² which was the highest value in the wafer surface, and from the center The average dislocation density in the region inside 0.9R = 137.2 mm was 80,000 pieces / cm ² . The dislocation density was measured by counting the number of etch pits generated by etching a semi-insulating GaAs single crystal wafer with an electron microscope. Using this semi-insulating GaAs single crystal wafer, 100 epitaxial growths were carried out by vapor phase epitaxy, but no slip dislocation or wafer cracking occurred.

W Semi-insulating GaAs single crystal wafer W1 Center portion W2 Outer peripheral portion S Slit R Wafer radius
1 pressure vessel 2 crucible 3 pulling shaft 4 seed crystal 4
5 Pedestal 6 Susceptor 7 Heater 8 Thermocouple 9 Raw material melt 10 Liquid sealant melt

Claims (4)

  A semi-insulating GaAs single crystal wafer having a diameter of 6 inches or more, wherein a portion having the highest dislocation density in the plane is located on the outer periphery. 2. The semi-insulating GaAs single crystal wafer according to claim 1, wherein the outer peripheral portion is located outside 0.9R from the center of the wafer when the radius of the wafer is R.   2. The semi-insulating GaAs single crystal wafer according to claim 1, wherein the dislocation density in the outer peripheral portion is 1.5 times or more the average value of the dislocation density inside 0.9 R from the center of the wafer.   4. The semi-insulating GaAs single crystal wafer according to claim 1, wherein a dislocation density in the outer peripheral portion is 120,000 / cm 2 or more.

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