JP2012028613A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012028613A
JP2012028613A JP2010166934A JP2010166934A JP2012028613A JP 2012028613 A JP2012028613 A JP 2012028613A JP 2010166934 A JP2010166934 A JP 2010166934A JP 2010166934 A JP2010166934 A JP 2010166934A JP 2012028613 A JP2012028613 A JP 2012028613A
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semiconductor chip
mounting portion
paste
semiconductor device
chip
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Hiroshi Kawakubo
弘史 川久保
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Sumitomo Electric Device Innovations Inc
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Sumitomo Electric Device Innovations Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of chip cracks in a semiconductor device in which a semiconductor chip including an SiC substrate is mounted on a mounting portion of Cu.SOLUTION: A semiconductor device 100 comprises: a semiconductor chip 10 including an SiC substrate 12; and a mounting portion 20 made of Cu for mounting the semiconductor chip. The semiconductor chip 10 is bonded to the mounting portion 20 with an Ag paste 30 in which Ag fine particles are dispersed in a solution not containing epoxy. The Ag paste is softer than an AuSn paste and functions as a buffer material for relieving stress transferred from the mounting portion 20 of Cu to the semiconductor chip 10. Therefore, occurrence of chip cracks can be suppressed by using the Ag paste as a brazing material for fixing the semiconductor chip 10 to the mounting portion 20.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

基板材料に炭化珪素（ＳｉＣ）を用いた半導体装置が知られている。例えば、基板上に窒化物系の半導体層（例えば、ＧａＮ系半導体層）を積層することで、高出力の高電子移動度トランジスタ（ＨＥＭＴ：ＨＥＭＴ：High Electron Mobility Transistor）を形成することができる。   A semiconductor device using silicon carbide (SiC) as a substrate material is known. For example, a high-power high electron mobility transistor (HEMT) can be formed by stacking a nitride-based semiconductor layer (for example, a GaN-based semiconductor layer) on a substrate.

ＳｉＣ基板を含む半導体チップを実装部に実装する場合、安価で放熱性に優れた銅（Ｃｕ）実装部を使用することが一般的である。また、ＳｉＣ基板を含む半導体チップをＣｕ実装部に固定する際のロウ材には、金スズ（ＡｕＳｎ）ペーストを使用することが一般的である。   When a semiconductor chip including an SiC substrate is mounted on a mounting portion, it is common to use a copper (Cu) mounting portion that is inexpensive and excellent in heat dissipation. Moreover, it is common to use a gold tin (AuSn) paste for the brazing material when fixing the semiconductor chip including the SiC substrate to the Cu mounting portion.

特開２００９−２８９９３５号公報JP 2009-289935 A

Ｃｕは熱膨張率が大きいため、温度変化に伴いＣｕ実装部が伸縮すると、Ｃｕ実装部の内部で応力が発生し、ＳｉＣ基板を含む半導体チップへと伝達される。ＳｉＣとＣｕは熱膨張率が大きく異なるため、半導体チップには非常に大きな力が加わる。また、半導体チップとＣｕ実装部とを固定するＡｕＳｎペーストは固いため、緩衝材としては十分に機能しない。その結果、半導体チップにクラックが発生してしまう場合がある。   Since Cu has a large coefficient of thermal expansion, when the Cu mounting portion expands and contracts with a change in temperature, stress is generated inside the Cu mounting portion and is transmitted to the semiconductor chip including the SiC substrate. Since SiC and Cu have greatly different coefficients of thermal expansion, a very large force is applied to the semiconductor chip. Further, since the AuSn paste for fixing the semiconductor chip and the Cu mounting portion is hard, it does not function sufficiently as a buffer material. As a result, a crack may occur in the semiconductor chip.

本発明は、上記課題に鑑みなされたものであり、ＳｉＣ基板を含む半導体チップがＣｕ実装部に実装された半導体装置において、チップクラックの発生を抑制することを目的とする。   The present invention has been made in view of the above problems, and an object thereof is to suppress the occurrence of chip cracks in a semiconductor device in which a semiconductor chip including an SiC substrate is mounted on a Cu mounting portion.

本半導体装置は、ＳｉＣ基板を含む半導体チップと、本体がＣｕで構成され前記半導体チップを搭載する実装部とを備え、前記半導体チップは、エポキシを含まない溶剤にＡｇ微粒子を分散したＡｇペーストにより前記実装部に固定されている。   The semiconductor device includes a semiconductor chip including a SiC substrate, and a mounting portion in which a main body is made of Cu and on which the semiconductor chip is mounted, and the semiconductor chip is made of Ag paste in which Ag fine particles are dispersed in a solvent not containing epoxy. It is fixed to the mounting part.

上記構成において、前記半導体チップにおける、前記実装部に固定される側の主面は、Ａｇである構成とすることができる。   The said structure WHEREIN: The main surface of the side fixed to the said mounting part in the said semiconductor chip can be set as the structure which is Ag.

上記構成において、前記基板の厚みは、５０μｍ〜１５０μｍである構成とすることができる。   The said structure WHEREIN: The thickness of the said board | substrate can be set as the structure which is 50 micrometers-150 micrometers.

上記構成において、前記実装部には、ネジ止め用の貫通孔が形成されている構成とすることができる。   The said structure WHEREIN: The said mounting part can be set as the structure by which the through-hole for screwing is formed.

本発明によれば、ＳｉＣ基板を含む半導体チップがＣｕ実装部に実装された半導体装置において、チップクラックの発生を抑制することができる。   ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of a chip crack can be suppressed in the semiconductor device with which the semiconductor chip containing a SiC substrate was mounted in Cu mounting part.

図１は、比較例に係る半導体装置の構成を示す図である。FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a comparative example. 図２は、実施例１に係る半導体装置の製造方法を示す図である。FIG. 2 is a diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. 図３は、実施例１に係る半導体装置の構成を示す図である。FIG. 3 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment.

（比較例）
最初に、比較例に係る半導体装置について説明する。 (Comparative example)
First, a semiconductor device according to a comparative example will be described.

図１は、比較例に係る半導体装置８０を試験装置に搭載した状態を示す図である。図１（ａ）は断面模式図であり、図１（ｂ）は上面模式図である。ＳｉＣ基板を含む半導体チップ１０が、ＡｕＳｎペースト３２によりＣｕ実装部２０に実装されている。（実装部２０は、ヒートシンク等を含む）。Ｃｕ実装部２０は、本体がＣｕ（純銅）で構成され、そのＣｕの上下には、Ｃｕ側からＮｉ，Ａｕの順に積層されたカバー膜がそれぞれ形成されている。Ｃｕ実装部２０の上面（半導体チップ１０が実装された側の面）には、半導体チップ１０を囲むように側壁２４が設けられ、側壁２４の上面はキャップ２６により封止されている。Ｃｕ実装部２０には複数の貫通孔２２が形成され、Ｃｕ実装部２０は貫通孔２２に設けられたネジ４２により、試験用のＡｌ筐体４０に固定されている。   FIG. 1 is a diagram illustrating a state in which a semiconductor device 80 according to a comparative example is mounted on a test apparatus. FIG. 1A is a schematic cross-sectional view, and FIG. 1B is a schematic top view. The semiconductor chip 10 including the SiC substrate is mounted on the Cu mounting portion 20 with the AuSn paste 32. (The mounting unit 20 includes a heat sink and the like). The Cu mounting portion 20 has a main body made of Cu (pure copper), and a cover film in which Ni and Au are laminated in this order from the Cu side is formed above and below the Cu, respectively. A side wall 24 is provided on the upper surface (the surface on which the semiconductor chip 10 is mounted) of the Cu mounting portion 20 so as to surround the semiconductor chip 10, and the upper surface of the side wall 24 is sealed with a cap 26. A plurality of through holes 22 are formed in the Cu mounting portion 20, and the Cu mounting portion 20 is fixed to the test Al housing 40 by screws 42 provided in the through holes 22.

ここで、Ａｌ筐体４０に固定された半導体装置８０に対し、「−６５℃に３０分、室温に５分、１７５℃に３０分」の条件下で１００回の繰り返し環境試験を行った。このとき、基板の厚みは１００μｍ、貫通孔の直径は１００μｍ、貫通孔の数は１７、貫通孔同士のピッチは２２２μｍ、半導体チップのチップサイズは３．９０×０．７２ｍｍ、ネジ締めの圧力は３ｋｇｆ／ｃｍ２、とした。その結果、試験に用いた１０個のサンプルのうち、４個のサンプルにおいてチップクラック（図１の符号１６）が発生した。 Here, the semiconductor device 80 fixed to the Al case 40 was subjected to 100 repeated environmental tests under the conditions of “-65 ° C. for 30 minutes, room temperature for 5 minutes, 175 ° C. for 30 minutes”. At this time, the thickness of the substrate is 100 μm, the diameter of the through holes is 100 μm, the number of through holes is 17, the pitch between the through holes is 222 μm, the chip size of the semiconductor chip is 3.90 × 0.72 mm, and the screwing pressure is 3 kgf / cm 2 . As a result, chip cracks (reference numeral 16 in FIG. 1) occurred in four of the ten samples used in the test.

ＳｉＣ基板を含む半導体チップ１０は、熱膨張率が小さく、硬く割れやすい性質を有する。一方、Ｃｕを材料とする実装部２０は、熱膨張率が大きく、周囲の温度変化に伴い大きく伸縮する。上記の環境試験において、Ｃｕ実装部２０の伸縮に伴い発生した内部応力は、ＡｕＳｎペースト３２を介して半導体チップ１０へと伝達される。Ｃｕ実装部２０の伸縮の繰り返しにより、半導体チップ１０に働く応力の大きさが限界値を超えたときに、半導体チップ１０にチップクラック１６が発生する。図中の矢印は、チップクラック１６が発生した際における応力の働く方向を示す。   The semiconductor chip 10 including the SiC substrate has a low thermal expansion coefficient and has a property of being hard and easily broken. On the other hand, the mounting part 20 made of Cu has a large coefficient of thermal expansion and greatly expands and contracts with changes in ambient temperature. In the above environmental test, the internal stress generated with the expansion and contraction of the Cu mounting portion 20 is transmitted to the semiconductor chip 10 through the AuSn paste 32. When the magnitude of stress acting on the semiconductor chip 10 exceeds the limit value due to repeated expansion and contraction of the Cu mounting portion 20, a chip crack 16 is generated in the semiconductor chip 10. The arrows in the figure indicate the direction in which the stress acts when the chip crack 16 occurs.

ここで、半導体チップ１０とＣｕ実装部２０とを固定するＡｕＳｎペースト３２は硬い材料であるため、Ｃｕ実装部２０から半導体チップ１０に伝達される応力を緩和するための緩衝材としては十分に機能していない。   Here, since the AuSn paste 32 that fixes the semiconductor chip 10 and the Cu mounting part 20 is a hard material, it functions sufficiently as a cushioning material for relaxing the stress transmitted from the Cu mounting part 20 to the semiconductor chip 10. Not done.

図２は、実施例１に係る半導体装置１００の製造方法を示す図である。図２（ａ）に示すように、Ｃｕ実装部２０の上面に側壁２４が形成され、側壁２４の周囲にＣｕ実装部２０の貫通孔２２が形成されている。比較例と異なり、側壁２４内部における半導体チップ１０の実装予定領域には、ＡｕＳｎペーストの代わりにＡｇペースト３０が供給されている。また、実施例１において、Ｃｕ実装部２０のＣｕの仕様は、比較例と同様である。   FIG. 2 is a diagram illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment. As shown in FIG. 2A, a side wall 24 is formed on the upper surface of the Cu mounting part 20, and a through hole 22 of the Cu mounting part 20 is formed around the side wall 24. Unlike the comparative example, an Ag paste 30 is supplied in place of the AuSn paste in a region where the semiconductor chip 10 is to be mounted inside the side wall 24. Moreover, in Example 1, the specification of Cu of the Cu mounting part 20 is the same as that of a comparative example.

最初に、図２（ａ）に示すように、Ａｇペースト３０が設けられた実装予定領域に半導体チップ１０を搭載（ダイボンディング）する。半導体チップ１０の下面（Ｃｕ実装部２０に固定される側の主面）には、Ａｇめっき層１４が設けられている。Ａｇペースト３０のリフロー時の温度は、例えば２００℃とする。また、Ａｇめっき層１４は、めっき以外にも蒸着、スパッタにより形成することもできる。   First, as shown in FIG. 2A, the semiconductor chip 10 is mounted (die-bonded) on the planned mounting area where the Ag paste 30 is provided. An Ag plating layer 14 is provided on the lower surface of the semiconductor chip 10 (the main surface on the side fixed to the Cu mounting portion 20). The temperature during reflow of the Ag paste 30 is, for example, 200 ° C. Further, the Ag plating layer 14 can be formed by vapor deposition or sputtering other than plating.

次に、図２（ｂ）に示すように、側壁２４の上面をキャップ２６により封止する。次に、図２（ｃ）に示すように、Ｃｕ実装部２０及び半導体チップ１０を室温付近（例えば、２５℃）まで冷却する。冷却に伴うＣｕ実装部２０の縮小により、Ｃｕ実装部２０の内部には圧縮方向の応力が残存し、半導体チップ１０の内部には引張方向の応力が残存する（図中の矢印参照）。以上の工程により、実施例１に係る半導体装置１００が完成する。   Next, as shown in FIG. 2B, the upper surface of the side wall 24 is sealed with a cap 26. Next, as shown in FIG. 2C, the Cu mounting portion 20 and the semiconductor chip 10 are cooled to around room temperature (for example, 25 ° C.). Due to the reduction of the Cu mounting part 20 accompanying cooling, the compressive stress remains inside the Cu mounting part 20, and the tensile stress remains inside the semiconductor chip 10 (see arrows in the figure). Through the above process, the semiconductor device 100 according to the first embodiment is completed.

図３は、実施例１に係る半導体装置１００を試験装置に搭載した状態を示す図である。図３（ａ）は断面模式図であり、図３（ｂ）は上面模式図である。ＳｉＣ基板１２を含む半導体チップ１０が、Ａｇペースト３０によりＣｕ実装部２０に実装されている。Ｃｕ実装部２０の上面には、半導体チップ１０を囲むように側壁２４が設けられ、側壁２４の上面はキャップ２６により封止されている。Ｃｕ実装部２０には複数の貫通孔２２が形成され、Ｃｕ実装部２０は貫通孔２２に設けられたネジ４２により、試験用のＡｌ筐体４０に固定されている。   FIG. 3 is a diagram illustrating a state in which the semiconductor device 100 according to the first embodiment is mounted on the test apparatus. FIG. 3A is a schematic sectional view, and FIG. 3B is a schematic top view. The semiconductor chip 10 including the SiC substrate 12 is mounted on the Cu mounting portion 20 with an Ag paste 30. A sidewall 24 is provided on the upper surface of the Cu mounting portion 20 so as to surround the semiconductor chip 10, and the upper surface of the sidewall 24 is sealed with a cap 26. A plurality of through holes 22 are formed in the Cu mounting portion 20, and the Cu mounting portion 20 is fixed to the test Al housing 40 by screws 42 provided in the through holes 22.

ここで、比較例と同様に、Ａｌ筐体４０に固定された半導体装置１００に対し、「−６５℃に３０分、室温に５分、１７５℃に３０分」の条件下で１００回の繰り返し環境試験を行った。このとき、基板の厚みは１００μｍ、貫通孔の直径は１００μｍ、貫通孔の数は１７、貫通孔同士のピッチは２２２μｍ、半導体チップのチップサイズは３．９０×０．７２ｍｍ、ネジ締めの圧力は３ｋｇｆ／ｃｍ２、とした。その結果、試験に用いた１０個のサンプル全てにおいて、チップクラックは発生しなかった。 Here, as in the comparative example, the semiconductor device 100 fixed to the Al case 40 was repeated 100 times under the conditions of “-65 ° C. for 30 minutes, room temperature for 5 minutes, 175 ° C. for 30 minutes”. Environmental tests were conducted. At this time, the thickness of the substrate is 100 μm, the diameter of the through holes is 100 μm, the number of through holes is 17, the pitch between the through holes is 222 μm, the chip size of the semiconductor chip is 3.90 × 0.72 mm, and the screwing pressure is 3 kgf / cm 2 . As a result, chip cracks did not occur in all 10 samples used in the test.

実施例１に係る半導体装置１００によれば、半導体チップ１０とＣｕ実装部２０とを固定するためのロウ材として、Ａｇペースト３０を用いている。ＡｇペーストはＡｕＳｎペーストに比べて柔らかく、Ｃｕ実装部２０から半導体チップ１０に伝達される応力を緩和する緩衝材として機能する。また、Ａｇペーストのリフロー時の温度（約２００℃）は、ＡｕＳｎペーストの融点（約２８０℃）に比べて低い。このため、半導体チップ１０をＣｕ実装部２０に実装後に室温（約２５℃）まで冷却する際に、ＡｕＳｎペーストでは約２５５℃の温度差が、Ａｇペーストでは約１７５℃の温度差がそれぞれ生じる。Ａｇペーストを用いる場合、ＡｕＳｎペーストを用いる場合に比べて冷却時の温度差が小さいため、半導体チップ１０の内部に残存する内部応力が小さい。以上のことから、ＳｉＣ基板１２を含む半導体チップ１０がＣｕ実装部２０に実装された半導体装置１００において、ロウ材としてＡｇペーストを用いることにより、チップクラックの発生を抑制することができる。   According to the semiconductor device 100 according to the first embodiment, the Ag paste 30 is used as the brazing material for fixing the semiconductor chip 10 and the Cu mounting portion 20. The Ag paste is softer than the AuSn paste and functions as a buffer material that relieves stress transmitted from the Cu mounting portion 20 to the semiconductor chip 10. Moreover, the temperature (about 200 ° C.) at the time of reflowing the Ag paste is lower than the melting point (about 280 ° C.) of the AuSn paste. For this reason, when the semiconductor chip 10 is cooled to room temperature (about 25 ° C.) after being mounted on the Cu mounting portion 20, a temperature difference of about 255 ° C. occurs in the AuSn paste and a temperature difference of about 175 ° C. occurs in the Ag paste. When the Ag paste is used, the internal stress remaining in the semiconductor chip 10 is small because the temperature difference during cooling is smaller than when the AuSn paste is used. From the above, in the semiconductor device 100 in which the semiconductor chip 10 including the SiC substrate 12 is mounted on the Cu mounting portion 20, the occurrence of chip cracks can be suppressed by using the Ag paste as the brazing material.

また、実施例１に係る半導体装置１００によれば、半導体チップ１０の下面にＡｇめっき層１４が設けられている。半導体チップ１０にＡｇめっきを施すことにより、半導体チップ１０とＡｇペースト３０との付着性が良好となるため、信頼性をより向上させることができる。   In addition, according to the semiconductor device 100 according to the first embodiment, the Ag plating layer 14 is provided on the lower surface of the semiconductor chip 10. By performing the Ag plating on the semiconductor chip 10, the adhesion between the semiconductor chip 10 and the Ag paste 30 becomes good, so that the reliability can be further improved.

上記実施例において、Ａｇペースト３０には、エポキシを含まない材料（例えば、エポキシを含まない有機溶剤（例えば、ターピネオールC）にＡｇ微粒子を分散したもの）を用いることが好ましい。エポキシは熱伝導性が悪いため、Ａｇペースト３０がエポキシを含まないようにすることで、半導体装置１００の放熱性を向上させることができる。   In the above embodiment, it is preferable to use an epoxy-free material (for example, an Ag-free organic solvent (for example, terpineol C) in which Ag fine particles are dispersed) as the Ag paste 30. Since epoxy has poor thermal conductivity, heat dissipation of the semiconductor device 100 can be improved by preventing the Ag paste 30 from containing epoxy.

上記実施例において、ＳｉＣ基板１２の厚みが所定値より小さいと、半導体チップ１０は柔軟になるためチップクラックが生じにくくなる。また、ＳｉＣ基板１２の厚みが所定値より大きいと、半導体チップ１０が頑丈になるため同様にチップクラックが生じにくくなる。従って、Ａｇペースト３０を用いることによるチップクラックの抑制効果を得るためには、ＳｉＣ基板１２の厚みが５０〜１５０μｍの範囲であることが好ましく、１００〜１５０μｍの範囲であることが更に好ましい。   In the said Example, when the thickness of the SiC substrate 12 is smaller than predetermined value, since the semiconductor chip 10 will become flexible, it will become difficult to produce a chip crack. Further, if the thickness of the SiC substrate 12 is larger than a predetermined value, the semiconductor chip 10 becomes rugged, and similarly, chip cracks are hardly generated. Therefore, in order to obtain the effect of suppressing chip cracks by using the Ag paste 30, the thickness of the SiC substrate 12 is preferably in the range of 50 to 150 μm, and more preferably in the range of 100 to 150 μm.

上記実施例において、半導体装置１００は、試験用のＡｌ筺体４０に実装されている構成としたが、実際の製品では、半導体装置１００は、Ａｌ筺体４０の代わりに回路基板または放熱用の治具に実装されている構成とすることができる。回路基板または放熱用の治具への実装は、例えばネジ止めにより行うことができるが、その場合はネジ止めによりＣｕ実装部２０の伸縮が制限されるため、よりチップクラックが生じやすくなる。このような構成は、Ａｇペースト３０によるチップクラックの抑制効果を得るためにより好適である。また、上記構成のために、Ｃｕ実装部２０には、ネジ止め用の貫通孔が形成されていることが好ましい。   In the above embodiment, the semiconductor device 100 is mounted on the test Al housing 40. However, in an actual product, the semiconductor device 100 may be a circuit board or a heat dissipation jig instead of the Al housing 40. It can be set as the structure mounted in. The mounting on the circuit board or the heat dissipation jig can be performed, for example, by screwing. In this case, since the expansion and contraction of the Cu mounting portion 20 is limited by screwing, chip cracks are more likely to occur. Such a configuration is more suitable for obtaining a chip crack suppressing effect by the Ag paste 30. Moreover, for the said structure, it is preferable that the through-hole for screwing is formed in Cu mounting part 20. As shown in FIG.

上記実施例において、半導体チップ１０は、例えばＳｉＣ基板１２の表面に窒化物半導体層が形成された構成とすることができる。窒化物半導体層は、例えば、ＡｌＮを材料とする３００ｎｍのバッファ層、ｉ−ＧａＮを材料とする１０００ｎｍのチャネル層（電子走行層）、ｎ−ＡｌＧａＮを材料とする２０ｎｍの電子供給層、及びｎ−ＧａＮを材料とする５ｎｍのキャップ層が順に積層された構造を有する。窒化物半導体層には、例えば、ＧａＮ、ＡｌＮ、ＩｎＮ、ＩｎＧａＮ、ＡｌＧａＮ、ＩｎＡｌＮ、ＩｎＡｌＧａＮ等を用いることができる。   In the embodiment described above, the semiconductor chip 10 can be configured, for example, such that a nitride semiconductor layer is formed on the surface of the SiC substrate 12. The nitride semiconductor layer includes, for example, a 300 nm buffer layer made of AlN, a 1000 nm channel layer (electron transit layer) made of i-GaN, a 20 nm electron supply layer made of n-AlGaN, and n -It has a structure in which 5 nm cap layers made of GaN are laminated in order. For example, GaN, AlN, InN, InGaN, AlGaN, InAlN, InAlGaN, or the like can be used for the nitride semiconductor layer.

以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

１０ 半導体チップ
１２ ＳｉＣ基板
１４ Ａｇめっき層
１６ チップクラック
２０ Ｃｕ実装部
２２ 貫通孔
２４ 側壁
２６ キャップ
３０ Ａｇペースト
４０ Ａｌ筺体
４２ ネジ
１００ 半導体装置
DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 SiC substrate 14 Ag plating layer 16 Chip crack 20 Cu mounting part 22 Through-hole 24 Side wall 26 Cap 30 Ag paste 40 Al housing 42 Screw 100 Semiconductor device

Claims (4)

ＳｉＣ基板を含む半導体チップと、
本体がＣｕで構成され前記半導体チップを搭載する実装部とを備え、
前記半導体チップは、エポキシを含まない溶剤にＡｇ微粒子を分散したＡｇペーストにより前記実装部に固定されていることを特徴とする半導体装置。 A semiconductor chip including a SiC substrate;
A main body is made of Cu and includes a mounting portion on which the semiconductor chip is mounted;
The semiconductor device, wherein the semiconductor chip is fixed to the mounting portion with an Ag paste in which Ag fine particles are dispersed in a solvent containing no epoxy. 前記半導体チップにおける、前記実装部に固定される側の主面は、Ａｇであることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a main surface of the semiconductor chip that is fixed to the mounting portion is Ag. 前記基板の厚みは、５０μｍ〜１５０μｍであることを特徴とする請求項１または２のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate has a thickness of 50 μm to 150 μm. 前記実装部には、ネジ止め用の貫通孔が形成されていることを特徴とする請求項１〜３のいずれかに記載の半導体装置。
The semiconductor device according to claim 1, wherein a screw hole is formed in the mounting portion.
JP2010166934A 2010-07-26 2010-07-26 Semiconductor device Pending JP2012028613A (en)

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JP2013211298A (en) * 2012-03-30 2013-10-10 Mitsubishi Materials Corp Power module and manufacturing method of the same
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