JP2012028559A - Electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component which allows size reduction and is also capable of reducing equivalent series resistance (ESR).SOLUTION: A laminate 2 consists of a plurality of laminated dielectric layers and has side faces S1 to S4. An internal conductor 3 is exposed from the laminate 2 at two positions, i.e. side faces S3 and S4, and penetrates through one or more dielectric layers in a laminating direction. A first capacitor conductor is arranged inside the laminate 2 and is electrically connected to the internal conductor 3. A second capacitor conductor is arranged inside the laminate 2 and constitutes a capacitor together with the first capacitor conductor. A first external electrode 5a is arranged on the side face S1 of the laminate 2 and is electrically connected to the second capacitor conductor.

Description

  The present invention relates to an electronic component, and more particularly to an electronic component incorporating a feedthrough capacitor.

  As a conventional electronic component, for example, a through-type three-terminal electronic component (hereinafter referred to as an electronic component) described in Patent Document 1 is known. FIG. 8A is a plan view showing the shape of the signal internal electrode 502 of the electronic component 500 described in Patent Document 1. FIG. FIG. 8B is a plan view showing the shape of the grounding internal electrode 503 of the electronic component 500 described in Patent Document 1. FIG.

  As shown in FIGS. 8A and 8B, the electronic component 500 includes ceramic green sheets 501a and 501b, a signal internal electrode 502, a grounding internal electrode 503, signal external electrodes 505a and 505b, and grounding. External electrodes 506a and 506b and dummy internal electrodes 512a, 512b, 513a and 513b are provided.

  The signal internal electrode 502 is provided on the rectangular ceramic green sheet 501a, and is provided so as to connect the short sides of the ceramic green sheet 501a. The grounding internal electrode 503 is provided on the rectangular ceramic green sheet 501b, and is provided so as to connect the long sides of the ceramic green sheet 501b. The signal internal electrode 502 and the ground internal electrode 503 are opposed to each other with the ceramic green sheet 501b interposed therebetween.

  The signal external electrodes 505a and 505b are respectively provided on the side surfaces of a laminate formed by laminating ceramic green sheets 501a and 501b. The side surface on which the signal external electrodes 505a and 505b are provided is formed by connecting the short sides of the ceramic green sheets 501a and 501b. Accordingly, the signal external electrodes 505a and 505b are connected to both ends of the signal internal electrode 502, respectively.

  The grounding external electrodes 506a and 506b are respectively provided on the side surfaces of the multilayer body. The side surface of the laminate on which the grounding external electrodes 506a and 506b are provided is formed by connecting the long sides of the ceramic green sheets 501a and 501b. Accordingly, the grounding external electrodes 506a and 506b are connected to both ends of the grounding internal electrode 503, respectively.

  The dummy internal electrodes 512a and 512b are respectively provided on the ceramic green sheet 501a and connected to the ground external electrodes 506a and 506b. The dummy internal electrodes 513a and 513b are provided on the ceramic green sheet 501b and are connected to the signal external electrodes 505a and 505b, respectively.

  In the electronic component 500 configured as described above, a signal is transmitted between the signal external electrode 505a and the signal external electrode 505b. Further, noise is transmitted to the grounding external electrodes 506a and 506b due to the capacitance generated between the signal internal electrode 502 and the grounding internal electrode 503.

  In the electronic component 500 configured as described above, dummy internal electrodes 512a, 512b, 513a, and 513b are provided in portions where the signal internal electrode 502 and the ground internal electrode 503 are not provided. Therefore, in electronic component 500, the stacking density of the internal electrodes in the stack can be made uniform. As a result, in the electronic component 500, insufficient sintering and oversintering are prevented, and the resistance of the internal electrode is prevented from increasing.

  Incidentally, in recent years, downsizing of electronic parts 500 as shown in Patent Document 1 is desired. As a method for reducing the size of the electronic component, it is conceivable to reduce the thickness of the internal electrode. However, when the internal electrode is thinned, the cross-sectional area of the internal electrode is reduced, so that ESR (equivalent series resistance) is increased.

JP 2003-22932 A

  Accordingly, an object of the present invention is to provide an electronic component that can be reduced in size and can reduce ESR.

  An electronic component according to an aspect of the present invention includes a laminate in which a plurality of dielectric layers are laminated, and a laminate of one or more dielectric layers that are exposed from the laminate at two locations on the side surface. An inner conductor penetrating in a direction, a first capacitor conductor provided in the multilayer body and electrically connected to the inner conductor, a first capacitor provided in the multilayer body, and the first capacitor A second capacitor conductor constituting a conductor and a capacitor, and a first external electrode provided on the side surface and electrically connected to the second capacitor conductor; It is characterized by.

  An electronic component according to another aspect of the present invention includes a laminate in which a plurality of dielectric layers are laminated, a linearly exposed outer surface of the laminate, and one or more dielectric layers. An inner conductor penetrating in the laminating direction; a first capacitor conductor provided in the laminated body and electrically connected to the inner conductor; provided in the laminated body; and the first A capacitor conductor, a second capacitor conductor constituting the capacitor, and a first external electrode provided on the outer surface of the multilayer body and electrically connected to the second capacitor conductor; It is characterized by having.

  According to the present invention, it is possible to reduce the size and reduce the ESR.

It is an external appearance perspective view of an electronic component. It is a disassembled perspective view of the laminated body of an electronic component. It is the figure which planarly viewed the mode when an electronic component was mounted in the circuit board from the normal line direction of the circuit board. It is a disassembled perspective view of the mother laminated body which is an aggregate | assembly of a laminated body. It is a disassembled perspective view showing a mode that the groove | channel G was formed in the mother laminated body. It is an external appearance perspective view of the electronic component which concerns on a 1st modification. It is a disassembled perspective view of the laminated body of the electronic component which concerns on a 2nd modification. FIG. 8A is a plan view showing the shape of the signal internal electrode of the through-type three-terminal electronic component described in Patent Document 1. FIG. FIG. 8B is a plan view showing the shape of the grounding internal electrode of the electronic component described in Patent Document 1. FIG.

  An electronic component according to an embodiment of the present invention will be described below with reference to the drawings.

(Configuration of electronic parts)
First, the configuration of an electronic component according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an external perspective view of the electronic component 1. FIG. 2 is an exploded perspective view of the multilayer body 2 of the electronic component 1. Hereinafter, the stacking direction of the stacked body 2 is defined as the z-axis direction. The direction in which the long side of the multilayer body 2 extends when the multilayer body 2 is viewed in plan from the z-axis direction is defined as the x-axis direction. The direction in which the short side of the multilayer body 2 extends when the multilayer body 2 is viewed in plan from the z-axis direction is defined as the y-axis direction.

  The electronic component 1 is a chip capacitor. As shown in FIGS. 1 and 2, the multilayer body 2, the internal conductor 3, the external electrodes 5 (5a and 5b), and the capacitors C1 and C2 (not shown in FIG. 1). It has.

  The laminate 2 is combined with the internal conductor 3 to form a rectangular parallelepiped shape. However, the laminated body 2 has a rounded shape at corners and ridgelines by chamfering. The surface of the laminated body 2 is comprised by side surface S1, S2, S3, S4, the upper surface S5, and the lower surface S6. Hereinafter, in the laminate 2, the surface on the positive direction side in the x-axis direction is referred to as a side surface S1, and the surface on the negative direction side in the x-axis direction is referred to as a side surface S2. The surface on the negative direction side in the y-axis direction is referred to as a side surface S3, and the surface on the positive direction side in the y-axis direction is referred to as a side surface S4. Further, the surface on the positive direction side in the z-axis direction is defined as an upper surface S5, and the surface on the negative direction side in the z-axis direction is defined as a lower surface S6. The side surfaces S1 to S4 do not intersect the z-axis direction as shown in FIG.

As shown in FIG. 2, the multilayer body 2 is configured by laminating a plurality of dielectric layers 11 (11 a to 11 j). As a material constituting the dielectric layer 11, for example, a dielectric ceramic composed of main components such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ can be used. Moreover, you may use what added subcomponents, such as a Mn compound, Mg compound, Si compound, Co compound, Ni compound, rare earth compound, to these main components. The thickness of the dielectric layer 11 is preferably 0.5 to 10 μm or less.

  The dielectric layers 11a to 11h have a rectangular shape. The long sides of the dielectric layers 11a to 11h extend in the y-axis direction, and the short sides of the dielectric layers 11a to 11h extend in the x-axis direction. Further, the dielectric layers 11a and 11b are provided at the same position (that is, the same layer) in the z-axis direction, and are opposed to each other through a gap Sp1 extending in the y-axis direction. Similarly to the dielectric layers 11a and 11b, the dielectric layers 11c and 11d, the dielectric layers 11e and 11f, and the dielectric layers 11g and 11h are provided so as to face each other through the gaps Sp2 to Sp4. The dielectric layers 11a, 11c, 11e, and 11g are overlapped with each other when viewed in plan from the z-axis direction. Similarly, the dielectric layers 11b, 11d, 11f, and 11h overlap with each other when viewed in plan from the z-axis direction.

  The dielectric layers 11i and 11j have a rectangular shape and are made of a dielectric ceramic. The long sides of the dielectric layers 11i and 11j extend in the x-axis direction, and the short sides of the dielectric layers 11i and 11j extend in the y-axis direction. The dielectric layers 11i and 11j overlap with each other when viewed in plan from the z-axis direction. Further, the short sides on the positive side in the x-axis direction of the dielectric layers 11i and 11j are on the positive side in the x-axis direction of the dielectric layers 11a, 11c, 11e, and 11g when viewed in plan from the z-axis direction. It overlaps with the long side. Similarly, the short sides on the negative side in the x-axis direction of the dielectric layers 11i and 11j are the negative side in the x-axis direction of the dielectric layers 11b, 11d, 11f, and 11h when viewed in plan from the z-axis direction. It overlaps with the long side of. Hereinafter, the main surface on the positive side in the z-axis direction of the dielectric layer 11 is referred to as the front surface, and the main surface on the negative direction side in the z-axis direction of the dielectric layer 11 is referred to as the back surface.

  Here, the dielectric layers 11a and 11b, the dielectric layers 11c and 11d, the dielectric layers 11e and 11f, the dielectric layers 11g and 11h, the dielectric layer 11i, and the dielectric layer 11j are sequentially in the positive direction side in the z-axis direction. Are stacked in this order from the negative direction side to the negative direction side. At this time, the gaps Sp <b> 1 to Sp <b> 4 overlap in a matched state when viewed in plan from the z-axis direction. As a result, the multilayer body 2 has a depth corresponding to the thickness of the dielectric layer 11 of one or more layers (four layers in the present embodiment) from the upper surface S5, as shown in FIG. A groove G that connects the side surfaces S3 and S4 is provided.

  As shown in FIGS. 1 and 2, the internal conductor 3 has a rectangular parallelepiped shape having a longitudinal direction in the y-axis direction, and is provided inside the electronic component 1. More specifically, the inner conductor 3 has a size and shape that fits in the groove G of the multilayer body 2. And the internal conductor 3 is exposed from the laminated body 2 in two places of the mutually opposing side surfaces S3 and S4, as shown in FIG. It is exposed from the laminated body 2 in the upper surface S5 which intersects with. Since the inner conductor 3 has a rectangular parallelepiped shape as described above, the exposed portions of the side surfaces S3 and S4 from the multilayer body 2 are connected in a straight line. That is, the inner conductor 3 linearly crosses the multilayer body 2 in the y-axis direction when viewed from the positive side in the z-axis direction. As a material constituting the inner conductor 3, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Ag, or the like can be used.

  Furthermore, since the groove G of the multilayer body 2 has a depth corresponding to the thickness of one or more dielectric layers 11, the internal conductor 3 has one or more layers (four layers in this embodiment). The dielectric layer 11 penetrates in the z-axis direction.

  The capacitor C1 is composed of capacitor conductors 18a and 20a provided in the multilayer body 2. As shown in FIG. 2, the capacitor conductor 18a has a rectangular shape and is provided on the surface of the dielectric layer 11c. The capacitor conductor 18 a is a conductor layer having a thickness smaller than that of the dielectric layer 11. The long side of the capacitor conductor 18a extends in the y-axis direction, and the short side of the capacitor conductor 18a extends in the x-axis direction. Further, the long side on the negative direction side in the x-axis direction of the capacitor conductor 18a overlaps the long side on the negative direction side in the x-axis direction of the dielectric layer 11c when viewed in plan from the z-axis direction. That is, the capacitor conductor 18 a is exposed on the inner peripheral surface of the groove G and is electrically connected to the inner conductor 3.

  As shown in FIG. 2, the capacitor conductor 20a has a rectangular shape and is provided on the surface of the dielectric layer 11e. The capacitor conductor 20 a is a conductor layer having a thickness smaller than that of the dielectric layer 11. The long side of the capacitor conductor 20a extends in the y-axis direction, and the short side of the capacitor conductor 20a extends in the x-axis direction. Further, the long side on the positive direction side in the x-axis direction of the capacitor conductor 20a overlaps the long side on the positive direction side in the x-axis direction of the dielectric layer 11e when viewed in plan from the z-axis direction. That is, the capacitor conductor 20a is exposed from the multilayer body 2 on the side surface S1.

  The capacitor conductor 18a and the capacitor conductor 20a overlap when viewed in plan from the z-axis direction. That is, the capacitor conductor 18a is opposed to the capacitor conductor 20a with the dielectric layer 11c interposed therebetween. As a result, the capacitor conductors 18a and 20a constitute a capacitor C1 in the overlapping portion.

  In the laminate 2, capacitor conductors 18b and 20b are also provided. The capacitor conductors 18b and 20b are provided on the surfaces of the dielectric layers 11g and 11i, and constitute the capacitor C1 similarly to the capacitor conductors 18a and 20a. A capacitor C1 is also formed between the capacitor conductors 20a and 18b. However, since the configuration of the capacitor conductors 18b and 20b is the same as the configuration of the capacitor conductors 18a and 20a, further description is omitted.

  The capacitor C <b> 2 is configured by capacitor conductors 19 a and 21 a provided in the multilayer body 2. As shown in FIG. 2, the capacitor conductor 19a has a rectangular shape and is provided on the surface of the dielectric layer 11d. The capacitor conductor 19a is provided on the opposite side of the capacitor conductors 18a, 18b, 20a, and 20b with the internal conductor 3 interposed therebetween when viewed from the positive side in the z-axis direction. In the present embodiment, the capacitor conductor 18a and the capacitor 19a have a line-symmetric relationship with respect to a straight line located between the side surface S1 and the side surface S2 when viewed from the positive side in the z-axis direction. . Therefore, further description of the capacitor 19a is omitted.

  As shown in FIG. 2, the capacitor conductor 21a has a rectangular shape and is provided on the surface of the dielectric layer 11f. The capacitor conductor 21a is provided on the opposite side of the capacitor conductors 18a, 18b, 20a, and 20b with the inner conductor 3 interposed therebetween when viewed from the positive side in the z-axis direction. In the present embodiment, the capacitor conductor 20a and the capacitor 21a have a line-symmetric relationship with respect to a straight line located between the side surface S1 and the side surface S2 when viewed from the positive side in the z-axis direction. . Therefore, further description of the capacitor 21a is omitted.

  In the laminated body 2, capacitor conductors 19b and 21b are also provided. The capacitor conductors 19b and 21b are provided on the surfaces of the dielectric layers 11h and 11i, and constitute a capacitor C2 in the same manner as the capacitor conductors 19a and 21a. A capacitor C2 is also formed between the capacitor conductors 21a and 19b. However, since the configuration of the capacitor conductors 19b and 21b is the same as the configuration of the capacitor conductors 19a and 21a, further description is omitted.

  Ni, Cu, Ag, Pd, Ag—Pd alloy, Ag, or the like can be used as the material constituting the capacitor conductors 18 to 21 as described above. The thickness of the capacitor conductors 18 to 21 is preferably 0.3 μm to 2 μm.

  As shown in FIG. 1, the external electrode 5 a is provided so as to cover the side surface S <b> 1 of the multilayer body 2, and is slightly folded back to the side surfaces S <b> 3, S <b> 4, the upper surface S <b> 5, and the lower surface S <b> 6. As described above, the capacitor conductors 20a and 20b are exposed from the multilayer body 2 on the side surface S1. Therefore, the external electrode 5a is electrically connected to the capacitor conductors 20a and 20b.

  As shown in FIG. 1, the external electrode 5 b is provided so as to cover the side surface S <b> 2 of the multilayer body 2, and is slightly folded back to the side surfaces S <b> 3, S <b> 4, the upper surface S <b> 5 and the lower surface S <b> 6. As described above, the capacitor conductors 21a and 21b are exposed from the multilayer body 2 on the side surface S2. Therefore, the external electrode 5b is electrically connected to the capacitor conductors 21a and 21b.

  The external electrode 5 is preferably composed of a base layer and a plating layer formed on the base layer. As a material constituting the base layer, for example, a metal such as Ag, Cu, Ni, Pd, an Ag—Pd alloy, or Au can be used. The thickness (the thickest part) of the underlayer is preferably 10 to 50 μm. As a material constituting the plating layer, for example, Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, or the like can be used. The plating layer may be composed of a plurality of layers, and a two-layer structure of Ni plating and Sn plating is preferable. The thickness per one plating film is preferably 1 μm to 10 μm. Note that a conductive resin layer for stress relaxation may be formed between the base layer and the plating layer.

  The electronic component 1 configured as described above is used by being mounted on a circuit board as described below. FIG. 3 is a plan view of the state in which the electronic component 1 is mounted on the circuit board 300 from the normal direction of the circuit board 300.

  As shown in FIG. 3, the circuit board 300 includes a board body 302 and lands 304 (304 a to 304 d). The board body 302 is a multilayer wiring board and has a circuit therein. The land 304 is an external terminal provided on the main surface of the substrate body 302. Specifically, the lands 304a and 304b are signal terminals for inputting and outputting signal currents. The lands 304c and 304d are ground terminals to which a ground potential is applied.

  The electronic component 1 is mounted on the circuit board 300 such that the upper surface S5 faces the main surface of the circuit board 300. Then, the vicinity of the end portion on the negative direction side in the y-axis direction of the inner conductor 3 is soldered to the land 304a. The vicinity of the end on the positive side in the y-axis direction of the inner conductor 3 is soldered to the land 304b. As a result, the signal current is transmitted between the lands 304 a and 304 b through the internal conductor 3. That is, the inner conductor 3 constitutes a part of the signal path.

  The external electrodes 5a and 5b are soldered to the lands 304c and 304d, respectively. Thereby, the capacitors C1 and C2 are connected between the internal conductor 3 and the ground. Therefore, noise parasitic on the signal current transmitted through the inner conductor 3 is transmitted to the ground side by the capacitors C1 and C2.

(Method for manufacturing electronic parts)
Next, a method for manufacturing the electronic component 1 will be described with reference to the drawings. FIG. 4 is an exploded perspective view of a mother laminate 200 that is an aggregate of the laminates 2. FIG. 5 is an exploded perspective view showing a state in which the groove G is formed in the mother laminated body 200.

  First, a ceramic raw material is weighed at a predetermined ratio and charged into a ball mill, and wet blending is performed. The obtained mixture is dried and pulverized, and the obtained powder is calcined. The obtained calcined powder is wet pulverized by a ball mill, dried and then crushed to obtain a dielectric ceramic powder.

  An organic binder and an organic solvent are added to the dielectric ceramic powder and mixed by a ball mill. The obtained ceramic slurry is formed into a carrier sheet by the doctor blade method and dried to produce a ceramic green sheet 111 to be the dielectric layer 11.

  Next, capacitor conductors 112a, 112b, 113a, 113b are formed on the ceramic green sheet 111 by applying a paste made of a conductive material by a method such as screen printing or photolithography. The capacitor conductors 112a, 112b, 113a, 113b have a rectangular shape. The long sides of the capacitor conductors 112a, 112b, 113a, and 113b extend in the x-axis direction, and the short sides extend in the y-axis direction. The paste made of a conductive material is obtained by adding an organic binder and an organic solvent to metal powder.

  Next, the ceramic green sheets 111a to 111f are laminated and pressure-bonded so as to be arranged in this order from the positive direction side to the negative direction side in the z-axis direction to obtain an unfired mother laminated body 200. Thereafter, the unfired mother laminate 200 is subjected to main pressure bonding in the stacking direction by means such as a hydrostatic pressure press. The mother laminated body 200 is manufactured through the above steps.

  Next, as shown in FIG. 5, using a dicer or the like, a surface on the positive side in the z-axis direction of the mother multilayer body 200 (hereinafter referred to as a main surface) A plurality of grooves G are formed. The groove G is formed at one location for each stacked body 2 and extends in the y-axis direction. The groove G separates the capacitor conductors 112a and 112b formed on the surfaces of the ceramic green sheets 111b and 111d into two rectangular capacitor conductors 18a, 18b, 19a, and 19b, respectively. The capacitor conductor 18a is positioned on the positive side of the groove G in the x-axis direction, and the capacitor conductor 19a is positioned on the negative direction side of the groove G in the x-axis direction. At this time, the groove G is formed so as to cut at least one ceramic green sheet 111. However, the ceramic green sheets 111e and 111f are not cut by the groove G.

  Next, the groove G is filled with a conductive paste for the inner conductor 3. The paste made of a conductive material is obtained by adding an organic binder and an organic solvent to metal powder.

  Next, the mother laminate 200 is cut into a laminate 2 having a predetermined dimension (2.0 mm × 2.0 mm × 0.9 mm) with a dicing saw or the like. Through the above steps, a plurality of unfired laminates 2 are obtained.

  Next, the unfired laminate 2 is fired. The firing temperature is preferably 900 ° C. to 1300 ° C., although it depends on the ceramic and the material of the capacitor conductors 112a, 112b, 113a, and 113b. The fired laminated body 2 is obtained through the above steps. The laminate 2 is chamfered by barrel polishing.

  Next, an electrode paste for the base layer of the external electrode 5 is applied to the side surfaces S <b> 1 and S <b> 2 of the multilayer body 2. The applied electrode paste is baked at 700 ° C. to 900 ° C. for 1 hour to form a base layer.

  The underlayer may be fired simultaneously with the dielectric layer 11 and the capacitor conductors 18 to 21. The underlayer may be formed directly on the laminate 2 by plating, or may be formed by curing a conductive resin including a thermosetting resin.

  Finally, the external electrodes 5a and 5b are formed by plating the surface of the base layer. Through the above steps, the electronic component 1 as shown in FIG. 1 is completed.

(effect)
According to the electronic component 1 as described above, as described below, it is possible to reduce the size and reduce ESR. More specifically, in the electronic component 500 described in Patent Document 1, if the signal internal electrode 502 and the ground internal electrode 503 are thinned in order to reduce the size, the signal internal electrode 502 and the ground internal electrode 503 are disconnected. The area becomes smaller and the ESR becomes larger.

  On the other hand, in the electronic component 1, as described below, the cross-sectional area of the internal conductor 3 that is a signal path can be easily increased without increasing the size of the multilayer body 2. More specifically, in the electronic component 1, the inner conductor 3 passes through at least one dielectric layer 11 in the z-axis direction and is not sandwiched by the dielectric layer 11 from the z-axis direction. Therefore, even if the number of dielectric layers 11 through which the inner conductor 3 penetrates is increased in order to increase the cross-sectional area of the inner conductor 3, the height of the multilayer body 2 in the z-axis direction does not increase. Therefore, in the electronic component 1, the cross-sectional area of the internal conductor 3 can be increased without increasing the size of the multilayer body 2. That is, the electronic component 1 can be reduced in size and ESR can be reduced.

  Further, the inner conductor 3 is exposed from the multilayer body 2 on the upper surface S5. Therefore, as shown in FIG. 3, the inner conductor 3 comes into contact with the lands 304a and 304b on the surface in the positive z-axis direction. Thereby, in the electronic component 1, it becomes easy to contact the internal conductor 3 and the lands 304a and 304b with a large area. As a result, the resistance value between the internal conductor 3 and the lands 304a and 304b can be reduced.

(Modification)
Below, the electronic component 1a which concerns on a 1st modification is demonstrated, referring drawings. FIG. 6 is an external perspective view of the electronic component 1a according to the first modification.

  As shown in FIG. 6, the electronic component 1a further includes external electrodes 7a and 7b. The external electrodes 7a and 7b are provided on the side surfaces S3 and S4 of the multilayer body 2, respectively, and the internal conductor 3 covers portions exposed from the side surfaces S3 and S4 of the multilayer body 2. Thereby, the external electrodes 7a and 7b are connected to both ends of the internal conductor 3 in the y-axis direction, respectively. The external electrodes 7a and 7b are configured by plating on the base layer, and have the same configuration as the external electrodes 5a and 5b.

  Next, an electronic component 1b according to a second modification will be described with reference to the drawings. FIG. 7 is an exploded perspective view of the laminate 2 of the electronic component 1b.

  As shown in FIG. 7, the stacked body 2 further includes a dielectric layer 11k. The dielectric layer 11k is laminated on the positive side of the dielectric layers 11a and 11b and the inner conductor 3 in the z-axis direction. Thereby, the inner conductor 3 is not exposed from the multilayer body 2 on the upper surface S5. As a result, when the electronic component 1b is mounted on the circuit board 300, the internal conductor 3 is prevented from coming into contact with lands other than the lands 304a and 304b and causing a short circuit.

  The inner conductor 3 serves as a signal current transmission path, but it is only necessary to secure an input portion and an output portion for the signal current. That is, the inner conductor 3 may be exposed linearly on the outer surface of the multilayer body 2. Further, the inner conductor 3 does not necessarily have to be exposed from the multilayer body 2 at two positions of the side surfaces S3 and S4. For example, the inner conductor 3 is exposed only on the upper surface S5, and wire bonding or the like is performed on one end and the other end of the inner conductor 3 May be connected to an external circuit. In the present invention, the term “linear” is not limited to a single straight line, and includes a bent line.

  As described above, the present invention is useful for electronic components, and is particularly excellent in that it can be downsized and ESR can be reduced.

C1, C2 Capacitor G Groove S1, S2, S3, S4 Side surface S5, Upper surface S6 Lower surface 1 Electronic component 2 Laminate body 3 Internal conductor 5a, 5b, 7a, 7b External electrode 11a-11j Dielectric layer 18a, 18b, 19a, 19b , 20a, 20b, 21a, 21b Capacitor conductor 200 Mother laminate 300 Circuit board

Claims (5)

A laminate in which a plurality of dielectric layers are laminated;
An inner conductor exposed from the multilayer body at two locations on the side surface and penetrating in one or more dielectric layers in the stacking direction;
A first capacitor conductor provided in the laminate and electrically connected to the inner conductor;
A second capacitor conductor provided in the laminate and constituting a capacitor with the first capacitor conductor;
A first external electrode provided on the side surface and electrically connected to the second capacitor conductor;
Having
Electronic parts characterized by The inner conductor is connected in a straight line to the portion where the inner conductor is exposed from the laminate,
The electronic component according to claim 1. A third capacitor conductor provided in the laminate and electrically connected to the inner conductor;
A fourth capacitor conductor provided in the laminate and constituting a capacitor with the third capacitor conductor;
A second external electrode provided on a side surface of the multilayer body and electrically connected to the fourth capacitor conductor;
Is further provided,
The third capacitor conductor and the fourth capacitor conductor are provided on opposite sides of the first capacitor conductor and the second capacitor conductor with the inner conductor interposed therebetween when viewed in plan from the stacking direction. thing,
The electronic component according to claim 1, wherein: Two third external electrodes connected to each of the portions where the internal conductor is exposed from the laminate,
More
The electronic component according to any one of claims 1 to 3, wherein: A laminate in which a plurality of dielectric layers are laminated;
An inner conductor that is linearly exposed on the outer surface of the multilayer body and penetrates one or more dielectric layers in the stacking direction;
A first capacitor conductor provided in the laminate and electrically connected to the inner conductor;
A second capacitor conductor provided in the laminate and constituting a capacitor with the first capacitor conductor;
A first external electrode provided on the outer surface of the laminate and electrically connected to the second capacitor conductor;
Having
Electronic parts characterized by

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