JP2012022508A - Semiconductor storage device, control device, and method for controlling semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device, a control device, and a method for controlling the semiconductor storage device capable of managing unreadable data without consuming a storage area of a nonvolatile memory.SOLUTION: The semiconductor storage device includes the nonvolatile memory storing data, and a control unit for controlling to write data in the nonvolatile memory and read data from the nonvolatile memory. The control unit includes: a writing control unit which adds an error correction code, which is generated by adding a first flag indicating that the data is valid or invalid to the data and by executing an error correction process, to the data, and writes them in the nonvolatile memory; and a reading control unit which reads out the data and the error correction code from the nonvolatile memory, adds a second flag that is fixed to either of the valid and invalid to the data read out and executes the error correction process using the error correction code read out to the data with the second flag added thereto.

Description

  The present invention relates to a semiconductor memory device, a control device, and a method for controlling a semiconductor memory device.

  In a NAND flash memory controller built in an SSD (Solid State Drive), the basic data transfer size (sector) depends on the convenience of the size of the management table used for internal data management and the ECC code length. In many cases, data management is performed with a larger size.

  When uncorrectable data is generated by ECC (Error Checking and Correction) processing among the data read from the NAND flash memory due to aging degradation of the NAND flash memory, the uncorrectable data is regarded as unreadable data. It is necessary to manage.

  Patent Document 1 describes that in SSD, unreadable data in which an ECC error has occurred in a NAND memory is registered and managed in a management table in units of sectors. In addition, since such management data needs to be made non-volatile, in Patent Document 1, a management table is stored in a NAND memory.

  As described above, in the conventional technique, a management table for managing unreadable data is prepared, and this management table is stored in the NAND memory. Therefore, the storage area of the NAND memory (nonvolatile memory) is stored in the management table. There is a problem of being consumed.

JP 2009-211130 A

  The present invention provides a semiconductor memory device, a control device, and a semiconductor memory device control method capable of managing uncorrectable data without consuming a storage area of a nonvolatile memory.

  According to an aspect of the present invention, the control unit includes: a non-volatile memory that stores data; and a control unit that controls writing of data into the non-volatile memory and reading of data from the non-volatile memory. Adds an error correction code generated by adding a first flag indicating whether the data is valid or invalid to the data and performing error correction processing, and writes the error correction code to the nonvolatile memory. A write control unit, reading the data and the error correction code from the nonvolatile memory, adding a second flag fixed to either valid or invalid to the read data, and reading the data A read control unit for performing error correction processing using the error correction code on the data to which the second flag is added. There is provided.

  According to another aspect of the present invention, there is provided a control device that controls writing of data into a nonvolatile memory and reading of data from the nonvolatile memory, and indicates whether the data is valid or invalid. A write control unit for adding an error correction code generated by adding an error correction process by adding a first flag to the data and writing the data to the nonvolatile memory; and the data and the error correction code. A second flag read from the non-volatile memory and fixed to either valid or invalid is added to the read data, and error correction processing using the read error correction code is performed. There is provided a control device including a read control unit that performs data read with respect to data with 2 flags.

  According to another aspect of the present invention, there is provided a method for controlling a semiconductor memory device having a nonvolatile memory for storing data, wherein the data to be written to the nonvolatile memory is valid or invalid. A first step of generating an error correction code by adding an error flag to the data to be written and performing error correction processing, and adding the error correction code generated in the first step to the data to be written A second step of writing to the non-volatile memory, a third step of reading the data and the error correction code from the non-volatile memory, and a second flag fixed to either valid or invalid Is added to the data read in the third step, and error correction processing using the error correction code read in the third step is performed. The fourth step to be performed on the data to which the flag is added, and when the second flag fixed to valid is detected to be an error, or the second flag fixed to invalid is correct If it is detected that the data to which the second flag has been added is invalid, and the second flag that has been effectively fixed is detected to be correct, or the second flag that has been fixed to invalid is detected. And a fifth step of determining that the data to which the second flag is added is valid when it is detected that the second flag is incorrect. A method for controlling a semiconductor memory device, comprising: Provided.

  According to the present invention, uncorrectable data can be managed without consuming the storage area of the nonvolatile memory.

FIG. 1 is a diagram showing a configuration of the semiconductor memory device 1 according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of the semiconductor memory device 1 according to the first embodiment. FIG. 3 is a diagram illustrating functional blocks formed in the memory 40 according to the first embodiment. FIG. 4 is a diagram for explaining the necessity of managing data that cannot be corrected in units of sectors. FIG. 5 is a diagram illustrating an internal functional configuration example of the L1 / L2 encoder 15 and the L1 decoder 16 according to the first embodiment. FIG. 6 is a diagram illustrating a data configuration according to the first embodiment. FIG. 7 is a flowchart illustrating an operation procedure of the writing process according to the first embodiment. FIG. 8 is a flowchart illustrating the operation procedure of the read process according to the first embodiment. FIG. 9 is a flowchart showing the operation procedure of the read-modify-write process in the first embodiment. FIG. 10 is a diagram illustrating encoding processing in the first ECC processing and the second ECC processing performed on data to which the valid / invalid flag F1 is not added.

A semiconductor memory device according to an embodiment of the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.
(First embodiment)

  FIG. 1 is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment from the hardware side. The semiconductor storage device 1 is connected to the outside of the host device HA via a communication medium and functions as an external storage medium for the host device HA. The host device HA includes, for example, a personal computer or a CPU core. The semiconductor memory device 1 includes, for example, an SSD (Solid State Drive).

  As shown in FIG. 1, the semiconductor memory device 1 includes an MPU (processor) 2, a NAND flash memory (hereinafter abbreviated as a NAND memory) 30 as a nonvolatile semiconductor memory, and a memory capable of operating at higher speed than the NAND memory 30. 40, a communication I / F 60, a NAND controller 10, an L2 decoder 20, and an internal bus 50. The NAND memory 30, the memory 40, the communication I / F 60, the L2 decoder 20 and the MPU 2 are connected to each other via the internal bus 50.

  The NAND memory 30 has a memory cell array in which a plurality of memory cells are arranged in a matrix, and each memory cell can store multiple values using an upper page and a lower page. In the NAND memory 30, data is erased in units of blocks, whereas data is written and read in units of pages. A block is a unit obtained by grouping a plurality of pages. In the NAND memory 30, internal data management by the MPU 2 is performed in units of clusters, and data is updated in units of sectors. In this embodiment, it is assumed that a page is a unit obtained by grouping a plurality of clusters, and a cluster is a unit obtained by grouping a plurality of sectors. The sector is a minimum access unit of data from the host apparatus HA, and has a size of 512B, for example. The host device HA designates data to be accessed by sector unit LBA (Logical Block Addressing).

  As shown in FIG. 3, the memory 40 functions as a cache area 41 for data transfer between the host device HA and the NAND memory 30 and as a work area 42 used by the MPU 2. Examples of the memory 40 include DRAM (Dynamic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Resistive Random Access Memory), PRAM, etc. (P Further, the memory 40 temporarily stores various management tables read from the NAND memory 30 in the work area 42.

  The communication I / F 60 is a memory connection interface such as an ATA interface (ATA I / F), outputs commands and data received from the host device HA to the internal bus 50, and receives data input via the internal bus 50, A response notification from the MPU 2 (such as a notification indicating completion of instruction execution) is transmitted to the host device HA.

  The MPU 2 comprehensively controls each component of the semiconductor memory device 1. When receiving a command from the host device HA via the communication I / F 60 and the internal bus 50, the MPU 2 performs control according to the command. . For example, the MPU 2 cooperates with the NAND controller 10 to control data writing to the NAND memory 30 and data reading from the NAND memory 30 in accordance with instructions from the host device HA. That is, from the functional aspect, one control unit 70 (see FIG. 2) including the MPU 2 and the NAND controller 10 is realized.

  The NAND controller 10 controls data transfer between the NAND memory 30 and the memory 40, and includes an instruction control unit 11, a command control unit 12, a DMA controller 13, a buffer memory 14, an L1 / L2 encoder 15, and an L1 decoder 16. And a memory I / F 17.

  The instruction control unit 11 converts the instruction received from the MPU 2 into a command for the NAND controller 10 and supplies the command to the command control unit 12. The command control unit 12 controls the DMA controller 13, the buffer memory 14, the L1 / L2 encoder, the L1 decoder 16, the L2 decoder 20, and the memory I / F 17 according to the supplied command.

  The DMA controller 13 performs data transfer control among the buffer memory 14, the L2 decoder 20, and the memory 40 in accordance with a DMA (Direct Memory Access) method according to control by the command control unit 12. The buffer memory 14 functions as a buffer area in each of data transfer from the DMA controller 13 to the L1 / L2 encoder 15 and data transfer from the L1 decoder 16 to the DMA controller 13.

  The L1 / L2 encoder 15 performs the encoding process in the ECC process (error correction process) on the data transferred from the DMA controller 13 via the buffer memory 14 according to the control by the command control unit 12, and the encoding result is converted into data. To be output. The L1 / L2 encoder 15 performs an encoding process using the first ECC code (L1, error correction code) and the second ECC code (L2, error correction code). As the first ECC code (L1) and the second ECC code (L2), for example, a Hamming code, BCH (Bose Chaudhuri Hocqchem) code, RS (Reed Solomon) code, LDPC (Low Density Parity Check) code, etc. Is adopted. The correction capability of the second ECC code (L2) is higher than the correction capability of the first ECC code (L1).

  Under the control of the command control unit 12, the L1 decoder 16 decodes the data transferred from the memory I / F 17 in the ECC process using the first ECC code (L1) (error using an error correction code). Correction processing) is performed, and the error-corrected data is output to the buffer memory 14. The memory I / F 17 outputs the data to which the ECC code output from the L1 / L2 encoder 15 is added to the NAND memory 30 and the data to which the ECC code input from the NAND memory 30 is added to the L1 decoder 16. Output.

  The L2 decoder 20 is provided outside the NAND controller 10, and when an uncorrectable error occurs in the decoding process in the ECC process using the first ECC code (L1) of the L1 decoder 16 (an ECC error occurs) Only when activated). The L2 decoder 20 performs a decoding process in the ECC process using the second ECC code (L2) on the data transferred from the DMA controller 13 and cannot be corrected by the L1 decoder 16.

  When writing data to the NAND memory 30, the L1 / L2 encoder 15 has a first error correction code (for example, CRC code) and M-bit correction capability for each sector data with respect to data to be written. ECC code (for example, Hamming code) is generated and added. Also, the L1 / L2 encoder 15 generates and adds a second ECC code (for example, BCH code) having a correction capability of N (N> M) bits to a cluster composed of a plurality of sector data. Data to which the error detection code, the first ECC code, and the second ECC code are added is written into the NAND memory 30 via the memory I / F 17.

  When reading data from the NAND memory 30, the L1 decoder 16 first performs error correction using the first ECC code on the data read from the NAND memory 30, and then uses the error detection code. To detect whether or not an erroneous correction has occurred. When the L2 decoder 20 determines that an error correction has occurred by the L1 decoder 16 (L1-ECC error), that is, an error exceeding the correction capability of the first ECC code has occurred and the error correction has occurred. In this case, error correction is performed using the second ECC code. When error correction using the second ECC code has failed (L2-ECC error), the semiconductor memory device 1 returns a response indicating a read error to the host device HA.

  FIG. 2 is a functional block diagram of the configuration of the semiconductor memory device according to the first embodiment. As shown in FIG. 2, the semiconductor memory device 1 includes a NAND memory 30 that stores data, and a control unit 70 that controls data writing to the NAND memory 30 and data reading from the NAND memory 30. The control unit 70 includes a write control unit 71 that controls writing of data to the NAND memory 30 and a read control unit 72 that controls reading of data from the NAND memory 30. Here, the write control unit 71 includes an MPU 2, an instruction control unit 11, a command control unit 12, a DMA controller 13, a buffer memory 14, a portion related to write processing in the memory I / F 17, an L1 / L2 encoder 15, It corresponds to. The read control unit 72 includes parts related to read processing in the MPU 2, the instruction control unit 11, the command control unit 12, the DMA controller 13, the buffer memory 14, and the memory I / F 17, the L1 decoder 16, and the L2 decoder 20. It corresponds to.

  Next, the necessity of managing the uncorrectable data in which the ECC error has occurred in the sector unit, which is the minimum access unit of the data from the host device HA, will be described with reference to FIG. For example, suppose that a plurality of sectors (sectors LBA = N to N + 7) shown in FIG. 4A are invalid as a result of error correction by the second ECC code. As shown in FIG. 4B, when a part of such a plurality of uncorrectable sectors is updated by a new write request, uncorrectable data and updated valid data (valid) are displayed. A process of creating a new ECC code from the combined data and the combined data and writing the combined data to which the created ECC code is added to a new page is performed. Therefore, thereafter, it becomes possible to correct the error of the combination data including the valid sector and the uncorrectable sector read from the new page by the ECC code added to the combination data. However, since the data other than the updated valid sector may still contain errors and cannot be said to be reliable data, it is necessary to manage that the data other than the updated sector was originally invalid data.

  Conventionally, a management table for managing uncorrectable clusters / sectors is prepared, and this management table is stored in the NAND memory 30, and the storage area of the NAND memory 30 is consumed for the management table. Accordingly, in the semiconductor memory device 1, ECC processing is performed using an invalid flag indicating whether data is valid / invalid, thereby enabling management of sectors that cannot be error-corrected without using a management table. In this type of semiconductor memory device, invalid data often refers to data in which data of the same logical address is written to another location and is no longer referred to. In the document, invalid data has the same meaning as uncorrectable data unless otherwise specified.

  FIG. 5 shows an internal functional configuration example of the L1 / L2 encoder 15 and the L1 decoder 16. The L1 / L2 encoder 15 includes a flag adding unit 15a, an ECC module 15b, and an ECC combining unit 15c.

  The flag adding unit 15a writes a valid / invalid flag (first flag) F1 composed of one to a plurality of bits indicating whether data to be written to the NAND memory 30 is valid or invalid for each sector. The sector data D added to the valid sector data D and the valid / invalid flag F1 added is output to the ECC module 15b. That is, the flag adding unit 15a selects a valid / invalid flag F1 indicating invalid / valid according to a select signal SL from the MPU 2 input via the instruction control unit 11 and the command control unit 12, and a selector 15aa. And an addition unit 15ab for adding the valid / invalid flag F1 output from the data to, for example, the head (or tail) of the sector data D.

  The ECC module 15b performs the first ECC process (error correction process) for each sector data D to which the valid / invalid flag F1 is added, that is, for each flagged data composed of the valid / invalid flag F1 + sector data D. An encoding process is performed to generate a first ECC code (L1) E. That is, as shown in FIG. 6A, the ECC module 15b encodes each of the plurality of sectors of data D1 to Dk to which the valid / invalid flags F11 to F1k are added in the first ECC process (error correction process). Process. Thereby, the ECC module 15b generates first ECC codes (L1) E1 to Ek for each sector data (F11 + D1), (F12 + D2),..., (F1k + Dk) with valid / invalid flags. As shown in FIG. 6A, the ECC module 15b is a data in which a CRC (Cyclic Redundancy Check) code is added to each of the data D1 to Dk to which the valid / invalid flags F11 to F1k are added. The first ECC code (L1) may be generated by performing an encoding process on (valid / invalid flag F1 + data D + CRC).

  The ECC module 15b performs an encoding process in the second ECC process (error correction process) on a cluster composed of a plurality of sector data D1 to Dk to which valid / invalid flags F11 to F1k are added, respectively. Accordingly, the ECC module 15b generates the second ECC code (L2) G1k for the entire sector data with valid / invalid flag (F11 + D1, F12 + D2,..., F1k + Dk) (see FIG. 6A). . As shown in FIG. 6A, the ECC module 15b has a CRC (Cyclic Redundancy Check) code added to each of the data D1 to Dk of the plurality of sectors to which the valid / invalid flags F11 to F1k are added. The second ECC code (L2) may be generated by performing an encoding process on the shape data (F11 + D1 + CRC, F12 + D2 + CRC,..., F1k + Dk + CRC).

  In other words, the L1 / L2 encoder 15 generates the first ECC code (L1) for each sector with valid / invalid flag, and for each cluster with valid / invalid flag that combines a plurality of sectors with valid / invalid flags. A second ECC code (L2) is generated.

  The ECC synthesis unit 15c adds the first ECC code (L1) and the second ECC code (L2) supplied from the L1 / L2 encoder 15 to the data transferred from the DMA controller 13 via the buffer memory 14. Then, ECC-signed data as shown in FIG. 6B is formed, and the formed data is output to the memory I / F 17 to be written in the NAND memory 30. For example, the ECC synthesis unit 15c adds the corresponding first ECC codes (L1) E1 to Ek after the data D1 to Dk of each sector, and the second ECC after the entire data D1 to Dk of the plurality of sectors. The code (L2) G1k is added. However, the valid / invalid flag F1 is used only when encoding the ECC module 15b. As shown in FIG. 6B, the valid / invalid flag field is included in the data written to the NAND memory 30. not exist.

  As shown in FIG. 5, the L1 decoder 16 includes a flag adding unit 16a and an ECC module 16b. The L1 decoder 16 receives the data with the first ECC code (L1) and CRC code read from the NAND memory 30 via the memory I / F 17. Data is temporarily stored in the buffer memory 14, and the CRC is temporarily stored in a CRC buffer (not shown) in the L1 decoder 16.

  The flag adding unit 16a displays a valid flag (second flag that is validly fixed) F2 indicating that it is valid, for example, at the head (for example, the top of the data D of each sector transferred from the memory I / F 17). Or add to the end). The insertion position of the validity flag F2 corresponds to the insertion position of the validity / invalidity flag F1, and when the validity / invalidity flag F1 is added to the beginning of the data, the validity flag F2 is added to the beginning of the data. When the / invalid flag F1 is added to the end of the data, the valid flag F2 is added to the end of the data. That is, the flag adding unit 16a adds the valid flag generating unit 16aa for generating the valid flag F2 and the generated valid flag F2 to the head of the data D, and the valid flag F2, the data D, the first ECC code (L1 And an adding unit 16ab for inputting the CRC to the ECC module 16b.

  The ECC module 16b performs a decoding process in the first ECC process (error correction process) using the first ECC code (L1) on each of the data D1 to Dk of the plurality of sectors to which the valid flag F2 is added. The ECC module 16b notifies the MPU 2 of the presence / absence of error and the corrected position information in the first ECC process according to the result of the decoding process.

  More specifically, the ECC module 16b performs error correction and decoding on the data of each sector to which the valid flag F2 is added using the corresponding first ECC code (L1), and further supports it. It is determined whether or not an error exceeding the correction capability of the first ECC code (L1) has occurred using the error detection code (CRC). That is, the ECC module 16b determines whether the first ECC processing has succeeded or failed for each sector data.

  When the ECC module 16b determines that the first ECC processing is successful (no error), the ECC module 16b notifies the MPU 2 of the determination result and the error bit occurrence position (corrected position information). The MPU 2 determines whether or not the error bit generation position is the bit part of the valid flag F2, and if the MPU 2 detects that the bit part of the valid flag F2 is correct, the sector data D to which the valid flag F2 is added is valid. On the other hand, when it is detected that the bit portion of the valid flag F2 is an error, it is determined that the sector data D to which the valid flag F2 is added is invalid. When the MPU 2 determines that the sector data D to which the valid flag F2 is added is invalid when responding to the read command, the MPU 2 notifies the read error to the host HA. If the ECC module 16b determines that the first ECC processing has failed (there is an error), the ECC module 16b notifies the MPU 2 of the determination result and requests the L2 decoder 20 to be activated.

  When an uncorrectable error has occurred due to the first ECC processing (L1-ECC error), a plurality of sector data constituting a cluster is stored in the L2 decoder 20 arranged outside the NAND controller 10 under the control of the MPU2. D1 to Dk, the second ECC code (L2), and the CRC are transferred via the buffer memory 14, the DMA controller 13, and the internal bus 50.

  As shown in FIG. 5, the L2 decoder 20 includes a flag adding unit 20a and an ECC module 20b. The flag adding unit 20a adds the valid flag F2 fixed to “valid” to all the sector data D1 to Dk constituting the cluster transferred from the memory I / F 17. The ECC module 20b performs a second ECC process (error correction process) using the second ECC code (L2) on the plurality of sector data D1 to Dk and the entire CRCs to which the valid flag F2 is added, respectively. Perform the decoding process.

  More specifically, the ECC module 20b uses the second ECC code (L2) to store a plurality of sector data D1 to Dk, each CRC to which a valid flag (second flag indicating validity) F2 is added. Error correction and decoding are performed on the entire cluster, and an error detection code (CRC) is used to determine whether an error exceeding the correction capability of the second ECC code (L2) has occurred. That is, the ECC module 20b determines whether the second ECC process has succeeded or failed for the cluster including the sector in which the first ECC process has failed.

  When the ECC module 20b determines that the second ECC processing is successful (no error), the ECC module 20b notifies the MPU 2 of the determination result and the error bit occurrence position (corrected position information). The MPU 2 determines whether or not the error bit generation position is the bit part of the valid flag F2, and if the MPU 2 detects that the bit part of the valid flag F2 is correct, the sector data D to which the valid flag F2 is added is valid. On the other hand, when it is detected that the bit portion of the valid flag F2 is an error, it is determined that the sector data D to which the valid flag F2 is added is invalid. When the MPU 2 determines that the sector data D to which the valid flag F2 is added is invalid when responding to the read command, the MPU 2 notifies the read error to the host HA.

  Further, when the ECC module 20b determines that the second ECC processing has failed (there is an error), the ECC module 20b notifies the MPU 2 of the determination result. When the MPU 2 receives the determination result that the second ECC process is unsuccessful (L2-ECC error) when responding to the read command, the MPU 2 notifies the read error to the host HA. Further, the MPU 2 selects invalid as the select signal SL for all the sector data D1 to Dk constituting the cluster in which the second ECC processing has failed, and adds the valid / invalid flag F1 by the L1 / L2 encoder 15 Then, the data is written into the NAND memory 30 via the memory I / F 17.

  When writing data to the NAND memory 30, the MPU 2 determines whether the select signal SL is enabled or disabled for each sector, and the determination result is sent via the instruction control unit 11 and the command control unit 12. To the L1 / L2 encoder 15. When the data input from the host HA is written to the NAND memory 10 in accordance with a write request from the host HA, the select signal SL is selected as valid for the data input from the host HA. That is, when a write occurs from the host HA to a logical address (LBA) that is not used (data is not stored) in the NAND memory 10 or when the entire cluster is updated instead of updating some sectors in the cluster. When writing to the NAND memory 10 for this purpose, valid is selected as the select signal SL.

  In addition, when updating some sectors in the cluster, the data stored in the NAND memory 30 is read, changed, and written back to the NAND memory 30 in the case of read-modify-write (RMW). In this case, it is determined whether each sector of the data read from the NAND memory 30 is valid or invalid based on the decoding results of the L1 decoder 16 and the L2 decoder 20, and the determination result and the change contents to be added Based on this, it is determined whether to select valid or invalid. A sector that is determined to be valid based on the decoding result is selected to be valid by the valid / invalid flag F1, and a sector that is determined to be invalid is valid / invalid flag F1 unless the sector HA has been updated. Use to select invalid. Therefore, at the time of read-modify-write, the validity / invalidity determination result of each sector obtained based on the decoding results of the L1 decoder 16 and the L2 decoder 20 Until the valid / invalid flag F1 is added and stored again in the NAND memory 30, it is temporarily stored in a storage unit such as the memory 40, for example.

  Next, operations related to the ECC processing of the semiconductor memory device 1 will be described with reference to FIGS. FIG. 7 is a flowchart showing the operation of the writing process, FIG. 8 is a flowchart showing the operation of the reading process, and FIG. 9 is a flowchart showing the operation of the RMW (read-modify-write) process.

  First, the operation of the writing process will be described with reference to FIG. First, the MPU 2 determines whether or not the command input from the host HA is a write command (step S1). If the input command is a write command, the LBA included in the write command and management information are determined. For example, by checking the LBA of data already stored in the NAND memory 10 registered in the memory 40, it is determined whether or not the current write requires the above-described read-modify-write (RMW) process. If it is determined (step S2) and it is determined that read-modify-write (RMW) processing is required, RMW processing described in FIG. 9 is executed (step S3).

  When the MPU 2 determines that the current write does not require read-modify-write (RMW) processing, for example, writing to an unused LBA, the MPU 2 reads the write data input from the host HA via the communication I / F 60. The signal is input to the L1 / L2 encoder 15 via the memory 40, the DMA controller 13, and the buffer memory 14, and the select signal SL is set to the effective side. As a result, the flag adding unit 15a of the L1 / L2 encoder 15 adds a valid / invalid flag F1 indicating valid “0000h” for each sector data D of the write data (step S4). Next, the ECC module 15b of the L1 / L2 encoder 15 generates a CRC and a first ECC code (L1) for each sector data D to which a valid / invalid flag F1 indicating valid “0000h” is added. A second ECC code is generated every time (step S5). Next, the ECC combining unit 15c receives the data transferred from the DMA controller 13 via the buffer memory 14, the CRC supplied from the L1 / L2 encoder 15, and the first and second ECC codes (L1, L2). Are merged (see FIG. 6B) and written to the NAND memory 30 via the memory I / F 17 (step S6).

  Next, the read processing operation will be described with reference to FIG. The MPU 2 determines whether or not the command input from the host HA is a read command (step S10). When the MPU 2 determines that the input command is a read command, the MPU 2 controls the NAND controller 10 to execute the read command. Data whose address is specified is read from the NAND memory 30 (step S11). First and second ECC codes (L1, L2) are added to the data read from the NAND memory 30 to the L1 decoder 16.

  The flag adding unit 16a of the L1 decoder 16 adds a valid flag F2 indicating valid “0000h” for each sector to the read data to which the first and second ECC codes (L1, L2) are added (step S12). . The ECC module 16b of the L1 decoder 16 performs error correction decoding processing on each sector data D to which the valid flag F2 is added using the first ECC code (L1) (step S13). Specifically, the ECC module 16b performs error correction and decoding for each sector using the first ECC code (L1), and further uses the error detection code (CRC) to generate the first ECC code (L1). It is determined for each sector whether or not an error exceeding the correction capability is generated (step S14).

  When the ECC module 16b of the L1 decoder 16 determines that the error correction using the first ECC code (L1) has succeeded, the ECC module 16b notifies the MPU 2 of the determination result and the error bit generation position. The MPU 2 determines whether or not the error bit occurrence position is the bit portion of the valid flag F2 (step S16). When the MPU 2 detects that the bit portion of the valid flag F2 is in error, the MPU 2 determines that the sector data D to which the valid flag F2 is added is invalid (step S17), and notifies the read error to the host HA. (Step S18).

  On the other hand, when the MPU 2 detects that the bit portion of the valid flag F2 is correct (NO in step S16), the MPU 2 determines that the sector data D to which the valid flag F2 is added is valid (step S19), The sector data D after error correction by the ECC code (L1) is output to the host HA via the memory 40 (cache area 41) and the communication I / F 60 (step S20).

  On the other hand, if the ECC module 16b determines that error correction using the first ECC code (L1) has failed (NO in step S14), the ECC module 16b requests the MPU 2 to activate the L2 decoder 20. The ECC module 20b of the L2 decoder 20 activated by the MPU 2 uses a second ECC code (L2) to add a plurality of sector data D1 to Dk to which a valid flag (second flag indicating validity) F2 is added. Then, error correction and decoding are performed on the entire cluster including each CRC, and it is further determined whether an error exceeding the correction capability of the second ECC code (L2) has occurred using the error detection code (CRC). (Step S15).

  If the ECC module 20b determines that the error correction using the second ECC code (L2) has succeeded, the ECC module 20b notifies the MPU 2 of the determination result and the error bit occurrence position. The MPU 2 determines whether or not the error bit occurrence position is the bit portion of the valid flag F2 (step S16). When the MPU 2 detects that the bit portion of the valid flag F2 is in error, the MPU 2 determines that the sector data D to which the valid flag F2 is added is invalid (step S17), and notifies the read error to the host HA. (Step S18).

  On the other hand, when the MPU 2 detects that the bit portion of the valid flag F2 is correct (NO in step S16), the MPU 2 determines that the sector data D to which the valid flag F2 is added is valid (step S19). The sector data D after error correction by the ECC code (L1) is output to the host HA via the memory 40 (cache area 41) and the communication I / F 60 (step S20).

  However, when the ECC module 20b of the L2 decoder 20 detects that an error exceeding the correction capability of the second ECC code (L2) has occurred (L2ECC error), the ECC module 20b reports that fact to the MPU2. When the MPU 2 receives the L2-ECC error, the MPU 2 notifies the read error to the host HA. Further, the MPU 2 selects invalid as the select signal SL for all the sector data D1 to Dk constituting the cluster in which the second ECC processing has failed, and adds the valid / invalid flag F1 by the L1 / L2 encoder 15 Then, the data is written into the NAND memory 30 via the memory I / F 17 (step S21).

  Next, the operation of the read-modify-write (RMW) process will be described with reference to FIG. The MPU 2 determines whether or not the current process is an RMW process (step S40). If the MPU 2 determines that the process is an RMW process, the MPU 2 controls the NAND controller 10 to read the corresponding cluster data from the NAND memory 30. (Step S41). The flag adding unit 16a of the L1 decoder 16 adds a valid flag F2 indicating valid “0000h” for each sector to the read data to which the first and second ECC codes (L1, L2) are added (step S42). . The ECC module 16b of the L1 decoder 16 performs error correction decoding processing on each sector data D to which the valid flag F2 is added using the first ECC code (L1) as described above (step S43), and an error detection code. It is determined for each sector whether or not an error exceeding the correction capability of the first ECC code (L1) has occurred using (CRC) (step S44).

  If the ECC module 16b of the L1 decoder 16 determines that error correction is impossible using the first ECC code (L1) (NO in step S44), it requests the MPU2 to activate the L2 decoder 20. . The ECC module 20b of the L2 decoder 20 activated by the MPU 2 uses a second ECC code (L2) to add a plurality of sector data D1 to Dk to which a valid flag (second flag indicating validity) F2 is added. Then, error correction and decoding are performed on the entire cluster including each CRC, and it is further determined whether an error exceeding the correction capability of the second ECC code (L2) has occurred using the error detection code (CRC). (Step S45). When the ECC module 20b of the L2 decoder 20 detects that an error exceeding the correction capability of the second ECC code (L2) has occurred (L2ECC error), the ECC module 20b reports that fact to the MPU2. When the MPU 2 receives the L2-ECC error, the MPU 2 invalidates the determination result in the flag F2 portion corresponding to all the sector data D1 to Dk constituting the cluster in order to invalidate the cluster (Step S1). S53).

  When error correction is possible by either the L1 decoder 16 or the L2 decoder 20, the L1 decoder 16 (or L2 decoder 20) notifies the MPU 2 of the presence / absence of an error and error bit position information. The MPU 2 determines whether or not the bit portion of the valid flag F2 is an error based on the error bit position information (step S46). When the MPU 2 detects that the bit portion of the valid flag F2 is an error, the valid flag F2 Is determined to be invalid (step S47), and when it is detected that the bit portion of the valid flag F2 is correct, it is determined that the sector data D to which the valid flag F2 is added is valid. (Step S48). The flag determination result for each sector in the cluster is temporarily stored as described above.

  Each sector data processed by the L1 decoder 16 (or L2 decoder 20) is written to the work area 42 of the memory 40 via the buffer memory 14 and the DMA controller 13, and is received from the host HA by the work area 42 of the memory 40. The replacement process with the updated data (write data) is executed, and combination data as shown in FIG. 4B is formed (step S49). The MPU 2 effectively changes the flag determination result corresponding to the sector corresponding to the update data received from the host HA among the flag determination results stored temporarily (step S50), and sets the changed flag as the valid / invalid flag F1. Are added to each sector to perform L1 / L2 encoding (step S51). That is, the combination data created in the work area 42 of the memory 40 is input to the L1 / L2 encoder 15 via the DMA controller 13 and the buffer memory 14, and the select signal SL is switched according to the invalidity / validity of each sector. Thus, in the L1 / L2 encoder 15, the valid / invalid flag F1 indicating valid “0000h” or invalid “0001h” is added for each sector data D of the write data, and each sector data to which the valid / invalid flag F1 is further added. A CRC and a first ECC code (L1) are generated for each D, and a second ECC code is generated for each cluster. Then, the generated CRC, the first and second ECC codes (L1, L2) are merged with the data transferred via the buffer memory 14 and written to the NAND memory 30 via the memory I / F 17 (step S52).

  In the present embodiment when the partial update process for the invalid sector portion as shown in FIG. 4 occurs, the RMW operation is as follows. The invalid sector shown in FIG. 4A is detected by the decoding process in the L1 decoder 16 or the L2 decoder 20. That is, error correction becomes impossible during the decoding process in the L1 decoder 16 or the L2 decoder 20, and an L2 ECC error occurs, whereby the MPU2 invalidates (invalidates). As a result, the invalid / invalid flag F1 indicating invalidity is added to the invalid sectors by the L1 / L2 encoder 15 to perform encoding processing, and the encoding results are added to each sector and written to the NAND memory 30. It is.

  In such a state, it is assumed that an update as shown in FIG. 4B occurs in a part of a plurality of consecutive invalid sectors. In such a case, the MPU 2 performs a read / modify / write operation. That is, first, a page or block including a cluster including an update sector is read from the NAND memory 30. The read data is subjected to the above-described decoding process in which the valid flag F2 is added to each read sector by the L1 decoder 16 and the L2 decoder 20, and as a result, the valid flag F2 portion is detected as having an error, Accordingly, the MPU 2 determines that these read sectors are invalid sectors that cannot be corrected for errors.

  The sector determined to be invalid is written into the work area 42 of the memory 40 via the buffer memory 14 and the DMA controller 13, and is combined with the update data received from the host HA in the work area 42 of the memory 40, as shown in FIG. Combination data as shown in (b) is formed. This combination data is transferred from the work area 42 of the memory 40 to the DMA controller 13 and the buffer memory 14.

  The MPU 2 controls the NAND controller 10 to select the invalid flag of the valid / invalid flag F1 for the invalid sector portion in the combination data and to select the valid flag of the valid / invalid flag F1 for the updated sector portion. Commands are given to part 11. As a result, the L1 / L2 encoder 15 creates an ECC code by adding an invalid valid / invalid flag F1 to an invalid sector, and adds an valid valid / invalid flag F1 to an updated sector and adds an ECC code. The created ECC code is added to the corresponding sector and written to a new page or block of the NAND memory 30. Accordingly, when data in which such a valid sector and invalid sector are combined is read, the above-described decoding process is performed by the L1 decoder 16 and the L2 decoder 20 so that each sector is valid or invalid. It is possible to properly determine whether or not.

  FIG. 10 shows that the valid / invalid flag F1 can be added by efficiently using an unused area in the ECC processing unit. In FIG. 10, the L1 / L2 encoder 15 performs the first ECC processing using data obtained by adding an unused area “DR” to the data portion and the CRC portion as a processing unit. Here, the unused area is data that is used in the encoding process and the decoding process, but is not actually written in the NAND memory 30. Note that some data in the unused area may actually be written in the NAND memory 30. Such an unused area may be generated as a fraction when a CRC part other than the data part is included in the ECC processing unit. In the present embodiment, for example, at least some bits of the unused area in such an ECC processing unit can be used as the valid / invalid flag F1. In this case, an unused area in the ECC processing unit that has not been used originally can be used efficiently.

  Each bit in the unused area is decoded, for example, by virtually assigning “0” data. In this case, in this embodiment, the bit representing the valid flag is similarly set to “0” data (“0000h”). As a result, the valid data that has been subjected to ECC processing by setting the valid flag during the encoding process is decoded as usual, and the invalid data that has been subjected to ECC processing by setting the invalid flag during the encoding process is unused. By detecting an error at the flag position in the area, it is possible to determine valid data / invalid data. Therefore, it is possible to efficiently use at least some bits of the unused area in the ECC processing unit as a virtual valid / invalid flag.

  As described above, in the present embodiment, at the time of ECC code generation, in addition to data, a virtual flag for identifying validity / invalidity of data is also included in the processing unit. At the time of writing to the NAND memory 30, the flag used in the ECC calculation is not targeted. At the time of reading from the NAND memory 30, the flag information does not exist because it has not been written, so an ECC operation is performed assuming that a valid flag is provided. If the flag is detected as having an error as an ECC calculation result, it can be treated as invalid data, and if the flag has no error, it can be treated as valid data.

  The ECC code (L1, L2) is generated by adding the valid / invalid flag F1 indicating the validity / invalidity of the sector data to the sector data, so that the ECC code (L1, L2) is generated. Information indicating a value (information indicating validity / invalidity of sector data) can be included. Then, since the ECC code (L1, L2) generated in this way is added to the sector data and written to the NAND memory 30, the storage area of the NAND memory 30 is determined by information for managing the validity / invalidity of the sector data. It can be prevented from being consumed. Here, ECC encoding processing is performed with a set of data + additional information, but only the data or only a part of the data + additional information is treated as a write target for the NAND memory 30, and the additional information deleted at the time of reading. Is complemented with a value prepared in advance to perform ECC decoding processing.

  Also, data including a plurality of sets of sector data and ECC codes is read from the NAND memory, and a valid flag F2 that is effectively fixed is added to each read sector data and read (the value of the flag F1 is changed). ECC processing using an ECC code (including information indicating the above) is performed on the sector data to which the valid flag F2 is added. As a result, it is possible to detect whether the validity flag F2 is an error and to estimate the value of the validity / invalidity flag F1 added during the encoding process. That is, when it is detected by ECC processing that the valid flag F2 is incorrect, it can be determined that the sector data to which the valid flag F2 is added is invalid. Further, when it is detected by the ECC process that the valid flag F2 is correct, it can be determined that the sector data to which the valid flag F2 is added is valid.

  Therefore, according to the first embodiment, the validity / invalidity of the sector data can be managed without consuming the storage area of the NAND memory 30. For example, it is not necessary to create a bad cluster table and a sector bitmap indicating the validity / invalidity of each sector constituting a cluster registered in the bad cluster table.

  In this embodiment, the two-stage ECC processing (L1, L2) is performed, but only one of the first ECC processing (L1) and the second ECC processing (L2) is performed. It may be. Alternatively, an error correction code may be generated in a format different from the first ECC process and the second ECC process, and three or more stages of ECC processes may be performed.

  In the above embodiment, the valid flag is employed as the flag F2 used in the L1 decoder 16 and the L2 decoder 20, but an invalid flag may be employed. In this case, if the MPU 2 detects that the bit portion of the invalid flag (second flag fixed to invalid) F2 is erroneous by the ECC process, the sector data D to which the invalid flag F2 is added is valid. Is determined. When the MPU 2 detects that the bit portion of the invalid flag F2 is correct by the ECC processing, the MPU 2 determines that the sector data D to which the invalid flag F2 is added is invalid.

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 MPU, 10 NAND controller, 11 Command control part, 12 Command control part, 13 DMA controller, 14 Buffer memory, 15 L1 / L2 encoder, 15a Flag addition part, 15aa selector, 15ab addition part, 15b ECC Module, 15c ECC synthesis unit, 16 L1 decoder, 16a flag addition unit, 16aa valid flag generation unit, 16ab addition unit, 16b ECC module, 17 memory I / F, 20 L2 decoder, 20a flag addition unit, 20b ECC module, 30 NAND memory, 40 memory, 41 cache area, 42 work area, 50 internal bus, 60 communication I / F, 70 control unit, 71 write control unit, 72 read control Control, F1, F11-F1k valid / invalid flag, F2 valid flag

Claims (7)

Non-volatile memory for storing data;
A control unit that controls writing of data to the nonvolatile memory and reading of data from the nonvolatile memory;
With
The controller is
Write control for adding an error correction code generated by adding a first flag indicating whether the data is valid or invalid to the data and performing error correction processing to the data and writing to the nonvolatile memory And
The data and the error correction code are read from the nonvolatile memory, a second flag fixed to either valid or invalid is added to the read data, and the read error correction code A read control unit that performs error correction processing on the data with the second flag added thereto;
A semiconductor memory device comprising: The read control unit detects that the second flag effectively fixed by the error correction process is an error, or detects that the second flag fixed invalid by the error correction process is correct If it is determined that the data to which the second flag has been added is invalid and it is detected that the second flag, which is effectively fixed by error correction processing, is correct, or invalidated by error correction processing. When it is detected that the fixed second flag is an error, it is determined that the data with the second flag added is valid;
The write control unit adds the first flag indicating invalidity to data determined to be invalid by the read control unit, and sets the data determined to be valid by the read control unit. 2. The semiconductor memory device according to claim 1, wherein the first flag indicating validity is added. The write control unit, when writing data input from a host device into the nonvolatile memory, adds the first flag indicating that the data is valid for the write data. Semiconductor memory device. A control device for controlling writing of data to a nonvolatile memory and reading of data from the nonvolatile memory,
Write control for adding an error correction code generated by adding a first flag indicating whether the data is valid or invalid to the data and performing error correction processing to the data and writing to the nonvolatile memory And
The data and the error correction code are read from the nonvolatile memory, a second flag fixed to either valid or invalid is added to the read data, and the read error correction code A read control unit that performs error correction processing on the data with the second flag added thereto;
A control device comprising: The read control unit detects that the second flag effectively fixed by the error correction process is an error, or detects that the second flag fixed invalid by the error correction process is correct If it is determined that the data to which the second flag has been added is invalid and it is detected that the second flag, which is effectively fixed by error correction processing, is correct, or invalidated by error correction processing. When it is detected that the fixed second flag is an error, it is determined that the data with the second flag added is valid;
The write control unit adds the first flag indicating invalidity to data determined to be invalid by the read control unit, and sets the data determined to be valid by the read control unit. The control device according to claim 4, wherein the first flag indicating that it is valid is added. The write control unit, when writing data input from a host device to the nonvolatile memory, adds the first flag indicating that the data is valid for the write data. Control device. A method for controlling a semiconductor memory device having a nonvolatile memory for storing data,
A first step of generating an error correction code by performing error correction processing by adding a first flag indicating whether data to be written to the nonvolatile memory is valid or invalid to the data to be written; ,
A second step of adding the error correction code generated in the first step to the data to be written and writing to the nonvolatile memory;
A third step of reading the data and the error correction code from the nonvolatile memory;
Error correction using the error correction code read in the third step by adding a second flag fixed to either valid or invalid to the data read in the third step A fourth step of performing processing on the data to which the second flag is added;
When it is detected that the second flag fixed to valid is an error, or when the second flag fixed to invalid is detected to be correct, the data to which the second flag is added is When it is determined that the second flag fixed to be valid is correct, or when the second flag fixed to be invalid is detected to be erroneous, the second flag is determined to be invalid. A fifth step of determining that the data to which the flag is added is valid;
A method of controlling a semiconductor memory device, comprising:

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