JP2012009774A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for improving crystal orientation of a ferroelectric layer in a ferroelectric capacitor.SOLUTION: The semiconductor device manufacturing method comprises the steps of forming a buffer layer 44 on a lower electrode layer 41, performing first heat treatment on the buffer layer 44 under an atmosphere of an oxygen concentration lower than 100 vol% and at a first temperature, and subsequently performing second heat treatment at a second temperature higher than the first temperature, forming a dielectric layer 42 on the buffer layer 44, forming an upper electrode layer 43 on the dielectric layer 42 and crystallizing the dielectric layer 42 by heat treatment.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, attention has been focused on nonvolatile memories that retain stored information even when the power is turned off.

  Among the nonvolatile memories, there is a ferroelectric memory (Ferroelectric Random Access Memory: FeRAM) as a memory that operates at a low voltage and can perform writing and reading at high speed.

  The ferroelectric memory has a ferroelectric capacitor including a ferroelectric film as a capacitive element. A ferroelectric capacitor is formed by sandwiching a ferroelectric film as a capacitive insulating film between a pair of electrodes. In the ferroelectric memory, information is stored using the hysteresis characteristic of the ferroelectric film.

  This ferroelectric film generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization of the ferroelectric film is also reversed. Therefore, the stored information can be read by detecting this spontaneous polarization. Further, since polarization is a phenomenon caused by displacement of atoms of the ferroelectric film, reading / writing of the ferroelectric memory is performed at a very high speed.

  As electronic devices equipped with a memory have higher functions, performances such as higher speed and lower power consumption are required for the nonvolatile memory.

  In response to such a demand, miniaturization of the ferroelectric capacitor is required in order to miniaturize the ferroelectric memory. By reducing the thickness of the ferroelectric capacitor, the polarization inversion voltage can be lowered.

  However, there are cases where the polarization characteristics before thinning cannot be maintained even if the ferroelectric capacitor is thinned while the electric field strength applied to the ferroelectric film is kept constant. One reason for this is considered that the lattice mismatch existing at the interface between the ferroelectric film and the lower electrode reduces the crystallinity of the thinned ferroelectric film.

  Accordingly, it has been proposed to improve the crystal orientation of the ferroelectric film by disposing a buffer layer between the ferroelectric film and the lower electrode.

For example, disposing strontium ruthenate (SrRuO ₃ ) as a buffer layer between a lead zirconate titanate compound (PZT) that is a ferroelectric film and platinum that is a lower electrode is disclosed. . Specifically, a strontium ruthenate film containing Ru in excess of 2-3% is formed on the lower electrode with a thickness of 2 nm or less. Then, the strontium ruthenate film is subjected to crystallization treatment by rapid heating annealing treatment at a temperature of 600 ° C. for 30 seconds in an atmosphere having an oxygen concentration of 100% by volume. A body film and an upper electrode are formed in order. The ferroelectric film is crystallized by heat treatment to improve the degree of orientation of the (111) plane of the lead zirconate titanate compound.

  However, in this method of forming a ferroelectric capacitor, excess Ru element forms an interface state at the interface between the ferroelectric film and the lower electrode, and thus there is a possibility that the leakage current increases. In addition, there is a problem that the polarization characteristics of the ferroelectric capacitor formed by this method have a large variation and an insufficient degree of (111) plane orientation.

  Another method for forming a ferroelectric capacitor has been proposed. First, a first layer of strontium ruthenate film is formed on the lower electrode in an oxygen atmosphere by sputtering, and then a second layer of strontium ruthenate film is formed in an oxygen atmosphere having a lower oxygen concentration. Is done. It is disclosed that a strontium ruthenate film is crystallized by rapid thermal annealing.

  However, in this method of forming a ferroelectric capacitor, since the strontium ruthenate film is formed in a low oxygen concentration atmosphere by sputtering, the stability of the quality of the strontium ruthenate film is deteriorated. Therefore, the crystal orientation degree of the ferroelectric film formed on the strontium ruthenate film that is the buffer layer becomes non-uniform, and the performance of the ferroelectric capacitor may not be stabilized.

JP 2007-119892 A

  An object of the present specification is to provide a method of manufacturing a semiconductor device that improves the crystallinity of a dielectric layer in a dielectric capacitor.

  In order to solve the above problems, according to one embodiment of a method for manufacturing a semiconductor device disclosed in this specification, a step of forming a buffer layer on a lower electrode layer, and 100% by volume with respect to the buffer layer Performing a second heat treatment at a second temperature higher than the first temperature after the first heat treatment is performed at a first temperature in an atmosphere having an oxygen concentration lower than the concentration; and the buffer layer A step of forming a dielectric layer thereon, a step of forming an upper electrode layer on the dielectric layer, and a step of crystallizing the dielectric layer by heat treatment.

  According to one embodiment of the semiconductor device manufacturing method described above, the crystallinity of the dielectric layer in the dielectric capacitor is improved.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

It is a figure showing one embodiment of a semiconductor device indicated to this specification. It is a figure which shows the manufacturing process (the 1) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 2) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 3) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 4) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 5) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 6) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 7) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the manufacturing process (the 8) by one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the relationship between XRD peak intensity | strength and 1st temperature of 1st heat processing. It is a figure which shows the relationship between XRD peak intensity | strength and the oxygen concentration of 1st heat processing. It is a figure which shows the relationship between the XRD peak intensity | strength and the process time of 1st heat processing. It is a figure which shows the relationship between XRD peak intensity | strength and 2nd temperature of 2nd heat processing. It is a figure which shows the relationship between XRD peak intensity | strength and the oxygen concentration of 2nd heat processing. It is a figure which shows the relationship between XRD peak intensity and 2nd heat processing. It is a figure which shows the relationship between XRD peak intensity | strength and 1st temperature of 1st heat processing. It is a figure which shows the relationship between XRD peak intensity | strength and the thickness of a buffer layer. It is a figure which shows the relationship between a XRD peak intensity | strength and the film thickness of a buffer layer.

  Hereinafter, preferred embodiments of a semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating an embodiment of a semiconductor device disclosed in this specification.

  A semiconductor device 1 according to an embodiment disclosed in this specification (hereinafter, also simply referred to as this embodiment) includes a ferroelectric memory having a ferroelectric capacitor Q as a capacitive element. The ferroelectric memory has a basic structure in which a MOS transistor and a ferroelectric capacitor Q are connected in series. As shown in FIG. 1, this ferroelectric memory has a planar structure in which a conductive plug 60b is formed on the contact region CR of the lower electrode 41a of the ferroelectric capacitor Q.

  As shown in FIG. 1, a semiconductor device 1 includes, for example, a transistor layer in which MOS transistors TR1 and TR2 are disposed, a capacitor layer formed on the transistor layer and in which a ferroelectric capacitor Q is disposed, and a capacitor layer. And a wiring layer on which the wiring is arranged.

  In the transistor layer, a p-type Si well 22 defined by an element isolation insulating film 21 is formed on the single crystal silicon substrate 20. Then, n-channel MOS transistors TR1 and TR2 are arranged at an interval in the Si well 22 region.

  MOS transistors TR1 and TR2 have gate insulating films 28 corresponding to the respective channel regions.

  On the gate insulating film 28, n-type doped polycrystalline silicon gate electrodes 25a and 25b are arranged. The gate electrodes 25a and 25b form part of the word line of the ferroelectric memory.

  Insulating sidewalls 26 are disposed on both side walls of the gate electrodes 25a and 25b. Further, n-type first to third source / drain regions 23 a, 23 b, and 23 c are disposed outside the sidewalls 26.

  As shown in FIG. 1, in the MOS transistor TR1, the first source / drain extension region 24a extends from the end of the first source / drain region 23a toward the gate insulating film 28. Similarly, in the MOS transistor TR2, the third source / drain extension region 24c extends from the end of the third source / drain region 23c toward the gate insulating film 28. In addition, second source / drain extension regions 24b are disposed on both sides of the second source / drain region 23b.

  As shown in FIG. 1, silicide layers 27 are disposed on the first to third source / drain regions 23a, 23b, and 23c, respectively. A similar silicide layer 27 is also disposed on the gate electrodes 25a and 25b.

  A first conductive plug 32 a that connects the first source / drain region 23 a and the upper layer is disposed on the first source / drain region 23 a via the silicide layer 27. Similarly, the second conductive plug 32b is disposed on the second source / drain region 23b, and the third conductive plug 32c is disposed on the third source / drain region 23c.

  As shown in FIG. 1, a cover film 29 is disposed on the silicon substrate 20 so as to cover the two MOS transistors TR1 and TR2. Further, the first insulating layer 30 is disposed on the cover film 29.

  In the capacitor layer disposed on the transistor layer, an alumina film 37 used for enhancing the crystallinity of the ferroelectric capacitor Q is disposed on the first insulating layer 30.

  As shown in FIG. 1, the ferroelectric capacitor Q is disposed on the alumina film 37. The ferroelectric capacitor Q includes a lower electrode 41a, a ferroelectric film 42a formed on the lower electrode 41a, and an upper electrode 43a formed on the ferroelectric film 42a.

The material for forming the dielectric film 42a, a lead zirconate titanate _{Pb (Zr x, Ti 1-} x) O 3 (0 ≦ x ≦ 1), or a _{Pb (Zr x, Ti 1-} x) O Ca relative to _{3, Sr, La, Nb,} Ta, it is preferable to use a compound in which at least one element is added which is selected from the group consisting of Ir and W.

  Thus, when lead zirconate titanate is used as the material for forming the dielectric film 42a, the dielectric film 42a has the maximum polarization value when the (001) plane is oriented. On the other hand, from the viewpoint of the productivity of the ferroelectric capacitor, it is easier to align than the (001) plane, and the switching direction forms an angle of 45 ° with respect to the inversion electric field and a relatively large polarization value. It is more preferable to orient the (111) plane from which is obtained.

  In the semiconductor device 1, a buffer film 44a is disposed between the lower electrode 41a and the ferroelectric film 42a in the ferroelectric capacitor Q. The buffer film 44a has a function of increasing the degree of (111) plane orientation when the ferroelectric film 42a is crystallized on the buffer film by heat treatment. The function of the buffer film 44a will be described in detail in the description of the method for manufacturing the semiconductor device 1 described later.

  Further, the first protective layer 10a is disposed on the upper electrode 43a of the ferroelectric capacitor Q. The first protective film 10 a prevents hydrogen from passing through the upper electrode 43 a and moving to the ferroelectric film 42 a during the formation of the semiconductor device 1.

  A second protective layer 50 that protects the ferroelectric capacitor Q from a reducing atmosphere such as hydrogen during the manufacture of the semiconductor device 1 is disposed on the alumina film 37 so as to cover the ferroelectric capacitor Q.

  A fourth conductive plug 60a for connecting the upper electrode 43a and the upper layer is disposed on the upper electrode 43a. The fourth conductive plug 60a penetrates the first protective layer 10a and the second protective layer 50 and is connected to the upper electrode 43a.

  Further, on the contact region CR of the lower electrode 41a, a fifth conductive plug 60b for connecting the lower electrode 41a and the upper layer wiring is disposed. The fifth conductive plug 60b penetrates the second protective layer 50 and is connected to the upper electrode 43a.

  Further, as shown in FIG. 1, a sixth conductive plug 60c that connects the lower first conductive plug 32a and the upper wiring is disposed on the first conductive plug 32a. The sixth conductive plug 60c penetrates the alumina film 37 and is connected to the first conductive plug 32a. Similarly, the seventh conductive plug 60d is disposed on the second conductive plug 32b, and the eighth conductive plug 60e is disposed on the third conductive plug 32c.

  Further, as shown in FIG. 1, the second insulating layer 51 is disposed on the second protective layer 50 so as to embed the ferroelectric capacitor Q therein.

  In the wiring layer disposed on the capacitor layer, a wiring 62b for connecting the fourth conductive plug 60a and the eighth conductive plug 60e is disposed. The wiring 62b connects the third source / drain region 23c of the MOS transistor TR2 and the upper electrode 43a of the dielectric capacitor Q through a plurality of plugs.

  Similarly, a wiring 62c connected to the fifth conductive plug 60b is disposed on the second insulating layer 51. The wiring 62c forms part of the planar line of the ferroelectric memory.

  Further, on the second insulating layer 51, a wiring 62a connected to the sixth conductive plug 60c is disposed.

  Further, a conductive pad 62d connected to the seventh conductive plug 60d is disposed on the second insulating layer 51. A ninth conductive plug 60f that connects the conductive pad 62d and the upper layer is disposed on the conductive pad 62d.

  Further, as shown in FIG. 1, the third insulating layer 63 is disposed on the second insulating layer 51 so as to embed each wiring or the like. On the third insulating layer 63, another wiring layer or the like may be arranged as necessary.

  Next, an embodiment of a method for manufacturing the semiconductor device 1 having the ferroelectric memory shown in FIG. 1 will be described below with reference to FIGS.

  First, as shown in FIG. 2, a transistor layer having MOS transistors TR <b> 1 and TR <b> 2 is formed on the silicon substrate 20. Then, an alumina film 37 is formed on the first insulating layer 30 in which the MOS transistors TR1 and TR2 are embedded. As a method for forming the alumina film 37, for example, an RF magnetron sputtering method can be used.

  Hereinafter, each step of forming the ferroelectric capacitor Q, which is a capacitive element, on the alumina film 37 in a portion surrounded by a square frame in FIG. 2 will be described.

  As shown in FIG. 3, the lower electrode layer 41 is formed on the alumina film 37. As a method for forming the lower electrode layer 41, for example, a sputtering method is used. Specifically, a DC magnetron sputtering method can be used as the sputtering method. The thickness of the lower electrode layer 41 can be appropriately set depending on the design of the ferroelectric capacitor, and can be set to, for example, 50 nm. As a material for forming the lower electrode layer 41, for example, platinum can be used. When platinum is used as the lower electrode layer 41, platinum has self-orientation, but the formation condition of the lower electrode layer may be set to promote the degree of (111) plane orientation of platinum. This is preferable from the viewpoint of increasing the (111) plane orientation height of the formed buffer layer and ferroelectric layer.

  Next, as shown in FIG. 4, a buffer layer 44 is formed on the lower electrode layer 41. As a method for forming the buffer layer 44, for example, a sputtering method is used. Specifically, a DC magnetron sputtering method can be used as the sputtering method. The temperature of the stage on which the silicon substrate 20 is placed at the time of sputtering can be set to 20 ° C. to 150 ° C., preferably 60 ° C., for example. The power used for sputtering can be set as appropriate depending on the design of the ferroelectric capacitor, and can be, for example, 30 W to 350 W, preferably 310 W. Moreover, it is preferable to use an atmosphere that does not contain oxygen as the atmosphere during sputtering. As this atmosphere, an inert gas such as argon gas can be used. Here, when an atmosphere containing oxygen is used as the atmosphere at the time of sputtering, the sputtering rate may decrease, and the uniformity of the specific resistance distribution in the buffer layer surface may decrease. When the distribution of specific resistance in the buffer layer surface becomes non-uniform in this way, the degree of orientation of the (111) plane of the ferroelectric layer formed on the buffer layer decreases, and the polarization characteristics of the ferroelectric capacitor deteriorate. There is a fear.

The thickness of the buffer layer 44 can be set as appropriate depending on the design of the ferroelectric capacitor, and can be set to 1 to 2 nm, for example. Examples of the material for forming the buffer layer 44 include strontium ruthenate (SrRuO ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), titanium oxide (TiO ₂ ), or barium lead oxide (BaPbO). ₃ ) can be used. In particular, the material for forming the buffer layer 44 is preferably a material having high lattice matching with the ferroelectric layer formed thereon.

  Thus, the buffer layer 44 formed on the lower electrode layer 41 is normally in an amorphous state.

  Then, the first heat treatment is performed on the buffer layer 44 in an atmosphere having an oxygen concentration lower than the concentration of 100% by volume and at a first temperature. By this first heat treatment, the crystallization of the buffer layer 44 in the amorphous state proceeds. At this time, the buffer layer 44 is crystallized according to the crystal plane of the exposed surface of the lower electrode layer 44. That is, if the exposed surface of the lower electrode layer 44 is the (111) plane, the buffer layer 44 also has the same crystal plane as the (111) plane of the lower electrode layer 44 and crystallization proceeds.

  The first temperature is preferably 600 ° C. or higher from the viewpoint of promoting crystallization of the buffer layer 44. The upper limit of the first temperature is preferably set to a temperature that does not cause defects or the like in the silicon substrate 20 on which the transistor layer is formed. As an upper limit of 1st temperature, it can be set as 1000 degrees C or less, or 900 degrees C or less, or 800 degrees C or less, or 650 degrees C or less, for example.

  In addition, the oxygen concentration in the first heat treatment is preferably higher than 0% by volume and 50% by volume or less, particularly preferably higher than 0% by volume and 10% by volume or less from the viewpoint of promoting the crystallization of the buffer layer 44. .

  The reason why it is preferable to set the oxygen concentration in the first heat treatment within the above-described range will be described below, taking as an example the case where strontium ruthenate as the buffer layer 44 is formed on platinum as the lower electrode layer 41. . Ruthenium that forms strontium ruthenate is more easily bonded to oxygen than strontium. Therefore, when the oxygen concentration when the buffer layer 44 is formed is low, ruthenium first bonds to oxygen, and the ruthenium oxide crystal nucleus. Is formed on the (111) plane of platinum which is the lower electrode layer 41. Then, it is considered that the (111) plane of strontium ruthenate grows preferentially on the (111) plane of platinum based on the ruthenium oxide crystal nucleus formed on the (111) plane of platinum. On the other hand, when the oxygen concentration when the buffer layer 44 is formed is high, it is considered that strontium is oxidized together with the oxidation of ruthenium, and further, the surface of platinum as the lower electrode layer 41 is also oxidized. Therefore, it is considered that the growth of strontium ruthenate according to the platinum (111) plane is inhibited, and the growth of strontium ruthenate having a random plane orientation occurs. Thus, the ferroelectric film formed on strontium ruthenate having a random plane orientation has a low degree of crystal orientation and a low polarization value. Further, when the buffer layer 44 is formed in an atmosphere not containing oxygen, ruthenium oxide is not formed in an atmosphere not containing oxygen, so that strontium ruthenate is formed with a random orientation on platinum. Conceivable.

  The first heat treatment described above is preferably a rapid heating annealing process. The reason for this will be described below with reference to an example in which strontium ruthenate as the buffer layer 44 is formed on platinum as the lower electrode layer 41. When strontium ruthenate, which is the buffer layer 44, is rapidly heated at a first temperature of 600 ° C. or higher, the strontium ruthenate grows preferentially in the (111) plane and grows in other crystal planes. Is suppressed. On the other hand, when strontium ruthenate that is the buffer layer 44 is heated at a slower heating rate, the growth of crystal planes other than the (111) plane increases and the growth of the (111) plane decreases. Therefore, it is preferable that the first heat treatment is a rapid heating annealing process with a high temperature rising rate. The temperature increase rate of the rapid thermal annealing process of the first heat treatment can be set to 125 ° C./second, for example.

  It is considered that a large number of crystal nuclei in accordance with at least the plane orientation of the lower electrode layer 41 are formed in the buffer layer 44 in the amorphous state by the first heat treatment described above. Then, a large number of crystal nuclei formed by the first heat treatment are bonded while growing each of the discrete crystal nuclei by the second heat treatment described below, and the entire buffer layer 44 becomes the lower electrode layer. It is considered that the crystal state follows the plane orientation of 41.

  Then, following the first heat treatment, the second heat treatment is performed on the buffer layer 44 at a second temperature higher than the first temperature. The second temperature is preferably 700 ° C. or higher in order to increase the degree of crystal orientation of the entire buffer layer 44. The upper limit of the second temperature is preferably set to a temperature that does not cause defects or the like in the silicon substrate 20 on which the transistor layer or the like is formed. As an upper limit of 2nd temperature, it can be 1000 degrees C or less, or 900 degrees C or less, or 800 degrees C or less, or 750 degrees C or less, for example.

  In addition, it is preferable that the second heat treatment is performed in an atmosphere containing oxygen from the same viewpoint as described in the first heat treatment. Specifically, the oxygen concentration in the second heat treatment is preferably 2.5% by volume or more, particularly 100% by volume.

  For the same reason as the first heat treatment described above, the second heat treatment is also preferably a rapid heating annealing treatment. The temperature increase rate of the rapid thermal annealing process of the second heat treatment can be set to 125 ° C./second, for example.

Next, as shown in FIG. 5, the first dielectric layer 42 b is formed on the buffer layer 44. As a method for forming the first ferroelectric layer 42b, for example, a sputtering method is used. Specifically, an RF magnetron sputtering method can be used as the sputtering method. The temperature of the stage on which the silicon substrate 20 is placed at the time of sputtering can be set to 20 ° C. to 150 ° C., preferably 50 ° C., for example. The power used for sputtering can be set as appropriate depending on the design of the ferroelectric capacitor, and can be set to 1.0 kW, for example. Moreover, as an atmosphere at the time of sputtering, for example, argon gas can be used. Specifically, argon gas may be flowed at a flow rate of 20 × 1.667 × 10 ⁻⁸ m ³ / sec (20 sccm), and the pressure may be set to 1 Pa. The thickness of the first ferroelectric layer 42b can be set as appropriate depending on the design of the ferroelectric capacitor, and can be set to 55 nm, for example. As a target forming material, for example, the composition is Pb: 1.13 / Zr: 0.45 / Ti: 0.55 / O: 3 / La: 0.02 / Sr: 0.025 / Ca: 0.05 It is possible to use lead zirconate titanate.

  Then, the structure in which the first ferroelectric layer 42b is stacked on the buffer layer 44 is subjected to rapid thermal annealing in an oxygen-containing atmosphere, and the first ferroelectric layer 42b is crystallized. The first ferroelectric layer 42 b is crystallized according to the plane orientation of the buffer layer 44 on the buffer layer 44 having a specific plane orientation degree. As conditions for this rapid thermal annealing treatment, for example, a substrate temperature of 582 ° C., an oxygen concentration of 1.25% by volume, a treatment time of 90 seconds, and a temperature rising rate of 125 ° C./second can be used.

  Next, as shown in FIG. 6, the second dielectric layer 42 c is formed on the buffer layer 44. The second dielectric layer 42c can be formed in the same manner as the first dielectric layer 42b described above. For example, the second dielectric layer 42c is formed using lead zirconate titanate using an RF magnetron sputtering method. The thickness of the second dielectric layer 42c can be set as appropriate depending on the design of the ferroelectric capacitor, and can be set to 15 nm, for example.

  Next, as shown in FIG. 7, the upper electrode layer 43 is formed on the second ferroelectric layer 42c. As a method for forming the upper electrode layer 43, for example, a sputtering method is used. Specifically, a DC magnetron sputtering method can be used as the sputtering method. The thickness of the upper electrode layer 43 can be appropriately set depending on the design of the ferroelectric capacitor, and can be set to, for example, 50 nm. As a material for forming the upper electrode layer 43, for example, a noble metal such as platinum, or a conductive oxide such as iridium oxide or ruthenium oxide can be used.

  Next, as shown in FIG. 8, together with the first ferroelectric layer 42b and the second ferroelectric layer 42c, the upper electrode layer 43 is crystallized by heat treatment, so that the first ferroelectric layer 42b and the second ferroelectric layer 42b are crystallized. The ferroelectric layer 42 is formed by crystallizing the dielectric layer 42c. In this heat treatment, the second ferroelectric layer 42c on the first ferroelectric layer 42b is crystallized according to the plane orientation of the first ferroelectric layer 42b. As a condition for this heat treatment, for example, a rapid heating annealing process in which the temperature is 717 ° C., the oxygen concentration is 1% by volume, and the treatment time is 120 seconds can be used.

  Next, as shown in FIG. 9, the first protective layer 10 is formed on the upper electrode layer 42. As a material for forming the first protective layer, iridium oxide, platinum, ruthenium oxide, or titanium aluminum nitride can be used. Further, the first protective layer 10 may be formed of two layers 10b and 10c as shown in FIG.

  Then, using a technique such as lithography, the lower electrode layer 41 to the lower electrode 41a, the buffer layer 44 to the buffer film 44a, the ferroelectric layer 42 to the ferroelectric film 42a, and the upper electrode layer 43 to the upper electrode 43a However, the first protective film 10 a is formed from the first protective layer 10. In this way, the ferroelectric capacitor Q shown in FIG. 1 is obtained. Further, each layer, each conductive plug, and wiring are formed on the silicon substrate 20 on which the ferroelectric capacitor Q is formed, and the semiconductor device 1 shown in FIG. 1 is obtained.

  According to the semiconductor device manufacturing method described above, the degree of crystal orientation of the ferroelectric film in the ferroelectric capacitor is improved. Specifically, the orientation of the surface of the lower electrostrictive layer 41 can be accurately transmitted to the first ferroelectric layer 42a and the second ferroelectric layer 42b via the buffer layer 44 to be crystallized. . For example, if the lower electrode layer 41 has a (111) plane, the first ferroelectric layer 42a and the second ferroelectric layer 42b can also be formed in a crystal having a high degree of (111) plane orientation. Therefore, since the polarization value of the ferroelectric film can be improved, the thickness of the ferroelectric film can be reduced without reducing the polarization value of the ferroelectric film.

  Next, by measuring the X-ray diffraction (XRD) peak intensity of the ferroelectric layer after the first heat treatment or the second heat treatment of the buffer layer in the semiconductor device manufacturing process described above, The relationship with the plane orientation degree of the dielectric layer will be described below.

  FIG. 10 is a diagram showing the relationship between the XRD peak intensity and the first temperature of the first heat treatment.

  FIG. 10 shows the relationship between the XRD peak intensity and the first temperature of the first heat treatment for four samples. Each of the four samples is different in the first temperature of the first heat treatment. Specifically, the first temperatures were 550 ° C., 600 ° C., 642 ° C., and 717 ° C. The lower electrode forming material of the four samples was platinum, the buffer layer was strontium ruthenate, and the ferroelectric layer was lead zirconate titanate. Here, each of the four samples was subjected to the rapid thermal annealing treatment in the first heat treatment with an oxygen concentration of 2.5% by volume and a treatment time of 1 minute. In the four samples, the XRD peak intensity was measured for the state after the second heat treatment was not performed, the upper electrode layer 43 was formed, and the ferroelectric layer 42 was crystallized. . The measurement of the XRD peak intensity was performed on the (111) plane and the (101) plane of lead zirconate titanate. Note that the (101) plane of lead zirconate titanate mainly means a random orientation state.

  As shown in FIG. 10, the higher the first temperature, the higher the (111) plane orientation degree of the ferroelectric layer. At any temperature, the (111) plane orientation degree of the ferroelectric layer is higher than the (101) plane orientation degree. Further, the lower the first temperature, the higher the (101) plane orientation degree of the ferroelectric layer. Here, it is considered that the (111) plane orientation degree of the ferroelectric layer corresponds to the height of the (111) plane orientation degree of the lower buffer layer.

  From this result, it is considered that the (111) plane orientation degree of the buffer layer increases as the first temperature of the first heat treatment increases.

  FIG. 11 is a diagram showing the relationship between the XRD peak intensity and the oxygen concentration of the first heat treatment.

  FIG. 11 shows the relationship between the XRD peak intensity and the oxygen concentration of the first heat treatment for five samples. Each of the five samples has a different oxygen concentration in the first heat treatment. Specifically, the oxygen concentration was 2.5% by volume, 5% by volume, 10% by volume, 50% by volume, and 100% by volume. Here, each of the five samples was subjected to the rapid thermal annealing treatment in the first heat treatment at a first temperature of 600 ° C. and a treatment time of 1 minute. For other manufacturing conditions, the five samples were processed in the same manner as the sample shown in FIG.

  As shown in FIG. 11, a high (111) orientation degree of the ferroelectric layer was obtained when the oxygen concentration was in the range of 2.5% to 10% by volume. In particular, the highest (111) plane orientation degree was obtained at an oxygen concentration of 5% by volume. At any oxygen concentration, the (111) plane orientation degree of the ferroelectric layer is higher than the (101) plane orientation degree. The (101) plane orientation degree of the ferroelectric layer tends to be slightly higher in the range of 50% by volume or more than in the range of 2.5% by volume to 10% by volume.

  From this result, it is considered that the (111) plane orientation degree of the buffer layer is high when the oxygen concentration is in the range of 2.5 volume% to 10 volume%.

  FIG. 12 is a diagram showing the relationship between the XRD peak intensity and the processing time of the first heat treatment.

  FIG. 12 shows the relationship between the XRD peak intensity and the processing time of the first heat treatment for two samples. Specifically, the processing time of the first heat treatment was 1 minute and 2 minutes. Here, each of the two samples was subjected to a rapid thermal annealing process in the first heat treatment at a first temperature of 600 ° C. and an oxygen concentration of 2.5% by volume. For other manufacturing conditions, the two samples were processed in the same manner as the sample shown in FIG.

  As shown in FIG. 12, when the processing time was 1 minute and 2 minutes, the same (111) plane orientation degree and (101) plane orientation degree of the ferroelectric layer were obtained. In any processing time, the (111) plane orientation degree of the ferroelectric layer is higher than the (101) plane orientation degree.

  From this result, it is considered that the degree of orientation of the (111) plane of the buffer layer is little changed when the processing time is between 1 minute and 2 minutes.

  FIG. 13 is a diagram showing the relationship between the XRD peak intensity and the second heat treatment temperature.

  FIG. 13 shows the relationship between the XRD peak intensity and the second temperature of the second heat treatment for two samples. Specifically, the second temperatures were 717 ° C. and 732 ° C. Here, each of the two samples was subjected to the rapid thermal annealing treatment in the first heat treatment with the first temperature being 600 ° C., the oxygen concentration being 2.5% by volume, and the treatment time being 1 minute. Thereafter, each of the two samples was subjected to a rapid thermal annealing treatment in the second heat treatment with an oxygen concentration of 100% by volume and a treatment time of 2 minutes. For other manufacturing conditions, the two samples were processed in the same manner as the sample shown in FIG.

  As shown in FIG. 13, when the second temperatures were 717 ° C. and 732 ° C., substantially the same (111) plane orientation degree of the ferroelectric layer was obtained. At any temperature, the (111) plane orientation degree of the ferroelectric layer is higher than the (101) plane orientation degree.

  From this result, it is considered that the (111) plane orientation degree of the buffer layer hardly changes when the second temperature of the second heat treatment is in the range of 717 ° C. to 732 ° C.

  FIG. 14 is a diagram showing the relationship between the XRD peak intensity and the oxygen concentration of the second heat treatment.

  FIG. 14 shows the relationship between the XRD peak intensity and the oxygen concentration of the second heat treatment for two samples. Specifically, the oxygen concentration was 2.5% by volume and 100% by volume. Here, in each of the two samples, in the first heat treatment, the first temperature was 600 ° C., the oxygen concentration was 2.5% by volume, the treatment time was 1 minute, and after the rapid heating annealing treatment, In the heat treatment of No. 2, rapid heating annealing was performed at a second temperature of 717 ° C. and a processing time of 2 minutes. For other manufacturing conditions, the two samples were processed in the same manner as the sample shown in FIG.

  As shown in FIG. 14, when the oxygen concentration in the second heat treatment was 2.5% by volume and 100% by volume, almost the same (111) plane orientation degree of the ferroelectric layer was obtained. At any temperature, the (111) plane orientation degree of the ferroelectric layer is higher than the (101) plane orientation degree. When the oxygen concentration in the second heat treatment was 2.5% by volume, the (101) plane orientation degree of the ferroelectric layer was a value below the lower limit of measurement.

  From this result, it is considered that the (111) plane orientation degree of the buffer layer hardly changes when the oxygen concentration in the second heat treatment is in the range of 2.5 vol% to 100 vol%.

  FIG. 15 is a diagram showing the relationship between the XRD peak intensity and the second heat treatment.

  FIG. 15 shows a comparison of XRD peak intensities when only the first heat treatment is performed and when the first heat treatment and the second heat treatment are performed. Here, in the first heat treatment, each sample was subjected to a rapid heating annealing treatment with a first temperature of 600 degrees, an oxygen concentration of 2.5 vol%, and a treatment time of 1 minute. In the second heat treatment, the rapid thermal annealing treatment was performed with an oxygen concentration of 2.5% by volume and a treatment time of 2 minutes. For other manufacturing conditions, each sample was processed in the same manner as the sample shown in FIG.

  As shown in FIG. 15, it can be seen that the (111) plane orientation degree of the ferroelectric layer is significantly improved by performing the second heat treatment. On the other hand, the (101) plane orientation degree of the ferroelectric layer decreases by performing the second heat treatment.

  From this result, the (111) plane orientation degree of the buffer layer is the second heat treatment at a second temperature higher than the first temperature after the first heat treatment is performed on the buffer layer at the first temperature. It is thought that it will improve greatly by being performed.

  FIG. 16 is a diagram showing the relationship between the XRD peak intensity and the first temperature of the first heat treatment.

  FIG. 16 shows the measurement results of the XRD peak intensity for the sample subjected to the second heat treatment after the first heat treatment at the first temperature of 550 ° C., 600 ° C., and 717 ° C. Here, in the first heat treatment, each sample was subjected to rapid thermal annealing treatment with an oxygen concentration of 2.5% by volume and a treatment time of 1 minute. In the second heat treatment, the rapid heating annealing process was performed at a second temperature of 717 ° C., an oxygen concentration of 100% by volume, and a treatment time of 2 minutes. For other manufacturing conditions, each sample was processed in the same manner as the sample shown in FIG.

  As shown in FIG. 16, the higher the first temperature, the higher the (111) plane orientation degree of the ferroelectric layer. However, if the first temperature is 600 ° C. or higher, the (111) plane of the ferroelectric layer becomes higher. ) The degree of plane orientation is almost constant.

  From this result, it is considered that the (111) plane orientation degree of the buffer layer is substantially constant when the first temperature is 600 ° C. or higher.

  Further, from the viewpoint of reducing the time of the high temperature heat treatment while securing the (111) plane orientation degree of the high ferroelectric layer, it is considered preferable to set the temperature of the first heat treatment to about 600 ° C.

  Next, the relationship between the thickness of the buffer layer and the (111) plane orientation degree of the ferroelectric layer will be described below.

  FIG. 17 is a diagram showing the relationship between the XRD peak intensity of the ferroelectric layer and the thickness of the buffer layer. Here, the buffer layer was strontium ruthenate, and the ferroelectric layer was lead zirconate titanate.

  As shown in FIG. 17, when the buffer layer is thick, the (111) plane orientation degree of the ferroelectric layer is lower than when the buffer layer is thin. On the other hand, the (101) plane orientation degree of the ferroelectric layer is slightly higher when the buffer layer is thicker than when it is thin.

  In view of this, a method for improving the degree of orientation of the (111) plane of the ferroelectric layer even when the buffer layer is thick was studied.

  Specifically, a thin buffer layer (for example, a film thickness of 1 nm) is formed on the lower electrode layer, and the first buffer layer is formed in an atmosphere having an oxygen concentration lower than a concentration of 100% by volume with respect to the buffer layer. A first heat treatment is performed at a temperature. Thereafter, the formation of a thin buffer layer (for example, the film thickness is 1 nm) and the first heat treatment are repeated to form a thick buffer layer on the lower electrode layer. Then, a second heat treatment is performed on the thick buffer layer.

  FIG. 18 is a diagram showing the relationship between the XRD peak intensity of the ferroelectric layer and the film thickness of the buffer layer. FIG. 18 shows the (111) plane orientation degree of the ferroelectric layer formed on the thick buffer layer formed by repeating the formation of the thin buffer layer (for example, the film thickness is 1 nm) and the first heat treatment. The relationship with the film thickness of the buffer layer is shown. Here, the buffer layer was strontium ruthenate, and the ferroelectric layer was lead zirconate titanate.

  As shown in FIG. 18, when the thick buffer layer is formed by repeating the formation of the thin buffer layer and the first heat treatment, the strength of the buffer layer shown in FIG. The (111) plane orientation degree of the dielectric layer is obtained. This is because each thin buffer layer is sufficiently crystallized by the formation of the thin buffer layer and the first heat treatment, so that the crystallinity of the thick buffer layer formed by stacking the thin buffer layers is increased. This is probably because of this.

  In the present invention, the semiconductor device and the manufacturing method thereof according to the above-described embodiments can be appropriately changed without departing from the spirit of the present invention. For example, in the above-described embodiment, the capacitive element is a ferroelectric capacitor having a ferroelectric film. However, the capacitive element may be a dielectric capacitor having a dielectric that is not a ferroelectric.

  In the above-described embodiment, the semiconductor device includes the ferroelectric memory having the ferroelectric capacitor. However, if the semiconductor device includes the capacitor having the above-described structure, the semiconductor device is not a ferroelectric memory. May be.

  In the above-described embodiment, the ferroelectric capacitor is a planar type, but the ferroelectric capacitor may be a stack type.

  In the above-described embodiment, the n-channel MOS transistor is included. However, a p-channel MOS transistor or another switching element may be included.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  Regarding the above-described embodiment, the following additional notes are disclosed.

(Appendix 1)
Forming a buffer layer on the lower electrode layer;
After the first heat treatment is performed on the buffer layer in an atmosphere having an oxygen concentration lower than 100% by volume and at a first temperature, a second temperature higher than the first temperature is used. Performing the heat treatment of 2;
Forming a dielectric layer on the buffer layer;
Forming an upper electrode layer on the dielectric layer;
Heat treating the dielectric layer to crystallize;
A method for manufacturing a semiconductor device comprising:

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, wherein the first temperature is 600 ° C. or higher.

(Appendix 3)
The semiconductor device manufacturing method according to Appendix 2, wherein the second temperature is 700 ° C. or higher.

(Appendix 4)
4. The method of manufacturing a semiconductor device according to claim 1, wherein an oxygen concentration of the first heat treatment is higher than 0% by volume and 10% by volume or lower.

(Appendix 5)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein the second heat treatment is performed in an atmosphere containing oxygen.

(Appendix 6)
The method for manufacturing a semiconductor device according to appendix 5, wherein the oxygen concentration in the second heat treatment is 2.5% by volume or more.

(Appendix 7)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the first heat treatment or the second heat treatment is a rapid heating annealing treatment.

(Appendix 8)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 7, wherein a material for forming the buffer layer is strontium ruthenate, strontium titanate, lead titanate, titanium oxide, or barium lead oxide.

(Appendix 9)
A material for forming the dielectric layer is Pb (Zr _x , Ti _1-x ) O ₃ (0 ≦ x ≦ 1), or Ca, Sr, Pb (Zr _x , Ti _1-x ) O ₃ . The method for manufacturing a semiconductor device according to any one of appendices 1 to 8, wherein the semiconductor device is a compound to which at least one element selected from the group consisting of La, Nb, Ta, Ir, and W is added.

(Appendix 10)
The manufacturing of the semiconductor device according to any one of appendices 1 to 9, wherein in the step of forming the buffer layer, the buffer layer is formed on the lower electrode layer in an atmosphere not containing oxygen using a sputtering method. Method.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 1st protective layer 10a 1st protective film 20 Silicon substrate 21 Element isolation insulating film 22 P well 23a 1st source / drain region 23b 2nd source / drain region 23c 3rd source / drain region 24a 1st source / drain Drain extension region 24b Second source / drain extension region 25a Gate electrode 25b Gate electrode 26 Side wall 27 Silicide layer 28 Gate insulating film 29 Cover film 30 First insulating layer 32a First conductive plug 32b Second conductive plug 32c Third Conductive plug 37 Alumina film 41 Lower electrode layer 41a Lower electrode 42 Ferroelectric layer 42a Ferroelectric film 42b First ferroelectric layer 42c Second ferroelectric layer 43 Upper electrode layer 43a Upper electrode 44 Buffer layer 44a Buffer film 50 second Protective layer 51 2nd insulating layer 54 2nd interlayer insulating film 54a 1st hole 60a 4th conductive plug 60b 5th conductive plug 60c 6th conductive plug 60d 7th conductive plug 60e 8th conductive plug 60f 9th Conductive plug 62a wiring 62b wiring 62c wiring 62d conductive pad 63 third insulating layer CR contact region Q ferroelectric capacitor (capacitance element)

Claims (5)

Forming a buffer layer on the lower electrode layer;
After the first heat treatment is performed on the buffer layer in an atmosphere having an oxygen concentration lower than 100% by volume and at a first temperature, a second temperature higher than the first temperature is used. Performing the heat treatment of 2;
Forming a dielectric layer on the buffer layer;
Forming an upper electrode layer on the dielectric layer;
Heat treating the dielectric layer to crystallize;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the first temperature is 600 ° C. or higher.   The method for manufacturing a semiconductor device according to claim 2, wherein the second temperature is 700 ° C. or higher.   The method for manufacturing a semiconductor device according to claim 1, wherein an oxygen concentration in the first heat treatment is higher than 0 volume% and equal to or lower than 10 volume%.   The method for manufacturing a semiconductor device according to claim 1, wherein the second heat treatment is performed in an oxygen atmosphere having an oxygen concentration of 2.5% by volume or more.

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