JP2012005170A - Storage device and charging control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suggest a storage device and a charging control method with high reliability capable of certainly performing data guarantee to a power failure while suppressing heating of a battery.SOLUTION: After power recovery from the power failure, all data amounts of data stored in a volatile memory in a cache memory part are acquired, an electric power amount required for performing backup of all the pieces of data stored in the volatile memory from the volatile memory to a non-volatile storage medium in the cache memory is calculated, the battery is rapidly charged until the power of the electric power amount is charged to the battery, and after charging the power of the electric power amount is charged to the battery, low-speed charging of the battery is performed with charging current lower than that in the rapid charging.

Description

  The present invention relates to a storage apparatus and a charging control method, and is particularly suitable for application to a storage apparatus equipped with a backup function during a power failure that saves data stored in a cache memory to a nonvolatile storage medium when a power failure occurs. .

  Conventionally, in a storage apparatus, a storage area provided by a storage device such as a hard disk apparatus is presented to the host apparatus, and data is read from or written to the storage area in response to a request from the host apparatus. In such a storage apparatus, for the purpose of improving the access speed for frequently used data, data read / written to / from the storage device is temporarily stored in a cache memory including a volatile memory. ing.

  Incidentally, data storage is the most important performance in a storage device. In the event of a power outage or the like, it is natural to protect the data, and data loss also leads to social problems. In view of these circumstances, in recent years, when a power failure occurs, power is supplied to the cache memory, etc. by the battery, and the data stored in the cache memory is backed up (backed up) to the nonvolatile memory, etc. The storage device with the function is commercialized.

  In this case, in order to perform “reliable backup” by the backup function at the time of power failure as described above, it is necessary that the battery always stores the amount of power necessary for such backup. It is necessary to charge the required amount of power as soon as possible in preparation for a power failure after power is restored after the amount is used or after the amount of power storage is reduced due to spontaneous discharge.

  In Patent Document 1 below, for example, as a battery charging method used in a video camera, rapid charging is performed with a charging current at a predetermined rate until full charging, and then slow charging with a pulsed charging current at the same predetermined rate is performed. Is disclosed.

JP-A-6-90531

  However, a nickel metal hydride (Ni-MH) battery widely used as a backup battery for storage products has a characteristic that heat generation increases when the battery is fully charged, and further heat generation occurs when the battery is charged beyond the full charge.

  The heat generated by the battery not only causes deterioration of the battery but also reduces the reliability of the battery. Furthermore, since the heat radiated from the battery is diffused in the storage product, the reliability of the storage apparatus is also lowered. Therefore, it is desirable to reduce the heat generation amount of the battery as much as possible.

  In this case, the amount of heat generation increases as the charging current increases. Therefore, it is desirable to charge with a current as low as possible in order to suppress heat generation. However, if the battery is charged with a constant current, the charging time becomes long, and there is an inappropriate problem as a charging method for a storage apparatus that requires rapid charging as described above.

  On the other hand, the performance of storage products is compared by storage capacity and data rate. We want to improve performance as long as size and price are allowed. Therefore, it is necessary to configure a battery or the like that is not directly evaluated as performance as simple as possible.

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose a highly reliable storage apparatus and charge control method capable of reliably guaranteeing data against power failure while suppressing heat generation of the battery.

  In order to solve this problem, in the present invention, a storage device unit having one or a plurality of storage devices, a cache memory unit for temporarily storing data to be read and written in a storage area provided by the storage device, and the storage device In a storage device having a control unit that controls reading and writing of data to and from a battery power supply unit that supplies driving power to the cache memory unit in the event of a power failure, the cache memory unit reads and writes to a storage area provided by the storage device A volatile memory for temporarily storing data, a non-volatile storage medium for temporarily backing up the data stored in the volatile memory, and reading and writing of data to and from the volatile memory; The data stored in the volatile memory is The battery power supply unit includes a battery and a charge / discharge control unit that controls charging / discharging of the battery, and the charge / discharge control unit is configured to recover power after a power failure. , Obtaining the total amount of data stored in the volatile memory notified from the memory controller, and calculating the amount of power required to back up all the data from the volatile memory to the nonvolatile storage medium. The battery is rapidly charged until the battery is charged with the amount of power, and after the battery is charged with the amount of power, the battery is charged at a low speed with a charging current lower than that during the quick charge. It is characterized by doing.

  In the present invention, a storage device unit having one or more storage devices, a cache memory unit for temporarily storing data to be read / written in a storage area provided by the storage device, and reading / writing data from / to the storage device In a charging control method in a storage device having a control unit to control and a battery power supply unit that supplies driving power to the cache memory unit in the event of a power failure, the cache memory unit reads and writes data in a storage area provided by the storage device A volatile memory for temporarily storing data, a non-volatile storage medium for temporarily backing up the data stored in the volatile memory, and controlling the reading and writing of data to and from the volatile memory. If necessary, the data stored in the volatile memory The battery power supply unit includes a battery and a charge / discharge control unit that controls charge / discharge of the battery, and the charge / discharge control is performed after power is restored from a power failure. A first step of acquiring a total data amount of data stored in the volatile memory notified from the memory controller; and all data stored in the volatile memory by the charge / discharge control unit. A second step of obtaining the amount of power required to back up the volatile memory from the volatile memory to the non-volatile storage medium, and until the charge / discharge control unit charges the battery with the amount of power. A third step of charging the battery at a low speed with a charging current lower than that at the time of the rapid charging after the battery is rapidly charged and charging the battery with the amount of power; Characterized in that it comprises.

  According to the present invention, while the amount of power stored in the battery is small and the backup of data in the cache memory unit cannot be ensured to a short period by rapid charging, the amount of heat generated by the battery is reduced by low-speed charging near the full charge where the heat generation amount is large. Can be suppressed. Accordingly, it is possible to realize a highly reliable storage apparatus and charge control method capable of reliably guaranteeing data against power failure while suppressing heat generation of the battery.

It is a block diagram which shows schematic structure of the storage apparatus by this Embodiment. It is a block diagram which shows the detailed structure of a cache memory part. It is a block diagram which shows the detailed structure of a battery power supply part. It is a flowchart with which it uses for description of the process of CPU of a battery power supply part regarding collection of the total data amount of the data stored in the cache memory part. (A)-(D) are the graph and waveform diagram with which it uses for description of a charge control process. It is a conceptual diagram which shows the structure of the required electric energy conversion table at the time of backup. It is a flowchart which shows the process sequence of a 1st charge control process. It is a flowchart which shows the process sequence of a 2nd charge control process. It is a flowchart which shows the process sequence of a write performance restriction | limiting process.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Configuration of Storage Device According to this Embodiment In FIG. 1, reference numeral 1 denotes a storage device according to this embodiment as a whole. The storage device includes a storage device unit 2 that provides a storage area, a control unit 3 that controls reading and writing of data to the storage device unit 2 in response to a request from a host device (not shown), a storage device unit 2, and a control unit 3. And a power supply unit 4 for supplying driving power to the apparatus.

  The storage device unit 2 includes one or more storage devices 10 and a DC / DC converter 11.

  The storage device 10 includes, for example, an expensive disk such as a SCSI (Small Computer System Interface) disk or an inexpensive disk such as a SATA (Serial AT Attachment) disk or an optical disk. One or more logical volumes (hereinafter referred to as logical volumes) are set on a physical storage area provided by one or more storage devices 10. Data from the host device is stored in this logical volume in units of blocks or files of a predetermined size.

  Each logical volume is given a unique identifier (hereinafter referred to as LUN (Logical Unit number)). In the case of this embodiment, the input / output of data to / from a logical volume is performed by combining this LUN and a unique number (LBA: Logical Block Address) assigned to each logical block as an address. This is done by designating the address and data length.

  The DC / DC converter 11 boosts or reduces the drive voltage supplied from the power supply unit 4 to a predetermined voltage, and supplies the drive voltage of the predetermined voltage thus obtained to each storage device 10.

  On the other hand, the control unit 3 includes information processing resources such as the controller 12 and the cache memory unit 13, and DC / DC converters 14 and 15 provided corresponding to the controller 12 and the cache memory unit 13, respectively. .

  The controller 12 is a processor that controls the operation of the entire storage apparatus 1, and includes a local memory (not shown) for storing various control programs therein. When the controller 12 executes various control programs stored in the local memory, various control processes such as data read / write control with respect to the storage device 10 of the storage device unit 2 are performed. The cache memory unit 13 is mainly used for temporarily storing data to be read from and written to the logical volume (storage device 10) in response to an access request from the host device.

  FIG. 2 shows a detailed configuration of the cache memory unit 13. As shown in FIG. 2, the cache memory unit 13 includes a plurality of volatile memories 30, a memory controller 31, and a data backup unit 32. The memory controller 31 communicates with the controller 12 (FIG. 1) and the charge / discharge control unit 20 (FIG. 1) of the battery power supply unit 17 (FIG. 1) described later, in addition to the function of reading / writing data from / to each volatile memory 30. A communication function is provided. The data backup unit 32 is composed of a nonvolatile memory such as a flash memory, for example, and is used for saving data stored in the volatile memory when a power failure occurs.

  The DC / DC converters 14 and 15 have functions similar to those of the DC / DC converter 11 of the storage device unit 2, and each of the DC / DC converters 14 and 15 is obtained by increasing or decreasing the drive voltage supplied from the power supply unit 4 to a predetermined voltage. A drive voltage of a predetermined voltage is supplied to the corresponding controller 12 and the cache memory unit 13.

  The power supply unit 4 includes an AC / DC converter 16 and a battery power supply unit 17. The AC / DC converter 16 converts an AC voltage of 100 [V] obtained from the commercial AC power supply 18 into a predetermined DC voltage, and the DC voltage thus obtained is converted to the DC / DC converter 11 of the storage device unit 2. The DC / DC converters 14 and 15 of the control unit 3 and the charge / discharge control unit 20 (FIG. 1) of the battery power supply unit 17 are supplied.

  The battery power supply unit 17 includes a battery unit 19 including a plurality of batteries, and a charge / discharge control unit 20 that controls charging / discharging of the battery unit 19.

  FIG. 3 shows a detailed configuration of the battery unit 19 and the charge / discharge control unit 20. The battery unit 19 is connected between a power supply line LN1 to which a DC voltage is applied from the power supply unit 4 (FIG. 1) via a power input / output terminal (not shown) of the battery power supply unit 17 and a ground line LN2. And a plurality of batteries 40 and a discharge current monitoring resistor R1, a battery voltage sensor 41, a battery temperature sensor 42, and a discharge current sensor 43.

  The battery 40 is composed of, for example, a nickel metal hydride battery. The battery voltage sensor 41 detects the output voltage of the battery unit 19 at the midpoint of connection between the power supply line LN1 and the battery unit 19, and transmits the detection result to the CPU 55 of the charge / discharge control unit 20 described later as a battery voltage detection signal.

  The battery temperature sensor 42 detects the temperature of the battery 40 and transmits the detection result to the CPU 55 of the charge / discharge control unit 20 as a battery temperature detection signal. Further, the discharge current sensor 43 detects the current value of the discharge current output from the battery unit 19 when a power failure occurs, and transmits the detection result to the CPU 55 of the charge / discharge control unit 20 as a discharge current detection signal.

  The charge / discharge control unit 20 includes an input circuit 50, a charge circuit 51, a discharge circuit 53, an auxiliary power supply unit 54 and a CPU (Central Processing Unit) 55.

  The input circuit 50 includes an inrush current prevention circuit 60 inserted on the power supply line LN1, first and second voltage dividing resistors R2 and R3 connected in series between the power supply line LN1 and the ground line LN2, and a power failure detection. Voltage sensor 61.

  The inrush current prevention circuit 60 is driven based on the inrush current prevention command signal given from the CPU 55 and suppresses the inrush current input when the storage apparatus 1 is powered on. The power failure detection voltage sensor 61 detects the voltage at the midpoint of connection between the first and second voltage dividing resistors R2 and R3, and transmits the detection result to the CPU 55 as a voltage detection signal.

  The charging circuit 51 includes a booster unit 70 and a constant current unit 71. The step-up unit 70 includes a step-up circuit 81 including first and second capacitors C1 and C2, a first coil L1, a diode D1, and a MOS-type FET (Metal Oxide Semiconductor Field Effect Transistor) 80; Voltage dividing resistors R4 and R5, and a boost control circuit 82.

  The first and second capacitors C1 and C2 constituting the booster circuit 81 are respectively connected between the power supply line LN1 and the ground line LN2, and the first coil L1 and the first diode D1 are connected to the first power line LN1. The first and second capacitors C1 and C2 are inserted in series. The MOS FET 80 has a drain connected to the connection midpoint of the first coil L1 and the first diode D1 in the power supply line LN1, a source connected to the ground line LN2, and a gate connected to the boost control circuit 82. Has been.

  The step-up control circuit 82 includes first and second voltage dividing resistors R4 and R5 connected in series between the connection midpoint of the first diode D1 and the second capacitor C2 in the power supply line LN1 and the ground line LN2. Monitor the voltage at the midpoint of the connection. Based on the charge command signal from the CPU 55, the boost control circuit 82 adjusts the voltage at the connection midpoint of the first and second voltage dividing resistors R3 and R4 to a predetermined voltage as necessary. The first MOS type FET 82 is turned on / off at a high frequency. As a result, the output voltage of the input circuit 50 is boosted in the booster 70. Specifically, when the signal level of the charge instruction signal is a logic “1” level, the boost control circuit 82 turns on the MOS FET 80 (on / off at a high frequency), and the signal level of the discharge command signal is a logic “0”. "Level, the MOS FET 80 is turned off.

  The constant current unit 71 includes a second coil L2, a current detection resistor R6, second and third diodes D2 and D3, a constant current circuit 84 including a MOS FET 83, and a constant current control circuit 85. The second coil L2, the current detection resistor R6, and the third diode D3 are connected in series in this order and inserted in the power supply line LN1. The MOS FET 83 has a drain connected to the connection midpoint of the first diode D1 and the second capacitor C2 of the booster circuit 81 in the power supply line LN1, a drain connected to the second coil L2, and a gate connected to the second coil L2. A constant current control circuit 85 is connected. Further, the second diode D2 is connected between the ground line LN2 and the connection midpoint of the drain of the MOS FET 83 and the second coil L2 in the power supply line LN1.

  The constant current control circuit 85 acquires the voltages at both terminals of the current detection resistor R6, and the voltage difference between these two voltages is a value designated by the charge command signal among a plurality of predetermined reference values. The MOS FET 83 is turned on / off at a high frequency so that Specifically, when the signal level of the charge instruction signal is a logic “1” level, the constant current control circuit 85 turns on the MOS FET 83 (on / off at a high frequency), and the signal level of the discharge command signal is a logic “1”. At the “0” level, the MOS FET 83 is turned off. As a result, the output current of the boosting unit 70 is controlled to a current value specified by the charge command signal in the constant current unit 71, and this is supplied to the battery unit 19 as a charging current. The constant current control circuit 85 obtains the current value of the charging current based on the voltage difference between both terminals of the current detection resistor R6, and transmits this to the CPU 55 as a charging current detection signal.

  The discharge circuit 53 includes a MOS FET 86, a fourth diode D4, and an output control circuit 87. The MOS FET 86 has a source connected to a connection midpoint between the battery group of the battery unit 52 and the power supply line LN 1, and a gate connected to the output control circuit 87. The drain of the MOS FET 86 is connected to the power input / output terminal of the battery power supply unit 17 via the fourth diode D4. Then, the output control circuit 87 starts or stops the discharge of the electric power stored in the battery 40 of the battery unit 19 by turning on / off the MOS type FET 86 based on the discharge command signal given from the CPU 55. Specifically, the output control circuit 87 turns on the MOS type FET 86 when the signal level of the discharge command signal is the logic “1” level, and the MOS type when the signal level of the discharge command signal is the logic “0” level. The FET 86 is turned off.

  The auxiliary power supply unit 54 supplies power to the CPU 55 by increasing or decreasing the drive voltage supplied from the AC / DC converter 16 of the power supply unit 4 via the power supply line LN1 to a predetermined voltage.

  The CPU 55 monitors the presence or absence of a power failure based on the voltage detection signal provided from the power failure detection voltage sensor 61 of the input circuit 50. For example, when detecting the occurrence of a power failure, the CPU 55 turns on the MOS FET 86 by raising the signal level of the discharge command signal to the logic “1” level, thereby starting the discharge from the battery unit 19. After that, when the CPU 55 detects power recovery from the power failure based on the voltage detection signal, the CPU 55 turns off the MOS FET 86 by lowering the signal level of the discharge command signal to the logic “0” level, thereby The discharge from the unit 19 is stopped.

  Further, the CPU 55 monitors the output voltage in the battery unit 19 based on the battery voltage detection signal given from the battery voltage sensor 41 of the battery unit 19, and when the output voltage of the battery unit 19 becomes a predetermined voltage or less, for example, charging is performed. The MOS type FETs 80 and 83 are turned on by raising the signal level of the command signal to the logic “1” level, thereby starting the charging of the battery unit 19 to the battery 40.

  Furthermore, CPU55 monitors the temperature of the battery 40 of the battery part 19 based on the battery temperature detection signal given from the battery temperature sensor 42 of the battery part 19, and when the said temperature exceeds predetermined predetermined temperature, The MOS FETs 80 and 83 are turned off by lowering the signal level of the charge command signal to the logic “0” level, thereby stopping the charging of the battery unit 19 to the battery 40.

  Further, the CPU 55 monitors the charged amount of the battery 40 of the battery unit 19 based on the charging current detection signal provided from the charging circuit 51 and the discharge current detection signal provided from the discharge current sensor 43 of the battery unit 19. Specifically, the CPU 55 calculates the amount of power stored in the battery unit 19 by subtracting the current value of the discharge current and the time integration result from the current value of the charging current and the time integration result. Then, the CPU 55 turns on the MOS FETs 80 and 83 by raising the signal level of the charge command signal to the logic “1” level as necessary based on the charged amount of the battery unit 19, thereby Start charging.

(2) Charging Control Processing According to the Present Embodiment Next, the charging control function according to the present embodiment installed in the storage device 1 will be described. The storage device 1 rapidly charges the battery 40 of the battery unit 19 of the power supply unit 4 with a high current in accordance with the amount of data held in the cache memory unit 13 of the control unit 3 (FIG. 1). One of the features is that a charge control function is mounted to switch between rapid charging to be performed and low-speed charging to be performed at low speed with low current.

  In this case, the storage device 1 controls the charging current to be a low current on average by applying a pulsed charging current to the battery 40 of the battery unit 19 during the low-speed charging.

  In addition, the storage device 1 responds to a write request from the host device when the amount of power stored in the battery unit 19 is less than the amount of power required to back up all data held in the cache memory unit 13. Another feature is that a light performance limiting function for limiting the light performance is installed.

  In practice, the CPU 55 (FIG. 3) of the charge / discharge control unit 20 of the battery power supply unit 17 makes each volatile memory 30 of the cache memory unit 13 to the memory controller 31 of the cache memory unit 13 as shown in FIG. 4. Are periodically inquired about the total amount of data stored therein (SP1, SP3, SP5,...).

  Further, in response to such an inquiry, the memory controller 31 of the cache memory unit 13 notifies the CPU 55 of the total data amount as cache data amount information (SP2, SP4, SP6,...).

  On the other hand, as shown in FIGS. 5A to 5C, the CPU 55 raises the signal level of the charge command signal to the logic “1” level when the storage apparatus 1 is started, and the amount of stored power is a predetermined value. The battery 40 of the battery unit 19 is rapidly charged with a constant high current (for example, 1 [A]) until it reaches (for example, 90% of the full charge) (time t0 to time t1).

  Thereafter, the CPU 55 repeatedly raises the signal level of the charge command signal to the logic “1” level for, for example, one minute, and then lowers the signal level to the logic “0” level for the next two minutes. The signal level of is changed in pulses. Thus, the CPU 55 causes the battery 40 to perform low-speed charging with a low current (for example, the average is 0.3 [A]) until the battery 40 is fully charged (time t1 to time t2).

  Further, when the battery 40 is fully charged (time t2), the CPU 55 stops the charging by lowering the signal level of the charge command signal to the logic “1” level, and thereafter, the discharge current sensor 43 ( Based on the discharge current detection signal given from FIG. 3), the charged amount of the battery unit 19 is monitored (time t2 to time t3).

  Further, during this time, the CPU 55, based on the cache data amount information given from the memory controller 31 of the cache memory unit 13, stores all the data stored in each volatile memory 30 of the cache memory unit 13 at that time in the data backup unit 32. The amount of power required for saving to (see FIG. 2) is obtained (hereinafter referred to as the required power amount for backup). Then, the CPU 55 compares the current storage amount of the battery unit 19 obtained as described above with the current required power amount during backup.

  Then, the CPU 55 changes the signal level of the charge command signal in a pulsed manner at the timing when the amount of power stored in the battery unit 19 falls below the required power amount at the time of backup, so that the battery 40 of the battery unit 19 is changed. The battery 40 is charged at a low speed (time t3 to time t4), and when the battery 40 eventually becomes fully charged, the signal level of the charge command signal is lowered to the logic “1” level to charge the battery 40. Is paused (time t4).

  Then, when the CPU 55 eventually detects the occurrence of a power failure based on the voltage detection signal given from the input circuit 50 (FIG. 3), the battery unit 19 raises the signal level of the discharge command signal to the logic “1” level. Discharge from the battery 40 is started (time t4). When the CPU 55 receives a notification from the memory controller 31 of the cache memory unit 13 that data saving from the volatile memory 30 to the data backup unit 32 has been completed, the signal level of the discharge command signal is changed to a logical “ The discharge is stopped by falling to the “0” level (time t5).

  Further, the CPU 55 thereafter detects the power recovery from the power failure based on the voltage detection signal given from the input circuit 50 (FIG. 3), thereby raising the signal level of the charge command signal to the logic “1” level. Rapid charging with a high current is started for the battery of the battery unit 19 (time t6). At this time, the memory controller 31 of the cache memory unit 13 executes processing for returning the data saved in the data backup unit 32 to the volatile memory 30 when a power failure occurs.

  Further, the CPU 55 resumes the process of inquiring the cache memory unit 13 about the total amount of data stored in each volatile memory 30. Then, the CPU 55 obtains the current required power amount at the time of backup based on the cache data amount information transmitted from the cache memory unit 13, and performs rapid charging with a high current until the charged amount of the battery unit 19 becomes the required power amount at the time of backup. Execute (time t6 to time t7).

  Further, the CPU 55 eventually switches the charging mode to low-speed charging with a low current by changing the signal level of the charging command signal in the above-described pulse shape when the charged amount of the battery unit 19 exceeds the required power amount at the time of backup. Thereafter, low speed charging is performed until the battery 40 of the battery unit 19 is fully charged (time t7 to time t8).

  Next, when the battery 40 of the battery unit 19 is fully charged, the CPU 55 stops charging the battery 40 by lowering the signal level of the charge command signal to the logic “0” level (time t8).

  Thereafter, the CPU 55 monitors the current charged amount of the battery unit 19 based on the voltage detection signal given from the battery unit 19 in the same manner as at time t2 to time t3. In addition to this, the CPU 55 obtains the current required power amount for backup based on the cache data amount information given from the cache memory unit 13. Then, the CPU 55 compares the current storage amount of the battery unit 19 obtained as described above with the required power amount during backup (time t8 to time t9).

  Then, the CPU 55 eventually transmits the above-described pulsed charge command signal to the charging circuit 51 at a timing when the amount of power stored in the battery unit 19 falls below the required power amount at the time of backup, thereby reducing the battery 40 of the battery unit 19. Low-speed charging with current is started (time t9), and then the above-described control is repeated for time t7 to time t9.

  As a means for realizing the charge control processing based on the charge control function according to the present embodiment as described above, the CPU 55 holds a backup required power amount conversion table 90 as shown in FIG.

  The backup required power amount conversion table 90 is a table used by the CPU 55 to convert the backup required power amount with respect to the total data amount stored in each volatile memory 30 of the cache memory unit 13. 6, the data amount column 90A and the backup-time required power amount column 90B are configured.

  In the data amount column 90A, the total amount of data stored in each volatile memory 30 of the cache memory unit 13 is sequentially stored, for example, in increments of a predetermined data amount, and in the backup necessary power amount column 90B, The amount of power required for backing up the data of the corresponding data amount, which is obtained in advance by calculation or actual measurement, from the volatile memory 30 to the data backup unit 32 (FIG. 2) is stored.

  Therefore, for example, in FIG. 6, when the total amount of data stored in each volatile memory 30 of the cache memory unit 13 is “10 to 20” [GB], the power amount of “BB” [W] is On the other hand, when the total data amount is “20 to 30” [GB], it is indicated that the power amount of “CC” [W] is necessary.

(3) CPU processing related to charge control processing according to the present embodiment Next, the CPU 55 (FIG. 3) and the cache memory unit 13 of the charge / discharge control unit 20 (FIG. 1) related to the charge control processing according to the present embodiment. Specific processing contents of the memory controller 31 (FIG. 2) of FIG. 1 will be described.

(3-2) First Charging Control Process FIG. 7 shows the specifics of the CPU 55 in the charging control process based on the charging control function according to the present embodiment at the initial startup of the storage apparatus 1 or at the time of power recovery from a power failure. The processing contents are shown.

  The CPU 55 starts the first charging control process when the storage device 1 is initially activated or recovers from a power failure, and first determines whether or not the current activation is at the initial activation (SP10). If the CPU 55 obtains an affirmative result in this determination, it raises the signal level of the charge command signal to a logic “1” level, thereby causing the battery 40 of the battery unit 19 to perform rapid charging with a high current (SP12). ).

  Then, the CPU 55 thereafter ends the rapid charging based on the charging current detection signal given from the charging circuit 51 (here, the charged amount of the battery 40 of the battery unit 19 is 90% of the full charge). (SP13), and when it is confirmed that the state in which quick charging is to be terminated is reached, the process proceeds to step SP14.

  On the other hand, if the CPU 55 obtains a negative result in the determination at step SP10, the charged amount of the battery unit 19 is determined based on the cache data amount information provided from the memory controller 31 of the cache memory unit 13, and the required power amount at the time of backup. Is determined (SP11).

  If the CPU 55 obtains a negative result in this determination, it proceeds to step SP12. If it obtains an affirmative result, the CPU 55 changes the signal level of the charge command signal in a pulsed manner to the battery 40 of the battery unit 19. On the other hand, low-speed charging with a low current is performed (SP14).

  Subsequently, the CPU 55 waits for the battery 40 of the battery unit 19 to be fully charged based on the charging current detection signal from the charging circuit 51 (SP15). The charging of the battery unit 19 to the battery 40 is suspended by lowering the charging command signal to the logic “0” level (SP16).

  After that, the CPU 55 periodically inquires the cache memory unit 13 about the total amount of data stored in each volatile memory 30 of the cache memory unit 13, and the battery unit 19 requires the required power amount at the time of backup. It is constantly monitored whether or not the power is secured (SP17). Then, the CPU 55 eventually returns to step SP14 at a timing when the amount of power stored in the battery unit 19 falls below the required power amount at the time of backup due to natural discharge or the like in the battery unit 19, and thereafter repeats the processing of step SP14 to step SP17.

(3-3) Second Charging Control Processing On the other hand, FIG. 8 shows specific processing contents of the CPU 55 when the battery 40 of the battery unit 19 is charged or when charging is suspended.

  When the CPU 55 starts charging the battery 40 of the battery unit 19 or stops the charging, the CPU 55 starts the second charging control process. First, based on the voltage detection signal given from the power failure detection voltage sensor 61, The presence or absence of a power failure is monitored (SP20).

  When the CPU 55 eventually detects the occurrence of a power failure, it raises the signal level of the discharge command signal to the logic “1” level to turn on the MOS FET 86 and start discharging from the battery unit 19 (SP21). As a result, the discharge current is supplied to the cache memory unit 13 as a drive current via the DC / DC converter 15 (FIG. 1). Then, the memory controller 31 (FIG. 2) of the cache memory unit 13 is driven based on the discharge current, and the data stored in the volatile memory 30 is saved in the data backup unit 32 (FIG. 2).

  Next, the CPU 55 determines whether or not a notification indicating that the backup has been completed is received from the memory controller 31 of the cache memory unit 13 after completion of the data backup (SP22). Then, it is determined whether or not an instruction (discharge stop instruction) to stop the discharge is given from the controller 12 of the storage apparatus 1 (SP23).

  If the CPU 55 obtains a negative result in this determination, it determines whether or not the current charged amount of the battery unit 19 has reached a predetermined voltage (discharge end voltage) (SP24). If the CPU 55 obtains a negative result in this determination, it determines whether or not power has been restored based on the voltage detection signal provided from the power failure detection voltage sensor 61 of the input circuit 50 (SP25).

  Further, when the CPU 55 obtains a negative result in this determination, it returns to step SP22, and thereafter repeats the loop of step SP22 to step SP25 until an affirmative result is obtained at step SP22, step SP23, step SP24 or step SP25.

  When the CPU 55 eventually obtains an affirmative result in any of step SP22, step SP23, step SP24 or step SP25, it turns off the MOS FET 86 by lowering the signal level of the discharge command signal to the logic “0” level ( SP28). As a result, the discharge from the battery unit 19 is stopped, and the supply of the drive current to the cache memory unit 13 is stopped. Then, the CPU 55 executes a predetermined shutdown process (SP29), and thereafter ends the second charge control process.

(3-4) Write Performance Restriction Processing On the other hand, FIG. 9 shows a processing procedure of write performance restriction processing executed by the memory controller 31 of the cache memory unit 13 regarding the write performance restriction function.

  When the power to the storage device 1 is turned on, the memory controller 31 starts this write performance restriction process. First, the CPU 55 of the battery power supply unit 17 (FIG. 1) supplies the required amount of power during backup to the battery. An inquiry is made as to whether or not electricity is stored in the unit 19 (SP30).

  The memory controller 31 determines whether or not the write performance is currently limited when the amount of power required for backup is not stored in the battery unit 19 (SP31). If the memory controller 31 obtains a positive result in this determination, it returns to step SP30. If it obtains a negative result, it requests the controller 12 (FIG. 1) to limit the write performance. Thus, in response to this request, the controller 12 limits the write performance, for example, by not accepting a part of the write request from the host device or delaying the response to the write request. Then, the memory controller 31 returns to step SP30.

  On the other hand, if the memory controller 31 obtains a positive result in the determination at step SP30, it determines whether the write performance is currently limited (SP33). If the memory controller 31 obtains a positive result in this determination, it returns to step SP30, and if it obtains a negative result, it requests the controller 12 to release the restriction on the write performance. Thus, the controller 12 releases the restriction on the write performance in response to this request. Then, the memory controller 31 returns to step SP30.

(4) Effects of the present embodiment As described above, in the present embodiment, at the time of power recovery after a power failure, the total amount of data stored in the cache memory unit 13 and the battery of the battery unit 19 at that time 40, when the amount of electricity stored in the battery unit 19 is lower than the required power amount at the time of backup, rapid charging is performed with a high current. If it exceeds, charge at low speed with low current is performed.

  Therefore, according to the storage device 1, as shown in FIG. 5D, the amount of power stored in the battery 40 of the battery unit 19 is small, and the period during which data backup cannot be guaranteed is suppressed to a short period by rapid charging, while generating heat. Near full charge with a large amount, the amount of heat generated by the battery 40 can be suppressed by low-speed charging. As a result, a highly reliable storage apparatus that can reliably guarantee data against power failure while suppressing heat generation of the battery 40 can be realized.

  Further, according to the present storage device 1, since a low current is formed by making the charging current into a pulse shape, for example, the battery 40 with a low current separately from the charging circuit 51 that charges the battery 40 with a high current. It is not necessary to provide a charging circuit for charging the battery, and the complication of the configuration of the entire system can be prevented accordingly.

(5) Other Embodiments In the above-described embodiment, the case where the battery power supply unit 17 is configured as shown in FIG. 3 has been described. However, the present invention is not limited to this, and various other types are also described. The configuration can be widely applied.

  Further, in the above-described embodiment, the case where the data backup unit 32 as a backup destination of data stored in the volatile memory 30 of the cache memory unit 13 is configured by a nonvolatile memory at the time of a power failure has been described. However, the present invention is not limited to this. For example, the data backup unit 32 may be configured from a nonvolatile storage medium such as a hard disk or an optical disk. Further, a specific logical volume created on a storage area provided by the storage device 10 may be used as a backup destination.

  Furthermore, in the above-described embodiment, the amount of power required to back up the data stored in the volatile memory 30 of the cache memory unit 13 to the data backup unit 32 is converted into the amount of power required for backup described above with reference to FIG. Although the case of obtaining with reference to the table 90 has been described, the present invention is not limited to this. For example, it may be obtained by calculation using a predetermined arithmetic expression. Various other ways of obtaining can be widely applied.

  The present invention can be widely applied to storage apparatuses equipped with a backup function during a power failure that saves data stored in a cache memory to a nonvolatile storage medium when a power failure occurs.

  DESCRIPTION OF SYMBOLS 1 ... Storage apparatus, 3 ... Control part, 4 ... Power supply part, 10 ... Storage device, 13 ... Cache memory part, 17 ... Battery power supply part, 19 ... Battery part, 20 ... Charge-discharge control , 30... Volatile memory, 31... Memory controller, 32... Data backup unit, 50... Input circuit, 51.

Claims (8)

A storage device unit having one or a plurality of storage devices, a cache memory unit that temporarily stores data to be read and written in a storage area provided by the storage device, a control unit that controls reading and writing of data to the storage device, In a storage device having a battery power supply unit that supplies driving power to the cache memory unit during a power failure,
The cache memory unit
A volatile memory for temporarily storing data to be read and written in a storage area provided by the storage device;
A non-volatile storage medium for temporarily backing up the data stored in the volatile memory;
A memory controller for controlling reading and writing of data to and from the volatile memory, and for saving data stored in the volatile memory to the nonvolatile storage medium as necessary,
The battery power supply is
Battery,
A charge / discharge control unit for controlling charge / discharge of the battery,
The charge / discharge control unit
To obtain the total amount of data stored in the volatile memory notified from the memory controller after power recovery from a power failure, and to back up all the data from the volatile memory to the nonvolatile storage medium After charging the battery until the battery is charged with the amount of power required for charging, and charging the battery with the power of the amount of power, the charging current is lower than that during the quick charge. The storage device is characterized in that the battery is charged at a low speed. The charge / discharge control unit
The battery is rapidly charged by applying a charging current having a constant current value during the rapid charging, and the battery is charged slowly by applying a pulsed charging current during the low-speed charging. The storage device according to claim 1. The charge / discharge control unit
The initial charge of the storage device is performed by rapidly charging the battery until a predetermined amount of electric power is charged, and after charging the battery with the predetermined amount of electric power, the battery is charged at a low speed. The storage apparatus according to 1. The memory controller is
When the amount of power required to back up all data stored in the volatile memory of the cache memory unit to the nonvolatile storage medium is not stored in the battery, the write performance for the write request from the host device is The storage apparatus according to claim 1, wherein the storage apparatus is limited. A storage device unit having one or a plurality of storage devices, a cache memory unit that temporarily stores data to be read and written in a storage area provided by the storage device, a control unit that controls reading and writing of data to the storage device, In a charging control method in a storage device having a battery power supply unit that supplies driving power to the cache memory unit during a power failure,
The cache memory unit
A volatile memory for temporarily storing data to be read and written in a storage area provided by the storage device;
A non-volatile storage medium for temporarily backing up the data stored in the volatile memory;
A memory controller for controlling reading and writing of data to and from the volatile memory, and for saving data stored in the volatile memory to the nonvolatile storage medium as necessary,
The battery power supply is
Battery,
A charge / discharge control unit for controlling charge / discharge of the battery,
A first step in which the charge / discharge control unit acquires the total amount of data stored in the volatile memory notified from the memory controller after power recovery from a power failure;
A second step in which the charge / discharge control unit obtains an amount of power required to back up all data stored in the volatile memory from the volatile memory to the nonvolatile storage medium;
The charge / discharge control unit rapidly charges the battery until the battery is charged with the amount of power, and after charging the battery with the amount of power, the charging current is lower than that during the quick charge. A charge control method comprising: a third step of charging the battery at a low speed. In the third step, the charge / discharge control unit includes:
The battery is rapidly charged by applying a charging current having a constant current value during the rapid charging, and the battery is charged at low speed by applying a pulsed charging current during the low-speed charging. The charge control method according to claim 5. In the third step, the charge / discharge control unit includes:
The initial charge of the storage device is performed by rapidly charging the battery until a predetermined amount of electric power is charged, and after charging the battery with the predetermined amount of electric power, the battery is charged at a low speed. 5. The charge control method according to 5. In the third step, the memory controller
When the amount of power required to back up all data stored in the volatile memory of the cache memory unit to the nonvolatile storage medium is not stored in the battery, the write performance for the write request from the host device is The charge control method according to claim 5, wherein the charge control method is limited.

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